Modeling nd Control of Six-Swith Single-Phse Inverter Christopher. Smith Thesis sumitted to the Fulty of the irgini Polytehni Institute nd Stte University in prtil fulfillment of the requirements for the degree of MASTERS OF SCIENCE in Eletril Engineering Approved: Json i, Chirmn Dougls Nelson Willim Bumnn August 5, 2005 Blksurg, A Keywords: single-phse inverter, trnsient performne, power eletronis, sixswith, stte spe ontrol Permission is given to opy this work provided redit is given nd opies re not intended for sle. Use or inlusion of ny portion of this ETD in work intended for ommeril use will require lerne y the opyright owner. Copyright 2005, Christopher Smith
Modeling nd Control of Six-Swith Single-Phse Inverter Astrt y Christopher. Smith Eletril Engineering Distriuted genertion for onsumer pplitions is reltively new field nd it is diffiult to stisfy oth ost nd performne trgets. High expettions oupled with extreme ost utting to ompete with trditionl tehnologies mke onverter design diffiult. As power eletronis mture more opportunities rise for entry into this lurtive re. An exellent understnding of onverter dynmis is ruil in produing well performing nd ost ompetitive system. The six-swith single-phse inverter proposed in this thesis is prime ndidte for use in single households nd smll usinesses. Its ompt size nd omptiility with existing eletril stndrds mke its integrtion esy. However, little work is ville on hrterizing the system from ontrols point of view. In prtiulr lning the two outputs with n uneven lod is onern. This thesis uses nodl nd loop nlysis to formulte mthemtil model of the six-swith single-phse inverter. A non-liner time invrint model is onstruted for iruit simultion; detils found in rel iruits re dded. A hrdwre-in-the-loop (HI) onfigurtion is used for more urte simultion. In ft, its use mkes for n lmost semless trnsition etween simultion nd hrdwre experimenttion. A detiled explntion of the HI system developed is presented. The system is simulted under vrious lod onditions. Uneven lods nd lightly loded onditions re thoroughly exmined. Controllers re verified in simultion nd then re tested on rel hrdwre using the HI system. DC us disturne rejetion nd non-liner lods re lso investigted. Aeptle inverter performne is demonstrted without expensive urrent sensors or high smpling frequeny. Copyright 2005, Christopher Smith
Aknowledgements I would like to express grtitude towrds numer of individuls nd orgniztions tht hve helped me in hoosing my reer pth nd growing s n engineer. Without their help I would still e hopelessly torn etween severl ppeling fields. First, I would like to thnk my fmily who lwys pushed me to do my est, work through things, nd ongrtulted my hievements. I would like to thnk my friends whose interesting ides nd omi relief hs helped mke it through the diffiult times. I would like to thnk Dr. Json i whose trust nd wisdom hs helped me lern lot out power eletronis. His hnds on pproh nd willingness help out on moments notie were extremely vlule in mny situtions. His insistene on rel iruits hs tught me muh tht I would hve otherwise missed. I would like to thnk Dr. Doug Nelson nd the Hyrid Eletri ehile Tem who got me strted in power eletronis. Dr. Nelson s work with the group hs helped numerous students find out how things relly work. Steve Gurski, Mike Ogurn, nd ountless others oth kept me entertined nd pushed me forwrd. I would like to thnk the other grdute students t Dr. i s Future Energy Eletronis : Elton Pep, Dmion Uriuoli, Jeremy Ferrell, Troy Nergrd, eonrd eslie, Amy Johnson, Andy Mndrih, Mike Shenk, Huijie Yu, Xudong Hung, Chngrong iu. As well, I would like to thnk Jerry Frnis who ws lwys willing to help out even if he didn t hve the nswer, yet. Also, I would like to thnk Mike Gilliom. Without his extensive help I would not hve een le to develop the hrdwre in the loop system shown in Chpter 3. In ft, the sensor nd power ord ws lmost entirely designed y Mike. In ddition, I would like to thnk Dr. Willim Bumnn whose ptiene helped me mke somewht lte entry into the ontrols field. stly, I would like to thnk Firhild Controls whose mens helped extensively in finishing this work, nd Jeff Grhm, whose persistene helped me see the projet through. Copyright 2005, Christopher Smith III
Tle of Contents Astrt...II Tle of Contents... I ist of Figures... Chpter - Introdution..... Bkground....2. Ciruit Topology Overview... 4.3. Controller Overview... 6 Chpter 2 - Theoretil Anlysis... 9 2.. System Formultion... 9 2.2. System Anlysis... 2 2.3. Deoupling... 8 Chpter 3 - Hrdwre Setup: Rpid Prototype System... 20 3.. Overview... 20 3.2. Power Interfe Bord (PIB)... 2 3.3. Controller... 29 3.4. Power System nd Sensors... 3 3.5. User Interfe... 33 3.6. Summry... 34 Chpter 4 - Ciruit Simultion nd Hrdwre Experimenttion... 36 4.. Plnt Model... 36 4.2. Controller... 39 Chpter 5 - Conlusion... 56 Appendix A, MATAB work files... 58 Referenes... 6 it... 65 Copyright 2005, Christopher Smith I
ist of Figures Figure. Typil single-phse three-wire trnsformer... 2 Figure 2. ow voltge power soures need step up voltge trnsition.... 3 Figure 3. Unlned opertion nd lned opertion.... 3 Figure 4. The split pitor H-ridge.... 4 Figure 5. Six-swith three-wire inverter.... 5 Figure 6. Inverter verge model.... 9 Figure 7. Input to N ode plots.... 2 Figure 8. Input to 2N ode plots.... 3 Figure 9. Input to I ode plots.... 4 Figure 0. Inputs to I ode plots.... 5 Figure. Inputs to I ode plots.... 6 Figure 2. Inverter system with hnging 0D us voltge.... 7 Figure 3. Deoupling Mtrix.... 9 Figure 4. The HI system digrm.... 2 Figure 5. The ssemled HI system.... 2 Figure 6. A piture of the tul PIB.... 22 Figure 7. PIB system digrm.... 22 Figure 8. Internl FPGA shemti.... 24 Figure 9. The ECP setion...... 25 Figure 20. A typil dt trnsfer yle.... 25 Figure 2. The PWM setion.... 26 Figure 22. The SPI setion.... 27 Figure 23. The FIFO setion.... 28 Figure 24. The isolted gte drive power supply.... 29 Figure 25. The dt exhnge yle.... 3 Figure 26. Power Bord Topology nd Sensors.... 3 Figure 27. The power ord.... 32 Figure 28. Isolted high voltge sensors.... 33 Figure 29. A omprison of the xpc trget sope nd rel sope pture... 34 Figure 30. The Simulink Plnt Model.... 37 Copyright 2005, Christopher Smith
Figure 3. Plnt input non-linerrities.... 38 Figure 32. Plnt model.... 38 Figure 33. Complete System.... 39 Figure 34. d diff to diff root lous.... 4 Figure 35. diff ontroller simultion.... 42 Figure 36. diff ontroller experimenttion.... 43 Figure 37. Unevenly loded system simultion.... 44 Figure 38. Unevenly loded experimenttion run.... 45 Figure 39. d omm to diff root lous.... 46 Figure 40. d diff ode plot nd root lous.... 47 Figure 4. d diff detiled root lous.... 48 Figure 42. Closed loop ode nd step response.... 49 Figure 43. Simultion of oth diff nd om.... 50 Figure 44. Experimenttion using oth diff nd om ontrollers.... 50 Figure 45. Unhrged retifier simultion.... 5 Figure 46. Unhrged retifier experimenttion.... 52 Figure 47. Feed forwrd ontroller.... 53 Figure 48. Feed forwrd ontroller simultion.... 53 Figure 49. Feed forwrd ontroller experimenttion.... 54 Copyright 2005, Christopher Smith I
Chpter - Introdution Generting len AC power for household nd smll usiness use is on the rise [25]. Systems suh s Uninterruptile Power Supplies (UPS), AC power genertors, nd tive filter line onditioners re just few exmples of power eletroni systems tht mke use of some type of inverter iruit. As with ny onsumer pplition, eonomi onerns ply lrge ftor in system design. With the rise of omputer proessing power, omplex ontrol is used s tool to derese overll system ost. This work presents six-swith inverter, hrdwre-in-the-loop (HI) ontrol system, nd severl system ontroller designs. The ontrollers re evluted in simultion nd then with tul hrdwre. The power onverter system ws designed to e highly ost effetive. The ontroller solution ws designed to provide mximum design flexiility. The omined system llows the est performne with the use of inexpensive omponents... Bkground The inverter used in this work ws designed to power typil residentil or smll usiness site. Stndlone power soures suh s fuel ell, miro turine, or solr ells ould provide the power. As mentioned in [6] single-phse three-wire output should e dopted euse this is the stndrd prtie for home onnetion to the grid. In typil utility system single-phse from the three-phse high voltge ville t the pole is down onverted to 20/240 with enter-tpped trnsformer s in Figure. Copyright 2005, Christopher Smith
Utility Grid Trnsformer To Home 20 240 Differentil oltge 2 20 Figure. Typil single-phse three-wire trnsformer. This type of trnsformer is used y utility ompnies to interfe single phse of the grid voltge to single-phse three-wire setup used in residentil systems. The single-phse three-wire pproh is used for severl resons. First, it llows the onsumer two seprte voltge levels: 20 for smller devies, 240 for lrger pplines nd HAC systems. Seondly, it offers twie the lod pity with only.5 times the ondutors [7]. To fit the existing systems the inverter designed will need single-phse three-wire output. One importnt item to note is tht mny power soures suh s fuel ells do not provide high voltge output. Therefore severl stges my e required. The first option would e to design stndrd single-phse inverter nd ouple it to the home with enter-tpped trnsformer similr to tht shown in Figure. The turns rtio my e djusted to step up the voltge, see Figure 2. While this pproh is well estlished the use of the 60 Hz trnsformer dds ost, size, nd ineffiieny to the system [7], [27]. There re lso issues with voltge regultion nd no possiility to tie the inverter to the grid. Additionlly, most distriuted systems hve DC output nd would not diretly onnet to the inverter. The seond pproh is to use DC-DC whih steps up the voltge nd then n inverter tht diretly genertes oth 20 outputs, nd 2, lso in Figure 2. Copyright 2005, Christopher Smith 2
ow oltge High oltge Fuel Cell DC-AC od Fuel Cell DC-DC DC-AC od Figure 2. ow voltge power soures need step up voltge trnsition. The top system uses 60 Hz trnsformer to mke the stop from low voltge to high voltge. The lower system uses high frequeny trnsformer or DC/DC to form high voltge us. Mny possile topologies exist ut few re ommerilly prtil nd resonly ontrollle for high power onverter [27]. One ommonly used topology is stndrd H- ridge inverter. This topology will work in lned se ut when the lod is unlned it ts s voltge divider ross the 240. The result is depited in Figure 3. When the lods re unlned nd 2 re skewed so tht neither output hs the orret voltge. = 237.6 = 20 k Ohm k Ohm 240 240 0 Ohm.99 I 0 Ohm () 2 = 2.4 () 2 = 20 Figure 3. Unlned opertion nd lned opertion. In () the system is unlned due to voltge divider effet. In () urrent soure is dded whih lnes the output voltge. One solution is to form two voltge soures nd run the inverter from those, see Figure 4. This option hs severl prolems. First, it requires two regulted soures. This further omplites the power soure. One option is to use one voltge soure nd split the us with two pitors. This n work with light lods ut under extreme unlnes the pitors re not stiff enough to mintin the proper regultion. If the pitors re not dequtely overrted this Copyright 2005, Christopher Smith 3
n even dmge the pitors. The ddition of ontrolled urrent soure n lso lne the output, s in Figure 3. A new topology is needed to form the urrent soure. + d P I C N I - 0 I C 2 2 Figure 4. The split pitor H-ridge. The split pitors re used to form loosely regulted enter point to lne the output voltges..2. Ciruit Topology Overview This six-swith inverter uses two dditionl swithes nd n indutor to form ontrollle urrent soure. The inverter is shown in Figure 5 nd its prmeters re summrized in Tle. The six-swith inverter is very similr to six-swith inverter used in three-phse pplitions exept tht the enter leg is onneted to ground insted of phse of the output with pitor. Three-phse four-wire systems lso use similr topology. They lso hve n extr phse leg for totl of 4 phse legs [28]. The extr phse leg ontrols neutrl urrent. Copyright 2005, Christopher Smith 4
+ d Phse A B C P I C N I - 0 I C 2 2 Figure 5. Six-swith three-wire inverter. An dditionl enter leg forms urrent soure whih if ontrolled orretly n lne the output voltges during n unevenly loded ondition. Tle. Importnt iruit prmeters. Ciruit Element esr C DC f s Mx Power lue 30 uh 20 mω 60 uf 400 0 khz 0 kw An inresed numer of swithes is n ovious disdvntge of this system. However, the extr two swithes llow urrent soure injetion. This extr ontrollility is le to lne n uneven lod. In generl, phse A nd C swithes ontrol the differentil voltge while phse B swithes ontrol the lne etween the nd 2, the ommon voltge. This work will onentrte on the ontrol of these two system vriles, the ommon mode voltge nd the differentil mode voltge. Copyright 2005, Christopher Smith 5
.3. Controller Overview The intent of the ontroller is to hieve the highest performne out of the most eonomil system. Generlly speking the highest performne mens low totl hrmoni distortion (THD) of the sinusoidl output. Output impedne for ny type of voltge soure is lwys importnt. Here low output impedne insures tht the output wveform will exhiit low THD nd urte RMS voltge vlue under vriety of lod onditions [22]. Output filter seletion is n importnt prt of the system design. A smller output filter provides lower output impedne, ut t the expense of higher hrmonis nd distortion due to voltge ripple from indequte ttenution of the swithing frequeny [9], [7]. In generl voltge soure would e etter with lrger pitor t the output, ut pek IGBT urrents neessitte the need for resonly sized output indutor. The simplest wy to ontrol the inverter is s n open-loop system. The PWM modultor is fed sine wve referene, nd enodes the referene into the gte signls. In stedy stte with liner lod this ontrol tehnique produes the est possile wveform. For the single-phse thee-wire inverter the phse A nd phse C swith pirs reeive omplementry duty yles, nd the enter phse n e modulted t 50 perent duty yle ontinully. This type of ontrol is suseptile to two min prolems. First, if the output indutor s impedne is signifint ompred to the lod impedne (t the fundmentl frequeny) there is signifint drop ross the indutor. An inresing lod retes more drop ross the indutor nd less output voltge. Seond, there is no onsidertion for hnging DC us voltge. Most forms of rw power ren t prtiulrly well regulted [27]. Solr, turine, fuel ell, flywheel, nd genertor soures exhiit vrying output voltge. A power supply s ility to rejet disturne on its input voltge is known s udiosuseptiility []. The disturne n rnge from low frequeny sg used y loding down the DC power soure to reltively high frequeny (20 Hz nd higher) ripple used y retifying n AC soure. A simple solution to the prolems listed ove is to employ reltively slow feedk mehnism. The RMS voltge of the output wveform is lulted nd then fed k round through n integrtor. ow frequeny disturnes in the input or output voltge re ompensted. This ontrol strtegy tkes severl yles to hndle disturne, ut mintins good verge vlue on the output wveform. This type of ontroller n e esily implemented Copyright 2005, Christopher Smith 6
with nlog omponents s stndrd proportionl-integrl (PI) ontroller. Some nlog ontrollers even employ feed-forwrd ompenstion to ount for quikly hnging DC us voltge [6]. Anlog PI ontrollers hve ttempted to follow sine wve referene, ut due to the high gin neessry to mintin trking usully eome unstle t light lod [2]. A lightly loded inverter hs no dmping nd forms high Q network, whih esily resontes. Dul nested loop systems hve proved useful in resonnt situtions. A urrent sensor is used to sense the indutor urrent. A losed-loop urrent ontroller n e losed t higher frequeny due to the ft tht from duty yle to indutor urrent the plnt is only first order system. The indutor urrent referene is reted y the outer voltge loop. Closed loop urrent ontrol is vlule ut often eonomi onerns prohiit the tul urrent sensor. The inresed flexiility of digitl ontroller hs mny enefits in n inverter system. More omplex ontrollers n e implemented. Pole zero nelltion with pole plement n e used to shpe the system for the desired response. Multiple input multiple output (MIMO) ontrollers nd stte spe systems re esier to implement. Non-liner type ontrollers re lso esier to implement. Multipliers used in ontrol loops re often diffiult in n nlog system. Optiml ontrollers suh s dedet ontrollers must use smpled ontroller. Oserver sed systems re lso usully implemented in omintion with digitl ontroller. Finlly, digitl ontrollers hve dded vlue in tht miroproessor or DSP n usully lso tke re of side tsks suh s simple user interfe or ommunition interfe. The most prtil ontroller is often omintion of mny ftors. In this se the ontrollers jo is not neessrily to follow the referene, ut to hve good disturne rejetion. A redued gin t the inverter referene frequeny n e ompensted with pre-filter euse phse is not onern in stnd-lone system. The lod n e modeled s n output disturne nd the DC us ripple n e modeled s n input disturne. Systems with low input sensitivity nd low output sensitivity perform well under these disturnes. In generl sense, ontrollers with high open-loop gin hve low sensitivity funtions. As previously mentioned high gin ontrollers re diffiult to use in lightly loded system. Smpling dely ples zeros in the right hlf plne. As the gin is inresed losed-loop poles re pulled to the right hlf plne where they use the system to go unstle. Inresing the smpling frequeny oviously dereses the smpling dely. However, ontroller omputtion speed, swithing Copyright 2005, Christopher Smith 7
frequeny, nd ville nlog-to-digitl onverters (A/Ds) hold the smpling frequeny to relisti vlue. Prtilly, n importnt prt of the ontroller is how intuitive its use is. The est ontroller in the world is useless if the user n t see wht is hppening during its opertion. Items suh s inurte plnt prmeter estimtion, stte sturtion or integrtor wind-up [2], fixed-point overflow, nd other non-liner effets omplite the prtil opertion of system. Most of these items n e simulted, ut no simultion is 00% urte. Beuse of this omplited ontrollers often need djustment nd this n e troulesome. In ddition prolems suh s smpling dely restrit ontroller performne no mtter how innovtive the ontroller. Chpter 2 will over the simultion of the theoretil nlysis or mthemtil model formultion. From there, Chpter 3 will go into the HI system used nd its onstrution. Next, Chpter 4 overs the simultion nd experimenttion with the hrdwre. Finlly, Chpter 5 summrizes the ontriution nd suggests future work. Copyright 2005, Christopher Smith 8
Chpter 2 - Theoretil Anlysis 2.. System Formultion The six-swith single-phse three-wire inverter is vrint of the more ommonly known voltge soure inverter (SI). As in mny power eletronis systems estlishing n operting point to linerize round is diffiult when system prmeters re onstntly hnging. In this se the lod nd input voltge re non-onstnt. Thus the est lterntive is to use n verge model nd swith the onverter t muh higher frequeny thn ny of the other system dynmis [22]. As stted ove in Tle the swith frequeny for the inverter is 0 khz. This swithing frequeny is over n order of mgnitude higher thn the inverter s fundmentl frequeny. The verge model is derived elow using stndrd nodl nd loop nlysis nd tehniques similr to those seen in [7]. Figure 6 shows the sme system s in Figure 5 with the swithes repled with the verge model. R A 0D (S - S ) + _ I R B C N 0D (S - S ) + _ I R C C 2 2 I Figure 6. Inverter verge model. The pulse width modulted (PWM) swithes re repled with voltge soures representing their verge vlue. K: di di OD ( S S ) R + R N + 2N + = 0 () dt dt Copyright 2005, Christopher Smith 9
di di OD ( S S ) + 2 N R + R + = 0 (2) dt dt KC: Tking the derivtive of (5) gives: d N N I C = 0 (3) dt R d2 N 2 N I C2 = 0 (4) dt R 2 I I + I = 0 (5) + d( I + I dt + I ) di = 0 = dt di + dt + di dt (6) Next sustituting (6) into () nd (2) gives: di di di OD ( S S ) N + 2N R + R = 0 (7) dt dt dt di di di OD ( S S ) + 2 N R + R = 0 (8) dt dt dt To find the stte spe equtions for the system we need to define the derivtive of sttes in terms of the sttes. But first we need to define the sttes in our system. Our system hs 5 energy storge elements so it hs possiility of 5 sttes. However, in the six-swith inverter the urrents must sum to zero (5). This ft mens tht the urrents re not liner independent. Any two of the urrents n e liner independent ut not ll three. Therefore our system will hve 4 sttes: N, 2N, I, I. Equtions (7) nd (8) ontin the derivtive I nd I terms ut they must e solved efore they re useful. Krmmer s rule is used to solve for I nd I derivtive terms. First, the equtions re put in the following form, x +x 2 =. Where, x = di /dt, x 2 = di /dt. di di ( + ) + = OD ( S S ) N + 2N R + R (9) dt dt Copyright 2005, Christopher Smith 0
R R N OD S S dt di dt di + + = + + 2 ) ( ) ( (0) Finlly, the equtions re solved nd we hve: R R R DO OD OD OD N N S S S dt di + + + + + + + = ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 2 () R R R DO OD OD OD N N S S S dt di + + + + + + + = ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( 2 (2) Equtions (3), (4), (), nd (2) re used to form the stte spe equtions. The stndrd form is used. All indutor equivlent series resistor voltge drops re lso repled with the pproprite IR. Also, for simpliity Bu Ax x + = & t is defined s follows. t + + = (3) u B x A x + = & + + + = t D t D t D t D t D t D N N t t t t t t t t N N S S S ) + ( - - - ) + ( I I R R R R R R R R C C C R C R C I I 0 0 0 0 0 0 2 2 2 2 2 2 0 0 0 0 0 0 ) ( ) ( 0 0 0 & & & & (4) In this system we our onerned out regulting the inverter output voltge so our outputs re defined s N nd 2N, see (5). Alterntively, the system n lso e defined s the differene in the voltge outputs nd the ddition of the outputs s in (6). x C y = = N N N N I I 2 2 0 0 0 0 0 0 (5) Copyright 2005, Christopher Smith
diff om = 0 0 0 0 I I diff om (6) 2.2. System Anlysis The ode plots for three loding ses re shown in the following plots. One should note tht the gin from S to N is high while S to N low. S ffets oth N nd 2N. This type of symmetril pttern is followed throughout the system. As would e expeted the full lod system (lue) is hevily dmped while the no lod is very under dmped (red). Also, the gin on ll the urrent plots is hevily dependent on lod. MATAB m-files for the system listed in (4) nd (5) re shown in Appendix A. Figure 7. Input to N ode plots. Column () shows the mgnitude nd phse from the S input to the output. Column () is S to nd olumn () is S to. The unlned lod se hs full lod on N nd no lod on Copyright 2005, Christopher Smith 2
2N. Column () hs very low mgnitude ( -250 db) for the full lod nd no lod se. This uses numeril errors in the orresponding phse plot. Figure 8. Input to 2N ode plots. Column () shows the mgnitude nd phse from the S input to the 2 output. Column () is S to 2 nd olumn () is S to 2. Copyright 2005, Christopher Smith 3
Figure 9. Input to I ode plots. Column () shows the mgnitude nd phse from the S input to the I output. Column () is S to I nd olumn () is S to I. Copyright 2005, Christopher Smith 4
Figure 0. Inputs to I ode plots. Column () shows the mgnitude nd phse from the S input to the I output. Column () is S to I nd olumn () is S to I. Copyright 2005, Christopher Smith 5
Figure. Inputs to I ode plots. Column () shows the mgnitude nd phse from the S input to the I output. Column () is S to I nd olumn () is S to I. Figure 2, elow, shows how the duty yle to output voltge gin hnges s funtion of DC us voltge. In-ft it ppers to e n entirely liner gin. This n e ompensted for y inverting the DC us voltge nd pplying it s gin. Copyright 2005, Christopher Smith 6
Figure 2. Inverter system with hnging 0D us voltge. The us voltge hnges the open loop gin of the system. Now tht we hve stte spe system desriing the inverter we n hek for oservility nd ontrollility. Eqution (7) is used to test for ontrollility. Sine the rnk is 4 it mens tht ll 4 sttes re ontrollle. Eqution (8) tests for oservility. Agin, sine the rnk is 4 it mens tht ll 4 sttes re oservle. 2 3 Controllility: Rnk( [ B AB A A B] ) = 4 B (7) C Oservility: Rnk CA = 4 2 (8) CA 3 CA However, n item of immedite onern is the A mtrix. In (4) it n e seen tht the upper left orner of the A mtrix ontins R nd R 2. Any hnge in lod will use system hnge nd render our ontrollility nd oservility tests moot. A stndrd oserver will only e s good s its estimtion of the system. Our system is not only time vrint, ut lso unpreditle due to rndom lod hnges. This type of prolem lls Copyright 2005, Christopher Smith 7
for speil oserver. Sine output voltge is diretly mesurle the urrent sttes re the ones tht we need to oserve. The indutor urrent n e lulted y integrting the voltge ross the indutor. Integrting () leds us to: ( ) N + ( ) 2N + ( OD + OD) S ( OD) S ( DO) S + ( + ) R ( ) R ( ) R I = dt + + + (9) Severl terms in the ove eqution present prolem. First, the resistive drop ross the indutor is sed off of the oserved urrent itself. Seond, the onstnt term fter the integrl ould e unknown in ertin situtions. This oserver is prtiulrly hrd to implement in relity euse the resistive drop ross the indutors n hnge with temperture, the voltge drop ross the semiondutors is lso not onstnt, nd zero order hold produes n lmost onstnt error. These smll soures of error re integrted over time nd umulte to signifint low frequeny error. 2.3. Deoupling Creful study of the B mtrix shows tht there exists quite it of ross-oupling in the duty yle inputs. No duty yle ffets one indutor urrent nd no indutor urrent is ffeted y only one input. A deoupling mtrix n e pplied to the inputs so tht one input ffets only one urrent nd vie vers. The desired B mtrix is first formulted, whih will e denoted B T. The stndrd input to stte spe system is denoted s some gin mtrix B multiplied y n input vetor u. x & = Ax + Bu (20) The input u must e multiplied y trnsformtion mtrix T efore it is pssed to the plnt s modified input u. Therefore, x & = Ax + BTu nd B = T BT (2) BBT nd B re known ut B must e n invertile mtrix. Sine in our system B is not invertile the B T eqution is n under onstrined system. The eqution is shown elow in ( 22). In the B mtrix ll three indutnes hve een set equl. Also, the input to voltge setion hs een deleted sine there re no terms present. Copyright 2005, Christopher Smith 8
T = = 3 3 2 3 3 3 3 2 0 0 B 0D 0D 0D 0D 0D 0D T (22) The B nd B D mtries re ugmented with rndom vlues so tht the system is fully onstrined. T is solved for using the eqution (23) elow. = = = 0 0 0 0 0 0 3 3 2 3 3 3 3 2 B B T 0D 0D 0D 0D 0D 0D 0D T - (23) Finlly, euse u must e etween 0 nd 0.5 offset is dded to u efore it is input into the plnt. This does not ffet the plnt euse it is onstnt offset. Figure 3. Deoupling Mtrix. The deoupling mtrix lok implements the following eqution u =Du+0.5 Copyright 2005, Christopher Smith 9
Chpter 3 - Hrdwre Setup: Rpid Prototype System Control design for high power onverters is diffiult proess. High power, high voltge, nd high urrent n quikly eome dngerous if unontrolled, nd insuring system sfety nd integrity n e hllenging espeilly while exploring new topologies nd ontrol strtegies. These hllenges often impede the omintion of rpid prototyping nd high power systems. This system uses FPGA to mnge hrdwre in the loop (HI) system, onneting stndrd x86 sed proessor to high power onverter. This omintion provides high flexiility nd lrge mount of proessing power. In ddition, the use of MATAB s xpc Trget system s the ontroller s operting system nd softwre mkes the user interfe strightforwrd. xpc Trget offers its users the ility to hnge ontroller prmeters on-the-fly. It gives the designer omplete visiility of the system, inluding ny inputs, outputs, or sttes, nd provides n esy-to-use interfe from whih the designer n mke ny type of hnge simply nd esily. Using xpc Trget to lose the loop in swithing power onverter gives you n exellent deug nd development tool. 3.. Overview The trditionl MATAB xpc Trget system is divided into two prts: host nd trget omputer [9]. The trget omputer is the system ontroller. It is pled in the loop where it reeives dt from the system sensors, nd rets to them in rel time. The host is the user interfe to the trget, where the ontroller is designed, simulted, nd djusted on the fly. During the setup phse, the host sends ompiled inry of the system digrm to the trget. When instruted to egin, the trget reeives system inputs, lultes ontrol vriles, sends output signls, nd updtes the ontrol prmeters. The trget n lso generte disply of ny system vrile, displying them lolly or sending them k to the host. To tke full dvntge of the pilities tht xpc trget provides, we must refully weigh its strengths nd weknesses. While the trget n ompute omplex ontrol vriles, mtrix multiplitions, nd stte mhines, it lks the ility to rete fundmentl high-speed uilding loks like ounters, omprtors, nd shift registers required for PWM signls nd digitl signl interfes. Additionlly, onsiderle re must e tken in tuting nd quiring signls from the high power system. The dt quisition system is designed for high power isoltion, slility, nd flexiility. Copyright 2005, Christopher Smith 20
The system is roken up into three mjor piees, whih re outlined in the following setions nd lso orgnized in Figure 4 nd physilly shown in Figure 5. xpc MATAB on Trget PIB Plnt ref + - Digitl Controller C Reeiver FPGA Duty Cyle Modultor Rx Enhned Prllel Port Comm ogi Prllel SPI Chnnels Sensors Host Computer Figure 4. The HI system digrm. The ontroller uses the PIB to intert with the power system s power devies nd high power sensors. Complex ontrol lgorithms n e ltered in rel time on the ontroller while the PIB tkes re of high-speed tsks suh s PWM ptterns. Figure 5. The ssemled HI system. The system is designed for mximum flexiility. rious output filters nd sensor onfigurtions n e used. 3.2. Power Interfe Bord (PIB) As previously mentioned the PIB s primry tsks re isoltion nd high-speed signl interfe. In prtiulr lmost ll power eletroni system will need PWM genertors, isolted gte drives, IGBT fult protetion, high voltge sensors, nd high urrent sensors. All of these Copyright 2005, Christopher Smith 2
exept the tul sensors re inluded on the PIB. A lok digrm level shemti is shown in Figure 7, nd piture of the tul PCB is shown in Figure 6. Figure 6. A piture of the tul PIB. The digitl interfe eletronis re on the left while the high voltge gte drives re on the right. To/ From Controller P o w e r In te rf e B o rd Prllel port FPGA Gtedrive Power Supply ~ Isolted x6 ~ ~ Fult Isolted x6 G te D riv e G te D riv e G te D riv e G te D riv e G te D riv e Power Converter G te D riv e ~ Isoltion Sensor Sensor... Sensor oltges, Currents Figure 7. PIB system digrm. The power interfe ord is the kone of the digitl ontrol system. Copyright 2005, Christopher Smith 22
The sensors re tthed to the power onverter, where the signls re onditioned, digitized, nd isolted. The signls re serilly shifted into the FPGA through n SPI-like interfe. This type of interfe llows the signls to e digitized efore they n eome suseptile to noise. Additionlly, the digitl signls noise immunity n e further improved using differentil pirs or n optil interfe. The PIB lso inludes six isolted nd shoot-through proteted gte drives sized for onverter in the 0-20 kw rnge. At the hert of the PIB sits 50 MHz, 3,000 lok Field Progrmmle Gte Arry (FPGA). The FPGA s speed, flexiility, nd prllel proessing pilities offer mny dvntges in this system. Any imginle type of PWM ptterns n e onfigured. Also, ny digitl sensor signl n e quired nd sent to the trget PC. The PIB to ontroller ommunition uses n enhned prllel port interfe, whih is ville on most personl omputers. The FPGA ode is written in erilog [4]. erilog is similr to C ut is strutured towrds the prllel nture of FPGAs. Two loks of ode n e proessed simultneously nd their results fed into nother lok. The ode is ompiled nd simulted in Alter s design softwre, Qurtus II. Qurtus is ville free of hrge from Alter s wesite [2], ut is still quite powerful. The high-level system design is orgnized in shemti type digrm. Bloks in the shemti represent piees of hndwritten ode. Shemti entry is dvntgeous euse one n esily look t the shemti digrm nd see how individul piees of ode relte to eh other nd get etter overll understnding of the system. A system lok digrm is shown in the Figure 8, elow. Copyright 2005, Christopher Smith 23
ECP PWM Outputs SPI Input Registers FIFO Gte Drive Power Supply Pulse Genertor Figure 8. Internl FPGA shemti. The FPGA system onsists of series of onneted erilog loks. The individul setions will e overed elow. The prllel port interfe hs 8 i-diretionl dt its nd 9 ontrol its [3]. The Enhned Cpilities Port (ECP) speifition hd 4 sttes: dt forwrd, dt reverse, ddress forwrd, nd ddress reverse. The xpc trget driver only mkes use of the dt sttes. Eh stte lso hs su sttes tht tke re of the hndshking etween the FPGA nd PC. An tul pture of the dt yle is shown in Figure 20 nd the detiled view of the ECP lok is shown in Figure 9. Copyright 2005, Christopher Smith 24
Figure 9. The ECP setion. The ECP lok nd its ssoited signl onnetions n exhnge dt t 2 MB/s.. Figure 20. A typil dt trnsfer yle. Dt (D0) is pled on the dt us, the H_ACK line is rised to signl dt trnsfer, H_CK is lowered to show dt is redy, the peripherl knowledges the vlid dt y rising P_ACK, H_CK is rised nd the dt is lthed in, nd finlly the peripherl lowers P_ACK to signl the end of the trnsfer. The dt us s diretion is ontrolled y the nrevreq signl. This signl is sserted low y the host to tell the peripherl it is llowed to send dt. When the host rings the line low the FPGA sends ny ville dt it hs queued up. From system perspetive this is when the previous yle s smples re stored nd sent into the PCs FIFO uffer. When the host s smpling interrupt trips nd the window for reeiving dt is over then it sserts the nrevreq line high nd the FPGA knows tht it is not llowed to ple dt, ut rther should e redy to reeive dt. The PWM signls re sent from the PC to the FPGA during the next prt of the ommunition sequene. Eh duty yle is trnsmitted s single yte followed y one Copyright 2005, Christopher Smith 25
heksum yte for the previous three ytes. The PWM prse lok reeives these hunks of dt from the ECP lok, sves eh of the three to register, tests the heksum, nd psses ny vlid dt to the PWM loks. Additionl, timeout logi mkes sure tht the duty yle is updting ontinully. If the lok reeives d heksum then the previous yle s duty yles re used. If no new duty yles re reeived within 0.4 ms then the duty yles re set to zero. This prevents ny loss of ommunition from using prolem in the power stge. These loks re shown elow in Figure 2. Figure 2. The PWM setion. The PWM signls reeived nd re generted with dedtime using these series of loks. The 8-it duty yle vlues re sent to their respetive PWM modultor loks. For lssi six-swith ridge three PWM loks re used. All three loks use the sme ode, ut onstitute three seprte modultors within the FPGA. The PWM lok swithing frequeny n e hnged through ompile time prmeters. A enter ligned PWM ws eventully used euse it eliminted simultneous swithing edges nd redued EMI on other iruitry. Other modultion shemes suh s interleved PWM ould e implemented nd ould esily reple the enter ligned PWM lok used here. Next the PWM signl ws sent to dedtime genertor lok. The dedtime used ws ompile time prmeter nd ould esily e hnged if neessry. The lok outputs two Copyright 2005, Christopher Smith 26
omplimentry gte signls with dedtime. The dedtime lok lso ontins n enle input for ny se where the gte signls needed to e shutdown. The dt quisition hlf of the FPGA provides up to seven seril peripherl interfe (SPI) hnnels. The power stge sensors utilize digitlly isolted seril nlog to digitl onverters (A/D). On rising nrevreq edge the smp_pulses lok genertes query signl for the sensors. The SPIx7 lok genertes one set of lok, nd hip selet lines for ll seven sensors. Additionlly it simultneously shifts seven lines of dt into the FPGA from the sensors. Figure 22. The SPI setion. The SPI portion of the FPGA reds in the sensors nd psses the info on to the FIFO. The ig_reg lok is lrge prllel lth the grs the output from the SPI lok nd holds it until the next smple yle is ville. The seven vlues re then muxed into FIFO lok so tht they n e pssed to the prllel port lok one t time when it is redy to send dt to the PC. Figure 23 shows the detil view of these loks. Copyright 2005, Christopher Smith 27
Figure 23. The FIFO setion. The mux psses its dt one t time to the FIFO. The FIFO wits for the dt exhnge yle to pss its dt to the prllel port lok. Severl other loks lso exist on the digrm shown in Figure 8. A freq_div lok is used to divide the 50 MHz system lok down to something slower. One use for this is the gte drive power supply. A forwrd onverter with six isolted seondries is lso on the PIB ord, nd is shown in Figure 24. A 500 khz, 44% duty yle gte drive signl is sent form the freq_div lok. This gte drive power supply n lso e turned off or on from within the FPGA. Here it is mpped to simple externl dip-swith. Swithes nd EDs re inluded on the ord for Copyright 2005, Christopher Smith 28
dignosti purposes suh s those mentioned ove. stly, every input to the FPGA must pss through synhronizer to prevent ny metstilty issues []. Metstiltiy ours when n input hnges stte without dequte setup time. A synhronizer onsists of two flip-flops in series nd insures tht the output is orretly synhronized with the system lok. Figure 24. The isolted gte drive power supply. The forwrd onverter (irled ove) provides power to the isolted gte drives. 3.3. Controller The ontroller onsists of n x86 sed PC running its own MATAB propriety xpc Trget operting system. The ontrol ode is generted from Simulink, MATAB s grphil system simultion environment. Sine Simulink n generte stndrd C ode the trget ould lso e miroproessor or miro ontroller. In prototyping system the x86 trget ffords mny dvntges. The proessing power of stte-of-the-rt PC is virtully unlimited ompred to simple miroproessor. The dditionl proessing power gives the user the ility to experiment with more omplex ontrollers nd refine the design efore pssing the ode long to hip more likely to pper in n emedded system. Also, the PC trget llows the user to tth trget PC sopes to the ontroller for displying system vriles on the trget s monitor in rel-time. Prmeters n e djusted on the fly through Simulink or we rowser interfe. Copyright 2005, Christopher Smith 29
Simulink hs the pility to rete mny types of ontrollers. A simple ontroller, like PID, is esy. Fixed-point sling n e dded to further emulte rel system. Modern ontrol theory nd mtrix opertions n e used to rete highly optimized stte spe systems [24]. Also, stte digrms n e used to rete dptive ontrollers. The Simulink interfe llows the use of model sed design pproh. Before the system is tested t the hrdwre level theoretil model of the plnt n e tested with the ontroller. ter, the lok representing the theoretil model n e removed nd the tul system inserted in its ple. In the rel world the input to the plnt is the PWM gte signls sent to the onverter nd the output would e the urrent nd voltge sensors. One the lok is inserted the dt exhnge for the input prmeters nd output signls is trnsprent to the user. One the plnt lok is opened up there is sustntil mount of ommunition present. The xpc trget to FPGA ommunition uses stndrd PC prllel port. Speifilly, it uses the Enhned Prllel Port (ECP) stndrd. The ECP stndrd is the third mjor revision to the ommon Centronis DB25 stndrd found on erly PCs, nd is out 0 times fster thn the originl prllel port speifition. All hndshking is done in hrdwre, whih requires fewer CPU yles to trnsfer yte. This redution in I/O overhed improves the yle time tht given PC n run. Also, the ECP hs first in first out uffer (FIFO) for pooling up dt. In our se this is used for ringing in ll of the smples from the previous yle [3]. The driver for xpc trget is written in C ode nd ompiled into stndrd Simulink S- funtion [8]. Control of the prllel port is done through si I/O port lirry provided y xpc trget. The rl32eoutpb funtion is used for writing 32-it word to speifi I/O port nd the rl32einpb funtion is used for reding 32-its from speifi port. The prllel port se ddress resides t 0x378 in stndrd PC. Dt is pssed to nd from this ddress s well s 5 other registers whih ontrol dditionl port prmeters suh s diretion. The si struture of the driver is s follows nd n e seen in Figure 25:. Initilize port 2. Cler FIFO 3. Red sensor dt from FIFO 4. Set port to output mode 5. Output A, B, nd C duty yles 6. Output heksum for duty yles 7. Set port to input mode 8. Goto 3 ove Copyright 2005, Christopher Smith 30
3 4 7 5 6 Figure 25. The dt exhnge yle. The dt from the previous yle is pulled from the FIFO t the eginning of eh smpling yle. 3.4. Power System nd Sensors The power system onsists of stndrd six-swith IGBT ridge on PCB onfigured to llow mximum flexiility for different topologies. Footprints for extr pitors nd indutors hve een dded. Nerly ll useful urrents nd voltges hve een instrumented, see Figure 26. The power ord hs een designed s proof of onept nd is ple of running t out 5 kw. Sensors hve een designed for high ndwidth nd re good up to round 50 khz. Communition hnnels llow for simultneous smpling of ll 7 sensors. I A I B AB DC I C BC C-GND Figure 26. Power Bord Topology nd Sensors. The power ord onsists of six-swith topology nd seven sensors. The power ord, see Figure 27 elow, n e onfigured for vriety of topologies, suh s, interleved uk or oost, power ftor orretion, multi-phse inverter, motor drive, nd resonnt topologies. rious PWM ptterns for these onverters re lso esily implemented on the PIB. Copyright 2005, Christopher Smith 3
Figure 27. The power ord. The power ord ws designed for mximum flexiility llowing vriety of different topologies to e implemented y esily removing nd dding iruit omponents. The sensor shemti is shown in Figure 28 elow. The high voltge is first divided down to usle vlue with resistive divider. This is then rought into differentil mplifier (OPA2277UA) nd then over to the seril A-to-D (ADCS7476). The A/D is 0-it A/D ple of million smples per seond. The ommunition from the A/D to the FPGA is eletrilly isolted through the high speed digitl isoltor (HCP-0930). Isolted power is supplied through smll ( Wtt) DC/DC. The urrent signls re quired in similr fshion exept the hll effet sensors re lredy eletrilly isolted so there is no need for the extr high speed digitl isoltor. The system tully used in testing hs severl limittions. First the urrent sensors were not used in the ontroller euse it ws deided tht low-ost ontroller proly wouldn t use them. They were used for visul nlysis while the system ws running ut not in n tul ontroller. Seond, the us voltge used ws 300 volts. imited vilility of progrmmle DC supplies ment the full us voltge (400) wsn t ville. A step-up trnsformer nd diode retifier were used. This setk ws tully helpful euse the output voltge ould e sled down nd it dded DC us ripple tht mde it esy to nlyze udiosuseptiility. Copyright 2005, Christopher Smith 32
Figure 28. Isolted high voltge sensors. The voltge sensors use seril A/Ds nd high speed digitl isoltors to mintin len noise free signl. 3.5. User Interfe One of the most useful things out the rpid prototyping system is the user interfe. Unique systems n e quikly implemented nd vriety of system dt n e rpidly rought together for exmintion. A typil design yle would progress s follows:. Crete or find mthemtil model of the system 2. Setup Simulink model sed upon the mthemtil model 3. Simulte the system nd verify stility nd desired opertion 4. Configure the physil power system to mth the onverter to e tested 5. Compile nd downlod ontroller ode to trget 6. Run system nd nlyze dt 7. Reonfigure nd renlyze Steps nd 2 were shown in Chpter 2. Steps 3 through 7 re shown in Chpter 4. The xpc trget system is responsile for most of the funtionlity in the lst few steps. Its doumenttion thoroughly outlines the tools used in steps 5 through 7 [9]. After good simultion is put together nd tested the user is redy to move on to the tul hrdwre. Compiling the ode is s esy s seleting menu item in Simulink. The ompiled ode is utomtilly downloded to the trget. After downlod the system is redy to run. Copyright 2005, Christopher Smith 33
While the system is running the trget displys dt on its tthed monitor. xpc trget sopes re dded to the Simulink digrm, see Figure 33 in ornge. Figure 29 shows n exmple of trget sope pture nd mthing rel sope pture. The overshooting output voltge in the ottom sope pne on the left (lue) is lso shown on the right. You n see tht oth re nerly identil. With this setup n tul sope is rely neessry t ll. In ft the trget sope n even show non-rel dt suh s D or Q urrents in rotting referene frme ontroller. In ddition, dt n e ptured for post proessing. () xpc Trget Sope () Atul Sope Figure 29. A omprison of the xpc trget sope nd rel sope pture. () This plot shows wht the user would see on the trget PC s sreen. () This plot is nerly identil nd shows wht the user would see on n osillosope. One the user understnds how the system is ehving they will most likely need to djust prmeters. Items suh s gins, offsets, mtrix oeffiients, nd run times n e djusted on the fly. In the event of mjor hnge the system usully needs to e reompiled. 3.6. Summry As previously mentioned the HI ontrol system ws designed for mximum flexiility. The setup time required to develop or verify new ontrol shemes n e minimized with this system euse mny of the usul prolems ssoited with digitl ontrol re eliminted. Fixed-point issues, omplited oding, proessor omputing power, non-liner funtions, nd system Copyright 2005, Christopher Smith 34
visiility re ll simplified. This leves time for developing etter ontrollers whih n minimize power onverter size nd ost s well s help in the overll design nd testing phse. The system shown ould e rguly fster thn n optimized DSP sed rrngement. However, the rel dvntge is in the totl time neessry to design nd verify the ontroller. Design itertion time is redued whih leves time to improve the lgorithm or explore different ontroller options. One the est ontrol sheme is determined ny numer of inexpensive miroproessor sed solutions ould e implemented. Copyright 2005, Christopher Smith 35
Chpter 4 - Ciruit Simultion nd Hrdwre Experimenttion 4.. Plnt Model Ciruit simultion ws performed in Mtl s Simulink softwre pkge. While Simulink is not typilly used for iruit simultion it performs very well for ontroller design. The stte spe system from Chpter 2, see (4)(5)(6), ws modeled s non-liner time invrint system. Prmeters in the A mtrix like resistne (R nd R 2 ) were llowed to hnge with respet to time. This would hppen during step hnge in lod. Also, input voltge ( 0D ) ws llowed to hnge with time. These dditionl detils provided n urte model of the plnt nd llowed the ontroller to e simulted nd tested for stility over vrying operting points. Copyright 2005, Christopher Smith 36
Figure 30. The Simulink Plnt Model. The Simulink digrm for the plnt model is shown ove. Gins from the A nd B mtrix re shown in the middle nd re denoted y nmes like A34 for A mtrix row 3, olumn 4, lso from (4) in Chpter 2. The duty yle inputs into the plnt were modeled with effets tht would typilly e seen in digitl ontroller, see Figure 3. The quntiztion dely is present euse the 8-it digitl PWM modultor uses time step size of F s *(/2 8 ). The quntiztion represents the ft tht the digitl PWM modultor must hnge its pulse width in disrete time steps. The ded zone lok represents the lk of response with very smll duty yles (ner zero). This lk of response shows up euse ded time is used to prevent ross ondution in omplementry swith pirs. With finite turn-on nd turn-off time the IGBTs minimum pulse width is limited. This phenomenon is lso known s minimum pulse elimintion. The ded zone is tive from five perent to zero. The zero-order hold lok represents the ft tht the duty yle n only e Copyright 2005, Christopher Smith 37
hnged t disrete time intervls or one per swithing yle. stly the sturtion lok represents the ft tht the onverter n only implement zero to one-hundred perent duty yle. Figure 3. Plnt input non-linerrities. Plnt inputs were modeled with effets typilly seen in digitl system. The plnt outputs in digitl ontroller lso hve some disrete smpling effets tht need to e modeled. Quntiztion nd the zero-order hold re present in ny smpled digitl system. In our system we use 8-it 500 volt sensors. The ssoited quntiztion is modeled with 500*(/2 8 ) step size. The nlog to digitl onverters (A/Ds) re smpled one per swithing yle. The zero-order hold uses the swithing time s its dely time. Figure 32. Plnt model. A typil open-loop simultion is shown ove. 0D, R, nd R 2 n e stepped or otherwise pertured to vry the operting point. One the open loop model is uilt nd tested the designer n egin to work on the ontroller. The reminder of this hpter will fous on vrious ontrollers nd their dvntges nd disdvntges. Copyright 2005, Christopher Smith 38
4.2. Controller The first ontroller type exmined is simple losed-loop voltge ontroller with sinusoidl referene. The si system is shown elow in Figure 33. The system ontins differentil ontroller nd ommon ontroller. The differentil ontroller ontrols the differentil voltge or the 240 AC. The ommon ontroller mkes the ddition of N nd 2N lwys equl to zero. This is the sme s sying tht they re equl nd opposite voltges. For ontroller design the liner system plnt model shown in Eqution 4 is used. The deoupling mtrix from ove is multiplied y the B mtrix to form new B mtrix. The operting point used in the design is full DC us voltge nd firly light lod. This point is the hrdest to ontrol euse the full DC us voltge ts s high gin nd the light lod (00 ohms) provides very resonnt seond order system. These properties n e seen in Figure 8 nd Figure 2. The zpk ommnd is used to find the trnsfer funtion from the differentil input to differentil voltge output. The output is shown in (24) elow. (s 2 2 43e9 (s + 295.7s +.794e7) 2 + 295.7s +.794e7) (s + 295.7s + 5.378e7) (24) Figure 33. Complete System. The losed-loop voltge ontroller with sinusoidl referene. Copyright 2005, Christopher Smith 39
For omplete liner system one must lso tke into ount the smpling dely. A firstorder Pde pproximtion is used to represent the smpling dely. MATAB s pde ommnd esily lultes the neessry liner system to represent the dely. The rlous ommnd or sisotool ommnd is used to show the poles nd zeros of the system long with the smpling dely, see Figure 34. The poles shown in Figure 34 will move wy from the imginry xis under more lod. Moving the poles wy from the imginry xis mens the ontroller n hve more gin nd still e stle. Appendix A shows the sript file used to exeute the ommnds ove. Controller design strted with neling the two omplex poles with zeros. The neling zeroes were dded slightly to the left of the existing poles sine lod hnge would ring the poles in tht diretion nywy. Then two poles were dded t the origin for stedy stte trking of sine wve referene. Next two omplex zeros were dded to pull the losed loop poles emnting from the origin towrd the left hlf plne. Finlly two more rel poles were dded so tht the system hd high frequeny roll off. The finl ompenstor is shown in (25) elow. The gin ws rised s high s possile with few deiels of gin mrgin. This gve rossover frequeny of 350 Hz. 359e - 6 (s 2 2 + 990s +.083e6)(s + 499s + 5.34e7) 2 s (s + 2597) (s + 490) (25) Copyright 2005, Christopher Smith 40
Figure 34. d diff to diff root lous. The losed loop root lous of d diff to diff with smpling dely in the feedk loop is shown ove. The ompenstor is set to unity gin. The right-hnd plot shows more detiled piture of the poles ner the imginry xis. In order to simplify trouleshooting the system ws first run with only differentil ompenstor. Any intertions tht might e present etween the ontrollers were eliminted nd the differentil voltge regultion ws verified t severl operting points. Figure 35 nd Figure 36 show the simultion nd tul response for the differentil voltge nd the ommon voltge during lod hnge. Simultion nd experimentl dt mth very well. The differentil voltge regultes firly well. The output voltge is firly stedy, ut does show some udiosuseptiility due to the retifier supplied DC us. The input voltge n e seen in the top left pnel of Figure 35 nd Figure 36. The us hs 30-volt ripple unloded nd 50-volt ripple under lod. The ripple frequeny is twie the input retifier frequeny, ut ontins mny higher order hrmonis during the rising edge. Sine the ontroller does not hve ny gin ove 350 Hz it n t entirely eliminte the effet of the input ripple. stly, the unregulted ommon voltge oviously needs ontroller. Figure 38 shows the ommon voltge on the output, nd out 20 volts of error is present. Copyright 2005, Christopher Smith 4
Figure 35. diff ontroller simultion. The lod step (t 40 ms) uses the us to drop more nd the duty yles inrese to mintin the sme differentil voltge. Copyright 2005, Christopher Smith 42
Figure 36. diff ontroller experimenttion. The xpc Trget pture ove shows the system during lod step from no lod to moderte lod ross oth N nd 2N. The upper left is the DC us, upper right the duty yles, lower left the output voltges. Copyright 2005, Christopher Smith 43
Figure 37. Unevenly loded system simultion. During uneven lod the ommon mode voltge vries. In the lower right plot one n see the line does not sty t zero s it should. Copyright 2005, Christopher Smith 44
Figure 38. Unevenly loded experimenttion run. The sope pture shows the system running with n uneven lod. Upper left is the DC us, upper right the duty yles, lower left the output voltges ( N nd 2N ), nd lower right the sme output voltges gin ( diff nd om ). The trnsfer funtion from ommon input to ommon output is shown elow in (23) nd the losed loop root lous is shown in Figure 39. It should e noted tht the negtive sign in the trnsfer funtion gives 80-degree phse shift t low frequeny. (s 2 2-2.505e9 (s + 295.7s + 5.378e7) 2 + 295.7s +.794e7) (s + 295.7s + 5.378e7) (26) Copyright 2005, Christopher Smith 45
Figure 39. d omm to diff root lous. The losed loop root lous of d omm to omm with smpling dely in the feedk loop is shown ove. The right-hnd plot shows more detiled piture of the poles ner the imginry xis. The differentil mode ontroller strted with setting the feedk to positive feedk sine the plnt nturlly hd 80-degree phse shift. Next two poles t zero were dded for trking with sine wve disturne. Two zeros were dded to nel the poles shown in Figure 39. One more pole ws dded to ring the losed-loop pole trjetories emnting from the origin to the left-hnd side. Finlly zero ws dded to mke the system prtil t high frequenies. The root lous nd open loop ode re shown in Figure 40, nd the step response nd losed-loop ode re shown in Figure 42. The losed-loop ode shows tht the system hs firly flt response up to 37 Hz where it rosses over. One prolem is the slight resonne t rossover. This effet is seen in the step response simultion, see Figure 42, whih hs high frequeny osilltion. The phse shift is lso importnt euse the system needs to trk well t the disturne frequeny of 60 Hz. The finl zpk form of the ommon ompenstor is shown ove in (24). 395e - 3 (s 2 + 72.6)(s + 647.3s +.82e7) 2 s (s + 3884) (27) Copyright 2005, Christopher Smith 46
Figure 40. d diff ode plot nd root lous. The root lous nd open loop ode for the differentil mode ontroller re shown ove. The shded re on shows the region tht the losed-loop poles must sty inside to minimize the overshoot during step. The system hs 37 Hz of ndwidth. Copyright 2005, Christopher Smith 47
Figure 4. d diff detiled root lous. A more detiled view of the enter shows two poles t the origin nd zero t 75. Copyright 2005, Christopher Smith 48
Figure 42. Closed loop ode nd step response. The overshoot is less thn 20 perent nd the phse shift t 60 Hz is only 7 degrees. The finl losed loop system ehved firly well under vrying types of lod steps s well s unlned lods. Figure 44, elow, shows the system running with n unlned lod. The top right pnel shows the duty yles nd it is evident tht the enter leg duty yle is eing djusted to ompenste for the disturne in om. Copyright 2005, Christopher Smith 49
Figure 43. Simultion of oth diff nd om. With ontrollers working the ommon mode voltge is gretly redued nd the differentil voltge is tightly regulted. Figure 44. Experimenttion using oth diff nd om ontrollers. The sope pture ove shows the system with oth the diff nd the om ompenstor in the loop. The lod is unlned however the ommon output voltge stys firly lose to zero. Upper left is the DC us, upper right the duty yles, lower left the output voltges ( N nd 2N ), nd lower right the sme output voltges gin ( diff nd om ). Copyright 2005, Christopher Smith 50
One re where the system did not perform well ws with non-liner lod. A retifier with DC lod ws tthed ross 2. This type of lod presents severl prolems. First, it pulls high urrents t the pek of the sine wve nd no urrent t ll during the reminder of the wveform. This ehvior uses high frequeny omponents in the lod urrent tht n exite resonne in the ontroller or just distort the output voltge wveform. Seondly, with pitor on the retifier output even higher surge urrents exist on strt-up. Figure 46 shows the system during this ondition. Hlf wy through the sope pture the non-liner lod is dded. The DC us egins to dip s does the output voltge. In response the duty yles re inresed nd eventully re ompletely sturted for prts of severl line yles. When the pitor is fully hrged the ontroller finlly strts to reover ut still nnot respond quikly enough to the surge urrent to prevent the output voltge from dipping t the pek of the sine wve. This se ws not too d ut severl others did not reover from duty yle sturtion nd the system went unstle. A ontroller with higher ndwidth would ertinly e le to del with this type of lod etter. Unfortuntely, euse of the 0kHz smpling limittion the gin n only e inresed so fr efore the system is not stle. Figure 45. Unhrged retifier simultion. A retifier onsisting of four diodes nd pitor on the output is pled ross the diff output. The inrush urrent uses lrge surge in power. Copyright 2005, Christopher Smith 5
Figure 46. Unhrged retifier experimenttion. This sope pture shows the ddition of non-liner retifier lod ross 2. Upper left is the DC us, upper right the duty yles, lower left the output voltges ( diff nd om ). The system is stle during this lrge trnsient event ut does hve some high frequeny hrmonis present fter the lod step. The udiosuseptiility prolem is still unsolved. Another optimiztion tht n e used is feed forwrd term. With the previous set of ontrollers the only feedk term is the output voltge. Any disturne due to the DC us voltge ripple n only e hndled fter it is lredy evident in the output voltge. A etter solution would e to wth the DC us nd tively djust the duty yles for ny hnge in us voltge. A ommon solution is to linerly inrese the duty yle s the us dereses. The inverse of the DC us voltge is found nd then gin term for nominl us voltge is used to normlize the duty yles round the nominl us vlue. The feed forwrd ontroller should work reltively well exept for the ft tht it the sme gin ross ll mesurle frequenies. Any noise tht mkes its wy into the system will immeditely ffet the duty yles. A low pss filter ws dded with -3dB point of.8 khz. This llowed the higher frequenies present in the us voltge ripple to pss ut loked spurious one smpling yle lip in the output voltge. Figure 47 shows the solution implemented in Simulink, nd Figure 49 shows the sope pture during opertion. The top right pnel in Figure 49 shows the duty yles, whih re firly distorted to del with the us Copyright 2005, Christopher Smith 52