bu Dhabi Men s College, Electronics Department Logic Families There are several different families of logic gates. Each family has its capabilities and limitations, its advantages and disadvantages. The following list describes the main logic families and their characteristics. Diode Logic (DL) Diode logic gates use diodes to perform ND and OR logic functions. Diodes have the property of easily passing an electrical current in one direction, but not the other. Thus, diodes can act as a logical switch. Diode logic gates are very simple and inexpensive, and can be used effectively in specific situations. However, they cannot be used extensively, as they tend to degrade digital signals rapidly. In addition, they cannot perform a NOT function, so their usefulness is quite limited. Diode OR Circuit D1 D2 The above figure shows two diodes D1 & D2 with a resistor load. The table shows the voltage truth table for the circuit. With both inputs at, the output is at. With either diode input at, the respective diode will be forward biased and current will flow through the diode and the load resistor. For silicon junction diodes, the output voltage will be approximately 0.7V less than the input voltage, due to the voltage drop across the forward biased diode. With both inputs at, the output will still be 0.7V less than the supply value (that is, 4.3V). Note: If the input voltages for the two inputs are different, then the output voltages will depend on the inputs. Table below shows the voltage truth table for inputs of +3V &. +3V +2.3V +4.3V +3V +4.3V Converting the voltage levels of the above truth table to logic levels 0 & 1 and using positive logic gives the truth table shown below 0 0 0 0 1 1 1 0 1 1 1 1 +4.3V +4.3V +4.3V bbas li 1 of 12
bu Dhabi Men s College, Electronics Department From the above table it can be seen that the output is at logic 1 if input OR OR both inputs are at logic 1. The circuit therefore performs the OR function. Circuits having inputs and an output, the output depending on the logic states of the inputs, are referred to as gates. circuit with the OR characteristic is referred to as an OR gate. Such a gate with two inputs would be referred to as a 2-input OR gate, one with three inputs a 3- input OR gate, etc. Diode ND Circuit D1 D2 R1 0.7V 0.7V 0.7V The above figure shows two diodes D1 & D2 and resistor R1 forming an ND circuit. The table shows the voltage truth table for the circuit. With both inputs at, both the diodes will be forward biased and the output will be 0.7V, this being the voltage drop across a forward biased silicon junction diode. With either diode input at, the respective diode will be forward biased and the output voltage will again be approximately 0.7V. With both inputs at, both diodes will be reverse biased and the output voltage will be the supply value (that is, ) provided there is no load resistor connected to the output circuit. With a load resistor R L connected to the output circuit the output voltage will be reduced to the value 5 x R L /(R1 + R L ). This is illustrated in the figure below D1 D2 R1 RL V out = 5 x RL R1 + R L Converting the voltage levels of the previous table to logic levels 0 & 1 and using positive logic gives the truth table shown below 0 0 0 0 1 0 1 0 0 1 1 1 bbas li 2 of 12
bu Dhabi Men s College, Electronics Department From the above table it can be seen that the output is at logic 1 only if inputs ND are at logic 1. The circuit therefore performs the ND function. Such a circuit with two inputs would be referred to as a 2-input ND gate, one with three inputs a 3-input ND gate, etc. Resistor-Transistor Logic (RTL) Resistor-transistor logic gates use Transistors to combine multiple input signals, which also amplify and invert the resulting combined signal. Often an additional transistor is included to re-invert the output signal. This combination provides clean output signals and either inversion or non-inversion as needed. RTL gates are almost as simple as DL gates, and remain inexpensive. They also are handy because both normal and inverted signals are often available. However, they do draw a significant amount of current from the power supply for each gate. nother limitation is that RTL gates cannot switch at the high speeds used by today's computers, although they are still useful in slower applications. lthough they are not designed for linear operation, RTL integrated circuits are sometimes used as inexpensive small-signal amplifiers, or as interface devices between linear and digital circuits. Diode-Transistor Logic (DTL) y letting diodes perform the logical ND or OR function and then amplifying the result with a transistor, we can avoid some of the limitations of RTL. DTL takes diode logic gates and adds a transistor to the output, in order to provide logic inversion and to restore the signal to full logic levels. Transistor pplication as a Switch Input R1 R2 Input Input 0 1 1 0 Positive Logic The above figure shows an NPN transistor circuit with base feed resistor R1 and collector load resistor R2. The table shows the voltage and positive logic truth tables for the circuit. With the input at, there will be no base current and hence the transistor will be turned OFF. There will be no collector current, so the output voltage from the collector will be the supply value (), provided there is no load resistance connected to the output. With the input at, there will be a current flow in the base-emitter circuit and the transistor will be turned ON. The value of R1 is arranged to allow sufficient collector current to flow for the collector voltage to fall to approximately zero. Under this condition the transistor is said to be saturated. Example: With a collector load resistor of 1k and a supply voltage of, the collector current required to saturate the transistor will be: Ic = 5V 1k = 5m bbas li 3 of 12
bu Dhabi Men s College, Electronics Department With a transistor current gain of 20, the minimum base current required is: Ib = 5m 20 = 0.25m There will be 0.7V drop across the transistor base - emitter junction and 4.3V across R1 (5V - 0.7V = 4.3V). The maximum value of R1 to allow 0.25m current to flow is: 4.3V R1 = 0.25m = 17.2k Normally a lower value for R1 would be used to ensure that the transistor saturates. From the truth tables it can be seen that the output logic level is the inverse of the input logic level. The circuit acts as an inverter and is referred to as a NOT gate. Diode-Transistor NOR Gate R1 R2 0 0 1 0 1 0 1 0 0 1 1 0 Positive Logic The above figure shows a 2-input diode-transistor circuit and the table shows the voltage and logic truth tables for the circuit. With both inputs at, the transistor will be turned OFF and the output voltage will be at. With either or both inputs at, the transistor will be saturated and the output will be at. The output states are the inverse of those for an OR gate. That is, it is a NOT OR gate and is referred to as a NOR gate. Diode-Transistor NND Gate R3 R1 R2 0 0 1 0 1 1 1 0 1 1 1 0 Positive Logic The above figure shows a 2-input diode-transistor circuit and the table shows the voltage and logic truth tables for the circuit. With either or both inputs at, the junction of R1 & R3 will be held at 0.7V, due to the voltage drop across the forward biased diode. The transistor will be turned OFF and hence the output voltage will be at. With both inputs at, the transistor base - emitter circuit will be fed via R3 & R1, the transistor will be saturated and the output will be at. bbas li 4 of 12
bu Dhabi Men s College, Electronics Department The output states are the inverse of those for an ND gate. That is, it is a NOT ND gate and is referred to as a NND gate. In practice, to ensure that the transistor base voltage is less than 0.7V with either input at, the resistor R1 is normally replaced with a diode as shown below R3 D R2 R3 R4 R2 Circuit using voltage shifting diode R5 Circuit using Schottky diodes Effect of Logic Convention on Gate Characteristics 0 0 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 Positive Logic ND Gate Negative Logic OR Gate The above tables show the voltage truth table characteristics of a gate and also the logic truth tables for positive and negative logic conventions. For positive logic the gate has an output of logic 1 only with both inputs at logic 1 and therefore represents an ND gate. For negative logic convention, the gate has an output of logic 1 when either or both inputs are at logic 1 and therefore represents an OR gate. 0 0 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 Positive Logic OR Gate Negative Logic ND Gate The above tables show the voltage truth table for a gate and its corresponding positive and negative logic truth tables. The gate represents an OR gate for positive logic and an ND gate for negative logic. bbas li 5 of 12
Transistor-Transistor Logic (TTL) bu Dhabi Men s College, Electronics Department The physical construction of integrated circuits made it more effective to replace all the input diodes in a DTL gate with a transistor, built with multiple emitters. The result is transistortransistor logic, which became the standard logic circuit in most applications for a number of years. s the state of the art improved, TTL integrated circuits were adapted slightly to handle a wider range of requirements, but their basic functions remained the same. These devices comprise the 7400 family of digital ICs. These are basically gate circuits consisting of several transistors, resistors and diodes that have been formed on a small piece of silicon and enclosed in a plastic package. Normally, more than one gate will be formed on the same piece of silicon and enclosed in the same package with the supply and the input and output connections for each gate brought out to external connecting pins. The complete unit is referred to as an integrated circuit (IC). These circuits are much smaller, require the minimum of connections, are faster and more reliable than equivalent circuits constructed from separate components. The usual package form is rectangular with the connecting pins aligned along the two longer sides and is referred to as a DUL-IN-LINE (DIL) package. For gate circuits, packages with either 14 or 16 connecting pins are used and they are therefore referred to as 14-pin DIL or 16-pin DIL packages. The following figure illustrates the DIL packaging and the pin numbering system, pin 1 being indicated by a circular indent at the end containing a notch. 14 13 12 11 10 9 8 16 15 14 13 12 11 10 9 Notch Pin 1 I dentification Pin Numbers 1 2 3 4 5 6 7 14-pin DIL IC 1 2 3 4 5 6 7 8 16-pin DIL IC TTL Logic Gates and Levels There are a series of TTL integrated circuits (IC's), the identification numbers starting with the numerals 74 and they are therefore referred to as the 74 series. e.g. 7400 Quad 2-input NND gate (Four 2-input NND gates in the IC) 7402 Quad 2-input NOR gate (Four 2-input NOR gates in the IC) 7408 Quad 2-input ND gate (Four 2-input ND gates in the IC) 7432 Quad 2-input OR gate (Four 2-input OR gates in the IC) 7404 Hex Inverter (Six Inverter or NOT gates in the IC) The following shows the gate pin-out connections for these IC's. bbas li 6 of 12
bu Dhabi Men s College, Electronics Department Vc c 14 13 12 11 10 9 8 Vc c 14 13 12 11 10 9 8 7400 7402 1 2 3 4 5 6 7 Gnd Quad 2-input NND gate Vc c 14 13 12 11 10 9 8 1 2 3 4 5 6 7 Gnd Quad 2-input NOR gate Vc c 14 13 12 11 10 9 8 7408 7432 1 2 3 4 5 6 7 Gnd Quad 2-input ND gate Vc c 1 2 3 4 5 6 7 Gnd Quad 2-input OR gate 7404 1 2 3 4 5 6 7 Gnd Hex Inverter This series of logic gates use positive logic, a supply voltage of and specified values for the voltages corresponding to the logic levels 0 & 1 and for the other characteristics of logic gates. There are several variations on the standard 74 series of TTL devices: STTL LSTTL LSTTL FST Schottky TTL Low power Schottky TTL dvanced Low Power Schottky TTL High speed Low Power TTL These have slight differences in respect of some of the characteristics compared with the standard TTL and will be considered in a further course on the topic. The voltage values specified for the two logic levels are common for all TTL series devices and are as follows: : Logic 0: < 0.8V Logic 1: > 2. s: Logic 0: <0.4V Logic 1: >2.4V These values represent the voltages that are recognized accurately as being at the respective level 0 or 1 at the input to or the output from a device. Intermediate voltages 0.8V - 2. at the input or 0.4V - 2.4V at the output may be inaccurately identified. The input voltage value at which a change in the output state is triggered is referred to as the THRESHOLD LEVEL. For the TTL family, this value is around 1.4V. bbas li 7 of 12
bu Dhabi Men s College, Electronics Department 4V 3V 2.4V 2V rea Outside Specification Typical Characteristic 1V 0.8V 1V 2V 3V 4V 5V Input 0.4V The above figure shows the typical TTL NND gate input/output transfer characteristic and indicates the voltage areas outside the stated specification for these devices. With the input voltage low, the output is high and exceeds 2.4V. t the threshold voltage, between 0.8V & 2V, the output state changes to its low level, this being less than 0.4V. For input falling voltage change from high value to zero, the characteristic is basically the same as for rising voltages. Emitter-Coupled Logic (ECL) lso known as Current Mode Logic (CML), ECL gates are specifically designed to operate at extremely high speeds, by avoiding the "lag" inherent when transistors are allowed to become saturated. ecause of this, however, these gates demand substantial amounts of electrical current to operate correctly. CMOS (Complementary Metal Oxide Semiconductor) Logic One factor is common to all of the logic families we have listed above: they use significant amounts of electrical power. Many applications, especially portable, battery-powered ones, require that the use of power be absolutely minimized. To accomplish this, the CMOS (Complementary Metal-Oxide-Semiconductor) logic family was developed. This family uses enhancement-mode MOSFETs as its transistors, and is so designed that it requires almost no current to operate. CMOS gates are, however, severely limited in their speed of operation. Nevertheless, they are highly useful and effective in a wide range of battery-powered applications. Most logic families share a common characteristic: their inputs require a certain amount of current in order to operate correctly. CMOS gates work a bit differently, but still represent a capacitance that must be charged or discharged when the input changes state. The current required to drive any input must come from the output supplying the logic signal. Therefore, we need to know how much current an input requires, and how much current an output can reliably supply, in order to determine how many inputs may be connected to a single output. bbas li 8 of 12
bu Dhabi Men s College, Electronics Department CMOS gates consist of field effect transistor circuits, these being formed on a piece of silicon and enclosed in a 14-pin or 16-pin DIL plastic package as for TTL devices. Combinations of P-channel (PMOS) and N-channel (NMOS) transistors are used and hence the name Complementary MOS (CMOS). CMOS gates are voltage operated devices (TTL being current operated) and, due to the use of complementary MOS transistors, their power supply consumption is very low. Typical power consumption: CMOS = 10nW and TTL = 10mW Thus, TTL devices consume of the order of 1000 times more power. Due to their voltage operation, the current capability of the output circuit of CMOS gates is less than that for TTL gates in respect of both delivering current ("sourcing") and receiving current ("sinking"). The figure below illustrates the direction of current flow in the output circuit of a gate when "sourcing" and "sinking" current. Gate Current Flow current flow "sourcing" Gate Current Flow current flow "sinking" lthough the current required by a CMOS input is much lower than that for a TTL input, the capacitance of CMOS devices is higher than for TTL devices. Hence their speed of operation is less than that for TTL gates. CMOS Logic Gates ICs In the standard series of CMOS integrated circuits, the identification numbers of all ICs start with the numeral 4 and normally having 4 digits. They are therefore referred to as the 4000 series, for example: 4001 Quad 2-input NOR gate (Four 2-input NOR gates in the IC) 4002 Dual 4-input NOR gate (Two 4-input NOR gates in the IC) 4011 Quad 2-input NND gate (Four 2-input NND gates in the IC) 4071 Quad 2-input OR gate (Four 2-input OR gates in the IC) 4049 Hex inverter (Six Inverter or NOT gates in the IC) This series of logic gates uses positive logic, and can operate on a supply voltage within the range 3V to 15V. CMOS Levels The voltage levels specified for the two logic levels are common to all 4000 series CMOS devices. For a supply, these voltages are as follows: : Logic 1 : s: Logic 1 : Logic 0 : 1.5V max 3.5V min Logic 0 : 0.05V max 4.95V min bbas li 9 of 12
bu Dhabi Men s College, Electronics Department The input values represent the voltages that will be recognized accurately as being at the respective level (0 or 1) at the input to a CMOS device. Intermediate voltages between 1.5V and 3.5V may be inaccurately identified. The output values represent the level 0 and level 1 voltages that will be present at the output of a CMOS 4000 series device that is operating within its normal specification. The input threshold voltage for a CMOS 4000 series gate is typically around half of the supply voltage, or 2.5V for a gate powered from a supply. CMOS Noise Margin Consider the situation where the output of one CMOS 4000 series gate drives the input of another. If the driving gate is operating within its specification and the supply voltage is, then: logic 1 output will exceed the minimum required logic 1 input voltage by at least 1.45V (4.95V - 3.5V). logic 0 output will be below the maximum allowable logic 0 input voltage by at least 1.45V (1.5V - 0.05V). The noise margin of 4000 series CMOS is therefore at least 1.45V in either state, as shown below 4.95V Min. (1) Noise margin = 1.45V 3.5V Min. Input (1) 1.5V Max. (0) Noise margin = 1.45V 0.05V Max. Input (0) This means that the amount of electrical noise at the output of the driving gate would have to exceed 1.45V in amplitude, before there would be any risk of a driven gate misinterpreting the logic level at its input. So the noise margin of standard CMOS running from a supply is more than three times that for standard TTL (0.4V). This relatively high noise immunity makes the use of CMOS gates preferable in conditions where a large amount of electrical noise is present. CMOS Fan-Out ecause CMOS gates are voltage operated devices, a CMOS input requires very little current (0.3 maximum). This makes the fan-out of CMOS logic extremely high. In fact, more than 50 CMOS inputs can, theoretically, be driven from a single CMOS output. However, in practical logic circuits where operating speed is important, the high input capacitance of CMOS gates is a more limiting factor than the fan-out. The more inputs that are connected to a single output, the longer will be the time taken for the gate output to change state when one of its own inputs changes. If this propagation delay time becomes too long, the circuit may no longer operate correctly. bbas li 10 of 12
Interfacing TTL and CMOS Gates bu Dhabi Men s College, Electronics Department It is sometimes possible to interface directly between TTL and CMOS gates, but the limitations of each logic family have to be taken into account when doing so. For instance, a standard TTL gate may drive a CMOS gate if the logic 1 output voltage from the TTL gate is increased. This can be achieved by using a pull-up resistor, as shown below 4.7k TTL CMOS However, the circuit will only operate correctly if the operating speed is low enough to allow for the propagation delay through the CMOS gate, and through any others that follow it. 4000 series CMOS gate cannot provide enough output current to drive a standard TTL input. However, there are variations of the CMOS range that can be directly connected to TTL. CMOS Gate Variations Two important variations on the standard 4000 series of CMOS devices have been introduced. These are: 74HC High speed CMOS devices with CMOS-compatible inputs and TTL/CMOS compatible outputs 74HCT High speed CMOS devices with TTL-compatible inputs and TTL/CMOS compatible outputs These overcome the speed limitations of 4000 series CMOS. The 74HCT series is ideal for interfacing with TTL outputs, while the 74HC series provides the high noise immunity that is a characteristic of CMOS 4000 series gates. Open Collector Gates Some TTL ICs have no internal collector load resistor provided for the output transistor of the gates. separate external load resistor is required as shown below. These gates are referred to as open collector gates. External Collector I.C. Load Resistor This arrangement enables more than one gate to feed a single output, this output being a logical function of the inputs. bbas li 11 of 12
bu Dhabi Men s College, Electronics Department The figure below shows two open collector buffers with a common output, with the truth table. O/P 0 0 0 0 1 0 1 0 0 1 1 1 With either input at logic level 0, and hence the corresponding buffer output at level 0, the combined output is at level 0. The combined output is at logic level 1 only with both inputs at level 1. The circuit performs the ND function and is referred to as the wired-nd function. The figure below shows two open collector Inverter gates with a common output with the truth table. O/P 0 0 1 0 1 0 1 0 0 1 1 0 With either input at logic level 1, and hence the corresponding inverter output at level 0, the combined output is at logic level 0. The combined output is at logic level 1 only with both inputs at level 0 - that is, when both inverter outputs are at level 1. The circuit performs the NOR function and is referred to as the wired-nor function. Multiple input TTL gates are also available with open collector outputs. These are suitable for similarly connected circuits. The circuits will give an output at logic level 1 only with all the connected gate outputs at logic level 1. Direct connection of the outputs of TTL gates having integral internal collector resistors for the output stages will not result in a logical output being obtained. The gates will take an excessive current from the supply, dependent on the input settings, but this will not normally damage the gates due to the limiting effect of the internal resistor. The outputs of CMOS gates should never be connected together directly. Standard Load The amount of current required to drive one standard input, is known as a standard load on any output. uffers re circuits designed to be able to drive more inputs than usual input current, and some gates, known as buffers. Fan-in Fan-in is a term that defines the maximum number of digital inputs that a single logic gate can accept. Most transistor-transistor logic (TTL) gates have one or two inputs, although some have more than two. typical logic gate has a fan-in of 1 or 2. Fan-out Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10 other digital gates or devices. Thus, a typical TTL gate has a fan-out of 10. bbas li 12 of 12