A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS N. Krishnapura 1 & P. Kinget 2 Lucent Technologies, Bell Laboratories, USA. 1 Currently at Columbia University, New York, NY, 10027, USA. 2 Currently at Broadcom, Irvine, CA, USA.
Programmable divider for a HiPerLAN carrier synthesizer(5 channels) f ref 23.5294 MHz phase detector loop filter VCO D f ref 0.25µm CMOS Low (~ 1.8V) Programmability D: {220, 224} D f in = D f ref high input frequency (5.15-5.3 GHz) ~ 300 mv pk (~ 0 dbm)
Outline Divider architecture: Phase switching. Timing issues. Solution: Signal retiming. Circuit implementation: High speed 2(D-Flip Flop) stage. Measurement results. Comparison & conclusions.
Phase switching divider 5.3 GHz 2.6 GHz 1.3 GHz pulse width = 23 MHz f in f in /2 4T in or 5T in f in /(4N+K) /2 0 o 90 o 180 o 270 o f in /4 X Y XB YB MUX /N SX SY SXB SYB rising edges separated by 1 cycle of f in K times per output cycle [Craninckx, JSSC 96] DECODER 4 STATE MACHINE K pulses per output cycle PULSE GENERATOR Division factor D K phase switches per output cycle: (4N + K) + No high speed feedback loops around multiple flip-flops.
f in Glitches Retiming X 1/4 f in Y X Y SY OUT elongated pulse SY OUT spurious pulse SY YON OUT modified control timing correct 4 T in 5 T in 4 T in 4 T in 5 T in incorrect clock-x to clock-y when both X & Y are in the same state. Retimer circuit: enforces control timing for each of the four possible clock transitions.
Phase switching divider with retiming retimed clocks and controls MUX f in f in /2 f in /(4N+K) /2 0 o 90 o 180 o 270 o RETIMER /N rising edges separated by 1 cycle of f in un-synchronized control signals DECODER 4 STATE MACHINE PULSE GENERATOR 4 to 8 pulses per output cycle Division factor D Retimer inserted after the second stage.
four parallel circuits Retimer: Implementation X Y SY Y X Y SY XB Y SXB YON 0 RETIMER MUX (a) (b) CY clock buffer control generator XB Y SXB Y 1 1 0 YON to MUX CY New control generated when both clocks are high. Clock and control go through identical paths. Feedforward operation high speed. multiplexed output
High speed 2 stages / latches pmos in signal path CLK (TSPC) OUT stacked devices too little headroom Q Q D D CLK Q Q D D I bias CLK CLKB (Razavi 95) (source coupled logic) Goals: Low (1.8 V) & high speed(5.5 GHz) pmos: much smaller drive than nmos.
Pseudo-nMOS low voltage latch Q Q D D CLK CLK CLKB 0.25µm CMOS, = 1.8 V: 3 stage ring osc. CMOS: 2.8 GHz. pseudo-nmos: 6 GHz.
5.5 GHz 2 stage CLK CLK CLKB CLK CLKB 0 o 180 o input ac coupling CLKB CLK CLKB 5.5 GHz 2 with 300mV pk (SE) inputs at = 1.8V. Disabled by pulling CLK, CLKB inputs to the rails.
Programmable divider retimed clocks and controls f in /2 0 o 90 o 180 o 270 o MUX f in /2 RETIMER /2 /3 /3 /3 rising edges separated by 1 cycle of f in un-synchronized control signals DECODER 4 STATE MACHINE PULSE GENERATOR 4 to 8 pulses per output cycle Division factor D {220,, 224} = 216 + {4,,8} = 2 3 3 3 + {4,,8} 3 stages-similar to 2, with gated input branches. f in /(216+K)
3 stage LOGIC IMPLEMENTATION D Q Q D 1 D Q D f clk /3 f 2 clk Q Q Q Q Q CLK CLKB CLK differential realization CLKB D 1 D 2 D 1 CLK D 2 CLKB AND gate: combined with the DFF input branches.
inp divider ~0.09 mm 2 inn Chip Photograph o/p buffer out gnd 1 st 2 2 nd 2 retimer other logic last 4 stages
0.5 0.4 0.3 0.2 0.1 0 Measurements: Sensitivity = 1.8V = 2.0V = 2.2V 0.5 0.4 V = 1.8V dd V = 2.2V dd 0.3 0.2 0.1 2 2.5 3 3.5 4 4.5 5 5.5 6 f / GHz 0 3.5 4 4.5 5 5.5 5.5 GHz operation with = 2.2 V, 300mV pk (SE) input. Changed technology: major discrepancy between models and process. V i, pk (SE) / V V i, pk (SE) / V f / GHz
Phase noise measurement setup POWER SPLITTER DIVIDER 1 DIVIDER 2 PHASE SHIFT 90 o PHASE DETECTOR SPECTRUM ANALYZER SIGNAL ANALYZER HP PHASE NOISE MEASUREMENT SYSTEM(HP 3048) Divider contributes phase noise inside the loop bandwidth. The inputs to the phase detector are 90 o apart. Measured noise = 3 db + noise of each divider. Input referred phase noise(@ 5.5 GHz): + 47dB (220x). HP83712B
Measurements: Phase Noise o/p phase noise from 2 dividers & o/p buffers. ~ -131 dbc/hz @ 1 khz offset. 1/f behavior down to 1Hz.
Summary Technology 0.25 µm CMOS Chip Area 0.09 mm 2 Vdd 2.2 V I(Vdd) 26.8 ma fin, max 5.5 GHz Sensitivity 300 mv pk., SE o/p phase noise (5.5 GHz signal i/p) -131 dbc / Hz @ 1 khz Vdd 1.8 V I(Vdd) 17.4 ma fin, max 4.5 GHz Sensitivity 300 mv pk., SE o/p phase noise (4.5 GHz signal i/p) -133 dbc / Hz @ 1 khz
Comparison of CMOS dividers This work 220 224 Tech. fin, max GHz Vdd V Pd mw Input Vpk 0.25 µm 5.5 2.2 59 0.3-83.2 De Muer 98 8/9 0.7 µm 1.5 5.0 55 0.16-93.9 Kurizu 97 4 0.15 µm 11.8 2.0 20 1.0 Craninckx 95 2 0.7 µm 1.7 3.0 7.5-87.9 Razavi 95 2 0.1 µm 13.4 2.6 26 1.3 Foroudi 95 16 1.2 µm 1.5 5.0 13 0.35 Cong 88 4/5 0.4 µm 4.2 3.5 0.5 Maeda 97 256 0.2 µm 14.5 0.6 22 1.0 Phase Noise (input ref.) dbc/hz@1khz
Conclusions Programmable divider for HiPerLAN in CMOS. Retiming circuit for reliable phase switching. 5.5 GHz low voltage 2 stage in 0.25µm CMOS. Low phase noise achieved at a high input frequency.
Acknowledgments W. Fischer for layout, V. Boccuzzi for testing. A. Dunlop, M. Banu, R. Melville, H. Wang for test equipment and support.