An Integrated, Dynamically Adaptive Energy-Management Framework for Linear RF Power Amplifiers Georgia Tech Analog Consortium Biranchinath Sahu Advisor: Prof. Gabriel A. Rincón-Mora Georgia Tech Analog and Power IC Design Laboratory School of Electrical and Computer Engineering Georgia Institute of Technology
Abstract 2 Energy-efficient, linear RF power amplifiers are critical and paramount to achieve longer battery life in state-of-the-art wireless handsets. In the proposed system, the energy-efficiency of a PA is improved by dynamically adjusting the supply voltage and current as a function of its transmitted power. System Requirements High efficiency Improvement in battery life Low voltage Single cell operation (Li-ion/NiCd/NiMH/Fuel Cell) Integrated External components, Cost Low noise Interference This work addresses the design challenges and trade-offs involved in realizing an integrated circuit (IC) for such a system with a wide range of supply voltage. Lower limit Minimum supply voltage for circuits to be operational (1.4 V) Higher limit Process technology constraints (5 V), AMI 0.5 µm CMOS
Energy-Efficient Efficient Linear PA 3 2.7 4.2 V Battery I D V DS,sat V GS increasing 3.6 V 1.5 V 3/5 V I D_MAX Display Audio Interface 2.5/5 V DSP core Baseband digital I/O DAC ADC Reduce the input power drawn from the battery as transmitter output power decreases Gain variation requires calibration with the rest of the transmitter chain LO Analog/RF 2.5 V 2.5 V PA LNA Control Signal I DQ_A I DQ_AB I DQ_C V IN = 1.4 4.2 V RF input DC-DC Converter and Dynamic Bias Circuit Power Amplifier The System V SUPPLY Q A RF Output V DS Output (0.5 5.0 V) Load
The System An Integrated Solution 4 PGND MNBUCK MNBUCK_GATE VPH1 MPBUCK_GATE VIN Integrated Power FETS SS VCON VFB Driver VOLTAGE MODE PWM CONTOLLER MUX MUX Driver Triangular wave generator MPBUCK IT Dual-mode noninverting buckboost converter for high efficiency over wide loading conditions VEAO VSHIFT AVDD PFM CONTOLLER PA Dynamic Bias Circuit IBIA VF Voltage-mode PWM controller at high PA output power AGND IBIAS Bias Current Generator Lev. Sft. Driver Driver MUX MUX Driver PFM controller at light loading conditions Integrated bandgap reference IREF VREF Bandgap Reference MPBOOST MNTGATE MPBOOST_GATE VPH2 MNBOOST_GATE MNBOOST PGND Integrated power amplifier dynamic bias circuit MODE VOUT
Dynamic Gate Bias Circuit 5 VDD = 1.4 4.2 V From buck-boost converter (0.5 5 V) Control signal (0.1 1 V) MP1 MP2 LD RF Output RC CC LG RBIAS = 40 kω I = 2.5-25 µa MN2 I = 125µA 1.25 ma MN1 IBIAS = 25-250 ma Dynamic supply block Challenge: Designing an op-amp with rail-to-rail input common mode range with V DD < V TP + V TN I X IX Die photo of the circuit VDD VIN+ V IN Power-supply-adaptive, common-mode feedforward circuit Auxiliary amplifier sets the common-mode signal for the main amplifier only when required Added power consumption, noise, offset VCM_ref Aaux IX I X Amain Vout
Buck-Boost Boost Converter PWM Mode 6 Vin MP1 MN1 Vph1 L D1 Vph2 MN2 D2 MP2 RESR MN3 ILOAD Vout V IN = 1.4 V 4.2 V V OUT = 0.5 V 5 V V RIPPLE 10-100 mv Voltage mode control Type III compensation C Drive and dead-time control Drive and dead-time control Duty cycle limit COMPBOOST Error amplifier Level shifting circuit Start-up and control signal by-pass circuit Error amplifier Gain : 70 db ICMR : 0.1 1 V OS : 0.2 V (V DD - 0.2 V) Input Offset: 10 mv Feedback control COMPBUCK Vcontrol Triangular wave generator PWM Comparators ICMR : 0.9 V 1.25 V Prop. Delay : 100 ns Input Offset: 10 mv Triangular wave generator V TW = 0.95 V 1.25 V Freq.= 0.9 1.1 MHz
Buck-Boost Boost Converter PFM Mode 7 VIN M1 Vph1 L T PMOS 2C V V V IN ( V V ) IN VOUT OUT L OUT IC [A] IL [A] IL_AVG = IOUT D2 RESR C ILOAD R1 R2 [V] VOUT VOUT_AVG [V] Gate Drive Qb S VFB Vph1 Time R TPMOS TNMOS TIDLE Gate Drive Delay Delay COMP1 VCON 7.0E-07 Key Waveforms in PFM Control 6.0E-07 Q S COMP2 Vph1 5.0E-07 PMOS ON time R PFM Controller Time (sec) 4.0E-07 3.0E-07 2.0E-07 VARIABLE DELAY BLOCK Required delay is inversely proportional to V DD Larger V DD lower T ON PMOS I L desired 1.0E-07 0.0E+00 1.4 1.9 2.4 2.9 3.4 3.9 Input supply (V)
The Building Blocks 8 Error amplifier Op-amp Input common-mode range (ICMR) By dynamically shifting the input signal as a function of supply voltage, a PMOS input stage is used. ICMR, Noise, Offset voltage Input Offset Voltage Error in output voltage = Offset voltage Closed loop gain of the converter. Depending on the accuracy requirement, offset cancellation techniques can be used. DC Gain and Bandwidth As DC gain, steady-state error IREF VREF Bandgap reference I REF = I PTAT + I CTAT V REF = I REF R Substrate vertical PNPs as diodes IX IX IX R1 R21 R23 Start-up and biasing circuit A UGF OPAMP >> Loop BW CONVERTER Architecture similar to the dynamic bias circuit NX X R22 R24
The Building Blocks 9 Triangular Wave Generator Performance Summary of the Converter V DD = 1.4-4.2 V MP 2 Specifications Target Sims. MP 3 MN 3 MP 1 MN 1 MN 2 COMP 1 COMP 2 S Q R Q MP 4 MN 4 Input voltage (V) 1.4 4.2 1.4 4.2 Voltage mode PWM controller Output voltage (V) 0.5 5 0.5 5 Peak-to-peak ripple (mv) 10 100 2 47 Efficiency (%) 60-97 % Programmable Current Source Comparators ICMR : 0.9 V 1.25 V Prop. Delay : 100 ns Input Offset: 10 mv Quiescent current (ma) 1 PFM controller Output voltage (V) 0.5 0.5 0.51 Peak-to-peak ripple (mv) 50 20 36 Efficiency (%) 50 84 % Spread spectrum triangular wave by adjusting the charging/discharging current dynamically Quiescent current (µa) 200 Potential reduction in EMI and noise
Layout of the System 10 BUCK NMOS BUCK PMOS BUCK NMOS DRIVE ERROR AMP BIAS GENERATOR BUCK COMP BOOST COMP BURST MODE CONTROLEER BUCK DTC BOOST DTC BUCK PMOS DRIVE SS GENERATOR TRIANGULAR WAVE GENERATOR PA_DYNAMIC BIAS CIRCUIT BANDGAP REFRENCE BOOST NMOS-2 BOOST NMOS-2 DRIVE BOOST NMOS-1 DRIVE BOOST PMOS DRIVE BOOST PMOS BOOST NMOS-1 System Floor Plan System Layout Layout size: 3.5 mm 3.3 mm Power transistor area more than 75 % Targeted Package: LCC 44 Design for Testability
Summary 11 IC design issues of key building blocks of a new energy-management system for linear RF PA is discussed. Key challenges with respect to implementation of low-voltage circuits are addressed. System Efficiency Enhancement Nominal voltage and current at peak PA output power Reduced supply and current as PA output power reduces Buck-Boost Converter Performance Enhancement PWM Mode at full/mode load, PFM Mode at light load Buck/Buck-Boost/Boost Mode of operation DC accuracy Low offset, wide input common-mode range opamp for error amplifier Ripple voltage/noise spectrum Spread-spectrum clocking Transient accuracy Higher bandwidth, slew rate Future Work: Performance evaluation of the IC