600 ma Step-Dwn DC/DC Cnverter with Built-in Inductr FEATURES Built-in inductr and transistrs Operating Input Vltage Range: 2.0 V ~ 6.0 V (A/B/C types) r 1.8 V ~ 6.0 V (G type) Output Vltage Range: 0.8 V ~ 4.0 V Output Vltage Errr: ±2% Output Current: 600 ma High Efficiency: 90% (V IN = 4.2 V, V OUT = 3.3V) Oscillatin Frequency: 3 MHz Maximum Duty Cycle: 100% Operating Mdes: PWM, PWM/PFM aut select Functins: Built-in Current Limit, High Speed Lad Capacitr Discharge, Sft start Operating Ambient temperature: -40 ~ +85 0 C Package Size: 2.5 x 2.0 x 1.0 mm EU RHS Cmpliant, Pb Free APPLICATION Mbile Phnes Bluetth headsets Digital hme appliances Office autmatin equipment Varius prtable equipment DESCRIPTION The series are synchrnus step-dwn DC/DC cnverters with an inductr and a cntrl IC in ne tiny (2.5 x 2.0 x 1.0 mm) package. A stable pwer supply with an utput current f 600 ma requires nly tw capacitrs cnnected externally. Operating vltage range is frm 2.0 V t 6.0 V (1.8 V ~ 6.0 V fr IXD920xG versin). Output vltage is internally set in a range frm 0.8 V t 4.0 V in 0.05 V increments. The device perates at 3.0 MHz switching frequency, and includes 0.42 Ω P- channel switching transistr and 0.52 Ω N-channel transistr fr synchrnus rectificatin. The IXD9205 series perate in PWM mde, while IXD9206 series autmatically switching between PWM/PFM mdes. An autmatic PWM/PFM switching allws fast respnse t the lad changes, lw ripple nise, and high efficiency ver the full range f lads. CE pin allws set device int stand-by mde with a current cnsumptin belw 1.0 µa. The built-in Under Vltage Lckut (UVLO) functin frces the internal switching transistr OFF when input vltage becmes less than 1.4V series f B and G versin have a fast sft start functin internally set at 0.25 ms (typ). series f B, C, and G versin have als fast lad capacitr C L aut discharge functin, which allws fast C L discharge thrugh switch lcated between the L X and V SS pins. When the devices enter stand-by mde, utput vltage quickly returns t the V SS level because f this functin. TYPICAL APPLICATION CIRCUIT TYPICAL PERFORMANCE CHARACTERISTIC Efficiency vs. Output Current (f OSC = 3.0 MHz, V OUT = 3.3 V) Pins L1 L X and L2 V OUT shuld be cnnected externally 2014 IXYS Crp. 1 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS UNITS V IN Pin Vltage V IN 0.3 ~ 6.5 V L X Pin Vltage V LX 0.3 ~ V IN + 0.3 1 V V OUT Pin Vltage V OUT 0.3 ~ 6.5 V FB Pin Vltage V FB 0.3 ~ 6.5 V CE/MODE Pin Vltage V CE 0.3 ~ 6.5 V Lx Pin Current I LX ±1500 ma Inductr Current at T = 40 0 C I LMAX 1000 ma Pwer Dissipatin P D 1000 2) mw Operating Temperature Range T OPR 40 ~ + 85 Strage Temperature Range T STG 50 ~ +105 NOTE: 1. L X pin vltage shuld nt exceed V IN +0.3 V r 6.5 V, which is less. 2. Pwer dissipatin shwn fr a PCB munted part. Please refer t page 15 fr mre infrmatin. ELECTRICAL OPERATING CHARACTERISTICS A series, Ta = 25 0 C PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT CIRCUIT Operating Vltage Range V IN 2.0-6.0 V Output Vltage V OUT V IN = V CE = 5.0 V, I OUT = 30 ma E-1 E-2 E-3 V Maximum Output Current I OUT_MAX V IN = V OUT(E) + 2.0 V, V CE = 1.0 V 8) 600 ma UVLO Vltage V UVLO V CE = V IN, V OUT = 0 1), 10) 1.00 1.40 1.78 V Supply Current IXD9205 46 65 I Q V IN = V CE = 5.0 V, V OUT = V OUT(E) x 1.1 V IXD9206 21 35 0 C 0 C µa Standby Current I STB V IN = 5.0 V, V CE = 0 V, V OUT = V OUT(E) x 1.1 V 0 1.0 µa Oscillatin Frequency f OSC V IN = V OUT(E) + 2 V, V CE = 1.0 V, I OUT = 100 ma 2550 3000 3450 khz PFM Switching Current I PFM 11) P-channel ON time maximum t PON_MAX 11) V IN = V CE = V OUT(E) + 2 V,, I OUT = 1 ma E-4 E-5 E-6 ma V IN = V CE = V OUT(T) + 1 V, I OUT = 1 ma 2D max 3D MAX Maximum Duty Cycle Rati D MAX V IN = V CE = 5.0 V, V OUT = V OUT(E) x 0.9 V 100 % Minimum Duty Cycle Rati D MIN V IN = V CE = 5.0 V, V OUT = V OUT(E) x 1.1 V 0 % Efficiency 2) EFFI V IN = V CE = V OUT(E) + 1.2 V, I OUT = 100 ma E-7 % L X H ON Resistance 1 3) R LXH1 V IN = V CE = 5.0 V, V OUT = 0 V, I LX = 100 ma 0.35 0.55 Ω L X H ON Resistance 2 3) R LXH2 V IN = V CE = 3.6 V, V OUT = 0 V, I LX = 100 ma 0.42 0.67 Ω L X L ON Resistance 1 4) R LXL1 V IN = V CE = 5.0 V 0.45 0.65 Ω L X L ON Resistance 2 4) R LXL2 V IN = V CE = 3.6 V 0.52 0.77 Ω L X H Leakage Current 5) I LXH V IN = V CE = 5.0 V, V OUT = 0 V, V LX = 5.0 V 0.01 1.0 µa L X L Leakage Current 5), 15) I LXH V IN = V CE = 5.0 V, V OUT = 0 V, V LX = 5.0 V 0.01 1.0 µa Current Limit 10) I LIM V IN = V CE = 5.0 V, V OUT = V OUT(E) x 0.9 V 7) 900 1050 1350 ma Output Vltage Temperature -40 0 C T Characteristics OPR 85 0 C, I OUT = 30 ma ±100 ppm/ 0 C CE H Vltage 13) V CEH V OUT = 0 V 0.65 6.0 V CE L Vltage 14) V CEL V OUT = 0 V 0 0.25 V CE H Current I ENH V IN = V CE = 5.0 V, V OUT = 0 V -0.1 0.1 µa CE L Current I ENL V IN = 5.0 V, V CE = 0 V, V OUT = 0 V -0.1 0.1 µa Sft-Start Time Latch Time 6) A, C versin 0.5 0.9 2.5 t SS I OUT = 1 ma ms B, G versins E-11 E-12 V t IN = V CE = 5.0 V, V OUT = 0.8 x V OUT(E), L X shrt with LAT 1.0 20.0 ms 1 Ω resistr t grund 2014 IXYS Crp. 2 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
ELECTRICAL OPERATING CHARACTERISTICS (CONTINUED) PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT CIRCUIT Shrt Prtectin Threshld Vltage V SHORT V IN = V CE = 5.0 V, L X shrt with 1 Ω resistr t 12) E-8 E-9 E-10 V grund C L Discharge Resistance 13) R CLD V IN = L X = 5 V, V CE = 0, V OUT = pen 200 300 450 Ω Inductance Value L Test frequency 1 MHz 1.5 µh Inductr Current Maximum I LMAX T = 40 0 C 1000 ma NOTE: Test cnditins: Unless therwise stated, V IN = 5.0 V, V OUT (E) = Nminal Vltage 1) Including hysteresis perating vltage range 2) EFFI = {(utput vltage utput current) / (input vltage input current)} 100% 3) ON resistance (Ω) = (V IN - Lx pin measurement vltage) / 100mA 4) Design target value 5) A 10µA (maximum) current may leak at high temperature 6) Time frm mment when V OUT is shrted t GND via 1 Ω resistr t the mment, when Current Limit generates pulse stpping L X scillatins 7) When V IN is less than 2.4 V, current limit may nt be reached because f vltage drp acrss ON resistance 8) When the difference between input and utput vltage is small, sme cycles may be skipped cmpletely befre current maximizes. If lad current increases in this state, utput vltage will decrease because f the vltage drp acrss P-channel transistr 9) Current limit dentes the level f an inductr peak current 10) Vltage, when L X pin vltage is L =+0.1 V ~ -0.1 V 11) IXD9206 series nly 12) V OUT vltage at which L X pin state changes frm H t L within 1 ms 13) B, C, and G versins nly 14) Versin A nly E-TABLES Output Vltage Errr PFM Switching Current NOMINAL OUTPUT V OUT, (V) I PFM, (ma) NOMINAL OUTPUT VOLTAGE E-1 E-2 E-3 E-4 E-5 E-6 VOLTAGE V OUT(T), V MIN TYP MAX MIN MAX TYP 1.00 0.980 1.000 1.020 V OUT(T) < 1.2V 190 260 350 1.20 1.176 1.200 1.224 1.2 V < V OUT(T) 1.75 V 180 240 300 1.40 1.372 1.400 1.428 1.8 V< V OUT(T) 170 220 270 1.50 1.470 1.500 1.530 1.75 1.715 1.750 1.785 1.80 1.764 1.800 1.836 1.90 1.862 1.900 1.938 2.50 2.450 2.500 2.550 2.80 2.744 2.800 2.856 2.85 2.793 2.850 2.907 3.00 2.940 3.000 3.060 3.30 3.234 3.300 3.366 Efficiency Shrt Prtectin Threshld Vltage NOMINAL EFFICIENCY, NOMINAL V SHORT, (V) OUTPUT % OUTPUT A, B, C VERSIONS G VERSION VOLTAGE E-7 VOLTAGE E-8 E-9 E-10 E-8 E-9 E-10 V OUT(T), V V OUT(T), V MIN TYP MAX MIN TYP MAX 1.00 79 1.00 0.375 0.500 0.625 0.188 0.250 0.313 1.20 82 1.20 0.450 0.600 0.750 0.225 0.300 0.375 1.40 83 1.40 0.525 0.700 0.875 0.263 0.350 0.438 1.50 84 1.50 0.563 0.750 0.938 0.282 0.375 0.469 1.75 1.90 85 1.75 0.656 0.875 1.094 0.328 0.438 0.547 2.50 3.30 86 1.80 0.675 0.900 1.125 0.338 0.450 0.563 1.90 0.713 0.950 1.188 0.357 0.475 0.594 2.50 0.938 1.250 1.563 0.469 0.625 0.782 2.80 1.050 1.400 1.750 0.525 0.700 0.875 2.85 1.069 1.425 1.781 0.535 0.713 0.891 3.00 1.125 1.500 1.875 0.563 0.750 0.938 3.30 1.238 1.650 2.063 0.619 0.825 1.032 2014 IXYS Crp. 3 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
Sft-Start Time ( B and G versins nly) NOMINAL OUTPUT t SS, (ms) VOLTAGE E-11 E-12 V OUT(T), V TYP MAX 0.8 V < V OUT(T) 1.75 V 0.25 0.4 1.8 V < V OUT(T) 4.0 V 0.32 0.5 PIN CONFIGURATION NOTE: The dissipatin pad shuld be sldered in recmmended munt pattern and metal masking t enhance munting strength and heat release. If the pad needs t be cnnected t ther pins, it shuld be cnnected t the V SS (N 2 and N 5) pins. V SS pins (N. 2 and 5) shuld be tied tgether and cnnected t grund plane n the bard. PIN ASSIGNMENT PIN NUMBER PIN NAME FUNCTIONS 1 L X Switching Nde 2, 5 V SS Grund 3 V OUT Fixed Output Vltage 4 CE Enable (Active HIGH) 6 V IN Pwer Input 7 L1 Inductr Cnnectin 8 L2 Inductr Cnnectin BLOCK DIAGRAMS A Series B/C/G Series Internal dides include an ESD prtectin and a parasitic dide BASIC OPERATION The series cnsists f a Reference Vltage surce, Ramp Wave Generatr, Errr Amplifier, PWM Cmparatr, Phase Cmpensatin circuit, utput vltage resistive divider, P-channel switching transistr, N- channel transistr fr the synchrnus switch, Current Limiter circuit, UVLO circuit, and thers. (See the blck diagrams abve.) The Errr Amplifier cmpares utput vltage divided by internal resistrs R 1 /R 2 with the internal reference vltage. Amplified difference between these tw signals applies t the ne input f the PWM Cmparatr, while ramp vltage frm the Ramp Wave Generatr applies t the secnd input. Resulting PWM pulse determines switching transistr ON time. It ges thrugh the Buffer and it appears at the gate f the internal P-channel switching transistr. This cntinuus prcess stabilizes utput vltage. 2014 IXYS Crp. 4 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
The Current Feedback circuit mnitrs current f the P-channel transistr at each switching cycle, and mdulates utput signal frm the Errr Amplifier t prvide additinal feedback. This guarantees a stable cnverter peratin even with lw ESR ceramic lad capacitr. Reference Vltage Surce The Reference Vltage Surce prvides the reference vltage t ensure stable utput vltage f the DC/DC cnverter. Ramp Wave Generatr The Ramp Wave Generatr prduces ramp wavefrm signal needed fr PWM peratin, and signals t synchrnize all the internal circuits. It perates at internally fixed 1.2 MHz r 3.0 MHz frequency. Errr Amplifier The Errr Amplifier mnitrs utput vltage thrugh resistive divider cnnected t V OUT (FB) pin. If utput vltage falls belw preset value and Errr Amplifier s input signal becmes less than internal reference vltage, the Errr Amplifier/s utput signal increases. That results in wider PWM pulse and respectively lnger ON time fr switching transistr t increase utput vltage. The gain and frequency characteristics f the errr amplifier utput are fixed internally t ptimize IC perfrmance. Current Limiter The Current Limiter circuit mnitrs current flwing thrugh the P-channel transistr cnnected t the Lx pin, and cmbines functin f the current limit and peratin suspensin. When transistr s current is greater than a specified level, the Current Limiter turns ff P-channel transistr immediately. After that, the Current Limiter turns ff t, returning t mnitring mde. The driver transistr turns n at the next cycle, but the Current Limiter will turn it ff immediately, if an ver- current exists. When the ver current state is eliminated, the IC resumes its nrmal peratin. The IC waits fr end f the ver current state repeating abve steps (t1 n figure belw). If an ver-current state cntinues fr a few ms with IC repeatedly perfrming abve steps, the Current Limiter latches the P-channel transistr in OFF state, and IC suspends peratins (t2 n figure belw). T restart IC peratin after this cnditin, either CE pin shuld be tggled H L H, r V IN pin vltage shuld be set belw UVLO t resume peratins frm sft start. The suspensin mde is nt a standby mde. In the suspensin mde, pulse utput is suspended; hwever, internal circuitries remain in peratin mde cnsuming pwer. Shrt- Prtectin The shrt-circuit prtectin mnitrs the R FB1 /R FB2 divider vltage (FB pint in the blck diagram). If utput is accidentally shrted t the grund, FB vltage starts falling. When this vltage becmes less than half f the reference vltage (V REF ) and P-channel switching transistr s current is mre than the I LIM threshld, the Shrt- Prtectin turns ff and latches quickly the P-channel transistr. 2014 IXYS Crp. 5 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
At D/E/F/G series, Shrt Prtectin starts nce FB vltage becmes less than 0.25 f reference vltage (V REF ), disregard t transistr s current. T restart IC peratin after this cnditin, either EN pin shuld be tggled H L H, r V IN pin vltage shuld be set belw UVLO t resume peratins frm sft start. The sharp lad transients creating a vltage drp at the V OUT, prpagate t the FB pint thrugh C FB, that may result in Shrt prtectin perating at vltages higher than 1/2 V REF vltage. UVLO When the V IN pin vltage becmes 1.4V r lwer, the P-channel transistr is frced OFF t prevent false pulse utput caused by unstable peratin f the internal circuitry. When the V IN pin vltage becmes 1.8 V r higher, switching peratins resume with the sft start. The sft start functin perates even when the V IN vltage falls belw the UVLO threshld fr a very shrt time. The UVLO circuit des nt cause a cmplete shutdwn f the IC, but causes pulse utput t be suspended; therefre, the internal circuitry remains in peratin. PFM Switch Current In PFM mde, the IC keeps the P-channel transistr n until inductr current reaches a specified level (I PFM ). P-channel transistr s ON time is equal t ON = L I PFM / (V IN - V OUT ), µs, where L is an inductance in µh, and I PFM is a current limit in A. PFM Duty Limit In PFM mde, P-channel ON time maximum (t PON_MAX ) is set t 2D MAX, i.e. tw perids f the switching frequency. Therefre, under cnditins, when the ON time increases (i.e. step-dwn rati is small), it is pssible that P-channel transistr t be turned ff, even when inductr current des nt reach t I PFM. (See Figures 1 and 2 belw) Figure 1 Figure 2 C L High Speed Discharge The B, C, and G series can quickly discharge the utput capacitr (C L ) t avid applicatin malfunctin, when CE pin set lgic LOW t disable IC. C L Discharge Time is prprtinal t the resistance (R) f the N-channel transistr lcated between the L X pin and grund and the utput C L capacitance as shwn belw. V - Output vltage after discharge V OUT(E) - Output vltage R = 300 Ω (Typical value) t DSH = RC L x Ln (V OUT(E) / V), where 2014 IXYS Crp. 6 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
Output Vltage Discharge Characteristics CE Pin Functin The series enter the shut dwn mde, when a LOW lgic-level signal applies t the CE pin. In the shutdwn mde, IC current cnsumptin is ~0 µa (Typical value), with the Lx and V OUT pins at high impedance state. The IC starts its peratin when a HIGH lgic-level signal applies t the CE. Sft Start Sft start time is available in tw ptins via prduct selectin. The sft-start time f series is ptimized by using internal circuits. The definitin f the sft-start time is the time when the utput vltage ges up t the 90% f nminal utput vltage after the IC is enabled by CE H signal. TYPICAL APPLICATION CIRCUIT EXTERNAL COMPONENTS f OSC 3.0 MHz C IN, µf 4.7 C L, µf 10 Capacitrs shuld be X7R r X5R series t minimize pwer lsses. 2014 IXYS Crp. 7 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
LAYOUT AND USE CONSIDERATIONS 1. Wire external cmpnents as clse t the IC as pssible and use thick, shrt cnnecting traces t reduce the circuit impedance. Please, pay special attentin t the V IN and GND wiring. Switching nise, which ccurs frm the GND, may cause the instability f the IC, s, psitin V IN and V CL capacitrs as clse t IC as pssible (See recmmended layut n the right). 2. Transitinal vltage drps r vltage rising phenmenn culd make the IC unstable if ratings are exceeded. 3. The series are designed t wrk with ceramic utput capacitrs. Hwever, if the difference between input and utput vltages is t high, a ceramic capacitr may fail t absrb the resulting high switching energy and scillatin culd ccur. In this case, cnnect an electrlytic capacitr in parallel t ceramic ne t cmpensate fr insufficient capacitance. 4. In PWM mde, IC generates very narrw pulses, and there is a pssibility that sme cycles will be skipped cmpletely, if the difference between V IN and V OUT is high. 5. If the difference between V IN and V OUT is small, IC generates very wide pulses, and there is a pssibility that sme cycles will be skipped cmpletely at the heavy lad current. 6. When drput vltage r lad current is high, Current Limit may activate prematurely that will lead t IC instability. T avid this cnditin, chse inductr s value t set peak current belw Current Limit threshld. Calculate the peak current accrding t the fllwing frmula: I PK = (V IN - V OUT ) x D / (2 x L x f OSC ) + I OUT, where L - Inductance f OSC -- Oscillatin Frequency D Duty cycle 7. Inductr s rated current exceeds Current Limit threshld f 1050 ma t avid damage, which may ccur until P-channel transistr turns ff after Current Limiter activates, but pulse current may exceed this value(see figure belw). Current flws int P-channel transistr reaches the current limit (I LIM). Current is mre than I LIM due the circuit s delay time frm the current limit detectin t the P-channel transistr OFF. The inductr s current time rate becmes quite small. IC generates very narrw pulses fr several millisecnds. The circuit latches, stpping peratin. 8. If V IN vltage is less than 2.4 V, current limit threshld may be nt reached due vltage drp caused by switching transistr s ON resistance 9. Latch time may becme lnger r latch may nt wrk due electrical nise. T avid this effect, the bard shuld be laid ut s that input capacitrs are placed as clse t the IC as pssible. 10. Use f the IC at vltages belw recmmended vltage range may lead t instability. 11. At high temperature, utput vltage may increase up t input vltage level at n lad, because f the leakage current f the driver transistr. 12. High step-dwn rati and very light lad may be cause f intermittent scillatins in PWM mde. 13. In PWM/PFM autmatic switching mde, IC may becme unstable during transitin t cntinuus mde. Please verify with actual cmpnents. 2014 IXYS Crp. 8 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
TEST CIRCUITS ON Resistance = (V IN V OUT/100 ma R PULL = 1 Ω External Cmpnents C IN = 4.7 µf (ceramic), C L = 10 µf (ceramic) L = 1.5 µh R PULL = 200 Ω 2014 IXYS Crp. 9 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
TYPICAL PERFORMANCE CHARACTERISTICS (1) Efficiency vs. Output Current (2) Output Vltage vs. Output Current CIN = 4.7 µf, CL= 10 µf (3) Ripple Vltage vs. Output Current (4) Oscillatin Frequency vs. Ambient Temperature (5) Supply Current vs. Ambient Temperature (6) Output Vltage vs. Ambient Temperature 2014 IXYS Crp. 10 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
TYPICAL PERFORMANCE CHARACTERISTICS (Cntinued) (7) UVLO Vltage vs. Ambient Temperature (8) CE H Vltage vs. Ambient Temparature (9) CE L Vltage vs. Ambient Temperature (10) Sft Start Time vs. Ambient Temperature (11) ON Resistance vs. Ambient Temperature (12) Start Wave Frm IXD920xB333AR-G 2014 IXYS Crp. 11 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
(13) Sft Start Time vs. Ambient Temperature (14) C L Discharge Time vs. Ambient Temperature IXD920xB333AR-G IXD920xB333AR-G (15) Lad Transient Respnse MODE: PWM/PFM Aut Switching IXD9206A183AR-G IXD9206A183AR-G IXD9206A183AR-G Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div IXD9206A183AR-G Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div 2014 IXYS Crp. 12 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
TYPICAL PERFORMANCE CHARACTERISTICS (Cntinued) (15) Lad Transient Respnse (Cntinued) MODE: PWM IXD9205A183AR-G IXD9205A183AR-G IXD9205A183AR-G Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div IXD9205A183AR-G Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div ORDERING INFORMATION IXD9205- PWM Mde nly IXD9206- PFM/PWM Mde aut switching Ch1 IOUT, Ch2 VOUT 50 mv/div, Time 100 µs/div DESIGNATOR DESCRIPTION SYMBOL DESCRIPTION NOTE: A V IN 2 V, N C L aut discharge, standard sft start B V Type f DC/DC Cntrller IN 2 V, C L aut discharge, fast sft start C V IN 2 V, C L aut discharge, standard sft start G V IN 1.8 V, C L aut discharge, fast sft start - integer part, - decimal part, i.e. V OUT = 2.8 V - = 2, = 8 Fixed Output Vltage, V 2) 08-40 0.05 V increments: 0.05 = A, 0.15 = B, 0.25 = C. 0.35 = D, 0.45 = E, 0.55 = F, 0.65 = H, 0.75 = K, 0.85 = L, 0.95 = M V OUT = 2.85 V - = 2, = L Oscillatin Frequency 3 3.0 MHz - 1) Packages (Order Limit) AR-G CL-2025 (3000/reel) 1) The -G suffix dentes halgen and antimny free, as well as being fully RHS cmpliant. 2) Standard utput vltages are: 1.0, 1.2, 1.4, 1.5, 1.75, 1.8, 1.9, 2.5, 2.8, 2.85, 3.0, and 3.3 V. Cntact lcal representative fr mre infrmatin if ther vltages in the range frm 0.8 t 4.0 V require. 2014 IXYS Crp. 13 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
PACKAGE DRAWING AND DIMENSIONS (Units: mm) CL-2025 Bttm View Reference Pattern Layut Reference Metal Mask Design 2014 IXYS Crp. 14 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
PACKAGE POWER DISSIPATION CL-2025 Pwer Dissipatin The pwer dissipatin varies with the munt bard cnditins. Please use this data as a reference nly. 1. Measurement Cnditins: Cnditin: Ambient: Sldering: Bard: Material: Thickness: Thrugh-hle: Munt n a bard Natural cnvectin Lead (Pb) free Dimensins 40 40 mm (1600 mm 2 in ne side) Cpper (Cu) traces ccupy 50% f the bard area n tp and bttm layers Package heat sink tied t the cpper traces. Glass Epxy (FR-4) 1.6 mm 4 x 0.8 Diameter 2. Pwer Dissipatin vs. Ambient Temperature Ambient Temperature, 0 C Bard Munt (Tjmax = 125 0 C) Pwer Dissipatin Pd, mw 25 1000 85 250 Thermal Resistance, 0 C/W 80 Evaluatin Bard (Unit: mm 2014 IXYS Crp. 15 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
MARKING CL-2025 Represents prduct series MARK PRODUCT SERIES 4 IXD9205Axxxxx-G C IXD9205Bxxxxx-G IXD9205Gxxxxx-G K IXD9205Cxxxxx-G 5 IXD9206Axxxxx-G D IXD9206Bxxxxx-G IXD9206Gxxxxx-G L IXD9206Cxxxxx-G Represents integral part f the vltage value OUTPUT VOLTAGE, MARK V IXD920xA/B/C IXD920xG 0.x F U 1.x H V 2.x K X 3.x L Y 4.x M Z Represents decimal part f the Vltage value V OUT, V MARK x.00 0 x.05 A x.10 1 x.15 B x.20 2 x.25 C x.30 3 x.35 D x.40 4 x.45 E x.50 5 x.55 F x.60 6 x.65 H x.70 7 x.75 K x.80 8 x.85 L x.90 9 x.95 M Represents prductin lt number 01~09 0A~0Z 11~9Z A1~A9 AA~AZ B1~ZZ in rder (G, I, J, O, Q, and W excluded) 2014 IXYS Crp. 16 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice
Warranty and Use IXYS CORP. MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. IXYS Crp. prducts are nt designed, intended, r authrized fr use as cmpnents in systems intended fr surgical implant int the bdy, r ther applicatins intended t supprt r sustain life, r fr any ther applicatin in which the failure f the IXYS Crp. prduct culd create a situatin where persnal injury r death may ccur. IXYS Crp. reserves the right t make changes t r discntinue any prduct r service described herein withut ntice. Prducts with data sheets labeled "Advance Infrmatin" r "Preliminary" and ther prducts described herein may nt be in prductin r ffered fr sale. IXYS Crp. advises custmers t btain the current versin f the relevant prduct infrmatin befre placing rders. diagrams illustrate typical semicnductr applicatins and may nt be cmplete. IXYS Crp. 1590 Buckeye Dr. Milpitas, CA 95035-7418 Phne: 408. 457.9000 Dcument N: IXD9205_DS Fax: 408. 496.0222 Revisin: N0 http://www.ixys.cm Issue date: 4/24/2014 2014 IXYS Crp. 17 Dc. N. IXD9205_DS, Rev. N0 Characteristics subject t change withut ntice