Volume 117 No. 16 2017, 757-76 ISSN: 1311-8080 (printed version); ISSN: 131-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu DWINDLING OF HARMONICS IN CML INVERTER USING GENETIC ALGORITHM OPTIMIZATION K. Ravi 1, T.Rammohan 2 1 Associate Professor, Karpagam college of Engineering, Coimbatore, India 2 Professor and HoD, EEE department, Karpagam College of Engineering Coimbatore, India Abstract: Devices whose outputs are non linear to inputs are responsible sources for creating the undesirable harmonics. Inevitably it is very important task to control the unwanted harmonics. We are right here to discuss about the Total Harmonic Distortion (THD) reduction in the output voltage of multilevel inverters. We know that the harmonics can be reduced by avoiding non fundamental frequencies and it can be achieved regulating the switching on and off angles of switches. In this paper the level of THD of the inverter device by applying switching angles obtained by Genetic algorithm is discussed. In this paper about the one of the new methodology adopted to pull down the harmonic distortion in multilevel inverters. The main advantage of this new topology is it reduces the number of switches compared to conventional cascaded H-bridge multilevel inverter and as well it be extended to any number of levels. The modes of operations of nine level inverter are outlined, as similar modes will be realized for higher levels. Simulations of nine level of the proposed inverter topology along with experimental results are presented. This paper enlighten with the analysis and simulation of the nine level inverter. This paper portray the nine level inverter with harmonics reduction along with the reduction of switches. The harmonic reduction is achieved by choosing suitable switching angles by Genetic algorithm. The functionality verification of the nine level inverter is done using MATLAB. Keywords: Genetic algorithm (GA), Total harmonic distortion (THD), multilevel inverter, THD minimization. 1. Introduction Of late, high quality power is necessary for medical, research & industrial applications to bring in to being lovely quality results & for correct evaluation. In this paper, an attempt has been made to improve the quality of power. A single phase nine level cascaded inverter with symmetrical dc supply is designed to reduce the harmonic parts of the output voltage. Multilevel inverters continue to get increasingly attention because of their high voltage operation capability, low switching losses, high efficiency & low output of electromagnetic interference (EMI),[1][2]. The preferred output of a multilevel inverter is constructed with several sources of dc voltages. With an increasing number of dc voltage sources, the inverter voltage waveform approaches a virtually sinusoidal waveform while using a low switching frequency method [3]. This ends in low switching losses, & because several dc sources are used to synthesize the total output voltage, intern every switch experiences a low level of dv/dt then to a single level inverter. Consequently, the multilevel inverter know-how is a promising know-how for high power electric devices such as utility applications. Multilevel voltage source inverter using with separate dc sources (SDCSs), hereafter called a cascaded multilevel inverter technically superior to other multi-level structures in term of its construction is simple & modular. It also needs the less number of output voltage levels without increase in power circuit. In addition, it overcome the need of additional clamping diodes or voltage balancing capacitors. [, 5]. An important key in designing an effective & efficient cascaded H-bridge multilevel inverter is to make positive that the total harmonic distortion (THD) in the output voltage waveform is tiny. The level of the dc sources was assumed to be equal & constant, which is probably not to be case in application even if the sources are nominally equal. There is roughly main types of transformer less multilevel inverter topologies, which have been studied & received considerable interest from high power inverter method manufactures: the flying capacitor inverter, the diode clamped inverter & the cascaded inverter. All share the same property, which is that the output filter can be dramatically reduced, & the usual bandwidth limit induced by the switching frequency can be reconsidered. Among these inverter topologies, the flying capacitor inverter is difficult to be appreciated because every capacitor has to be charged with different voltages as the voltage level changes. This paper elucidate the method of harmonic distortion reduction is achieved by the new topology of multilevel inverters using programmed Pulse Width Modulation technique. This novel topology has the merits of its decreased number of switches match up to 757
the usual cascaded H-bridge inverter for the equal number of levels. The similar mode of operation of a nine level inverter can be realized for higher levels. The inverter operation is controlled by using switching angles with help of PWM pulse generator. These angles calculated by solving the waveform equations using Genetic Algorithm. The simulation of higher levels of the proposed inverter topology is carried out using MATLAB. The validity of the proposed topology & the harmonic elimination technique are verified experimentally for nine level inverter. 2. Nine Level Inverter 2.1 Existing System of Nine Level Inverter A single phase nine level inverter constructed with four H-bridge inverters, each bridge can produce three output voltages namely +Vdc, 0 or Vdc, hereby the whole inverter can generate nine voltage levels. Every H-bridge has to be operated only once each half cycle of the main harmonic. The harmonics produced during this operation is the fundamental harmonic with addition to odd sine harmonics. Figure 1 shows the diagram conventional nine level cascaded inverter. This multi-level inverter is constructed from several fullbridge inverters. The AC outputs of every different level of the full bridge inverters are connected in series in such a way that the output voltage waveform becomes the sum of the inverter outputs. The switching angles α1, α2, α3, and α are calculated at different values of the main harmonics, so as to result with absolute values of the 5th, 7th, and 11th harmonics, by applying a selective harmonic elimination technique, [6][7]. All the unwanted low order harmonics till the 11th harmonic are nipped in the output voltage of the cascaded multilevel inverter. levels like normal multilevel inverter topologies,. The inverter performance like output voltage, load current, and control signals are shown in Figure.3. The projected inverter is operated in three different modes namely powering mode, free wheeling mode and regenerating mode according to the polarity of the load voltage and current. These modes of operation will be repeated irrespective of the levels of the inverter. 2.3 Calculating The Switching Angles The firing angles of switches as α1, α2, α3, and α are of the multilevel inverter are considered as variables and it is to be calculated. Vdc is the voltage of the DC sources which are shown in Figure 3. 2.2 Proposed System of Nine Level Inverter The projected nine level inverter has the merit of diminish number of switches compared to the same number of levels of standard cascaded H-bridge and diode-clamped multilevel inverters. The new nine level inverter model consists of four dc source. The output terminal voltages of different level inverters are connected in series. The ten switches, T1-T10 are adjusted to different combinations so that each inverter level can generate four different voltage outputs, +Vdc, -Vdc, and zero. The output terminals of each level of full-bridge inverters are connected in series such that the total output voltage waveform is the summation of the every inverters output. A proposed single-phase nine level inverter is shown in Figure 2. In the proposed new nine level inverter, the four main switches in H-bridge configured as T1 to T, and six auxiliary switches T5, T6, T7, T8, T9 and T10. The proposed topology can be extended to any number of Figure 1. Conventional Nine level cascaded inverter 758
In this circuit, all the DC sources voltages are equal. Every full-bridge of the inverter produces a three level waveform +Vdc,0, -Vdc. The number of levels (L) of an inverter is calculated by L = 2S+1. where S is the number of DC sources that is equal to number of switching angles.. O/P Vout Table 1. The Voltage level and switch states of proposed nine level Inverter Switch State T1 T2 T3 T T5 T6 T7 T8 T9 T10 0 0 0 0 0 0 0 0 1 1 1 V1 1 0 0 1 0 0 0 0 0 0 V1+2 1 0 0 1 1 0 0 0 0 0 V1+2 +3 1 0 0 1 1 1 0 0 0 0 V1+2+ 3+ 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 V1+2 +3 0 1 1 1 1 1 0 0 0 0 V1+2 0 1 1 1 1 0 0 0 0 0 V1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 3. Formulation of the problem Figure 2. Power diagram of proposed Nine Level Inverter In this approach, the number of output phase voltage levels is defined by M = 2S+1, where S is the number of DC sources. The switching states of nine level inverter are summarized in table 1. The Fourier series of the general quarter wave symmetric waveform, similar to that of Fig.3, with switching angles α1, α2, α3 and α per quarter cycle is given by V out ( ω t ) = a 2 m + 1 sin( 2 m + 1 ) t ( 1 ) m = 0 = V k cos( 2 m + 1 ) α k ( 2 ) π ( 2 m + 1 ) Where V K is the increase in voltage value from each switching angle to another. Assuming regular staircase waveform (V1=V2=...=Vs=E), the amplitude of the harmonic voltage V 2m+1 is given by the values of a 2m+1 i.e. S E V 2m + 1 = cos(2m + 1) αk ( 3) π (2m + 1) k = 1 For the nine level inverter four switching angles α1, α2, α3, α are available, and the first four non zero harmonics in the output line voltages of the three phase inverter are V 1 = E [ cosα1 + cosα2 + cosα3 + cosα ] ( ) π V 5 = E [ cos5α1 + cos5α 2 + cos5α 3 + cos5α ] ( 5) 5π V 7 = E [ cos7α1 + cos7α 2 + cos7α 3 + cos7α ] ( 6) 7π V 11 = E [ cos11α 1+ cos11α 2 + cos11α 3+ cos11α ] ( 7) 11π These four relations will be turned to be four equations that are solved to obtain the values of the switching angles α1, α2, α3, and α; by setting: V 1 = The required amplitude of the main harmonic, V 5 = 0, V 7 = 0 V 11 = 0. Figure 3. Output phase voltage waveform diagram 759
Genetic algorithm to calculate optimum switching angels Genetic algorithm is a Mathematical model, which gives solutions to the optimization problems by referring its genetic processes and the history of evolution by using genetic operators like reproduction, crossover, mutation etc.. Genetic algorithm is still a novel technique for PWM-SHE technique. It imitates biological evolution by using genetic operators like reproduction, crossover, mutation, etc. Optimization in GA means maximization [8]. In cases where minimization is required, the negative or the inverse of the function to be optimized is used. The switching angles are determined using GA. The procedure for formulating a problem involves various steps and applying a GA are as follows: 1. Select binary or floating point strings. 2. Find the number of variables specific to the problem; this number will be the number of genes in a chromosome. The number of variables is depends upon the number of controllable switching angles which is the number of H-bridges in a cascaded multilevel inverter. For example a nine-level inverter requires four H-bridges; thus, each chromosome for this application will have four switching angles, ie, (α1, α2, α3 and α). 3. Define the population size and initialize the population. The higher population might increase the rate of convergence and it also increases the execution time. Hence the selection of an optimum-sized population requires some experience in GA. We set the population in this paper has 20 chromosomes, each containing four switching angles. During the process the population is initialized with random angles between 0 degree and 90degree taking into consideration the quarter-wave symmetry of the output voltage waveform.. The very important step for the GA to evaluate the fitness of each chromosome is the cost function. Main objective of this study is to minimize specified harmonics; therefore the cost function has to be related to these harmonics. In this paper the fifth and seventh harmonics at the output of a nine-level inverter are to be minimized. Hence the cost function (f) can be selected as the sum of these two harmonics normalized to the fundamental, V 5 + V 7 f(θ 1,θ 2,θ3,θ )= 100 ( 8) V1 For each chromosome a multilevel output voltage waveform is created using the switching angles in the chromosome and the required harmonic magnitudes are calculated using FFT techniques. The fitness value (FV) is calculated for each chromosome inserting. In FV(θ1,θ 2,θ3,θ ) = 100 V 5 + V 7 V1 ( 9) this case, The switching angle set producing the maximum FV is the best solution of the first iteration. 5. Generally the GA is set to run for a certain number of iterations (100 in this case) to get an angle. After the first iteration, FVs are used to determine new offspring. Then followed with crossover and mutation operations and a new value of the cost function reaches below 1, in this case the sum of population is created which runs through the same cycle starting from FV evaluation. Generally, the GA can converge to a solution well before 100 iterations are completed. To save time, in this paper, the iterations have been stopped when the absolute the fifth and the seventh harmonics is negligible compared to the fundamental. After completion of iterations, the GA finds one solution; therefore, it has to be run as many times as the number of solutions required to cover the whole modulation index range. The algorithm to find the optimum switching angles is described through the flow chart shown in Figure.. Figure Flowchart of Genetic Algorithm. Comparison of switches used and THDs in the phase voltage of both the system is summarized in table 2. Table 2. Comparison of switches used and THDs TYPE OF MULTILEVEL INVERTER CASCADED H BRIDGE CASCADED BRIDGE (Proposed) NO OF SWITCHES USED THD Phase (%) 16 10.27 10 9.03 % REDUCTION 37.50% 12.07%. Simulation Results The feasibility of the proposed approach is verified using computer simulations. A model of the nine level inverter is constructed in MATLAB-Simulink software. A new strategy with reduced number of switches is 760
employed. For cascaded H bridge nine level inverter requires 16 switches to get nine level output voltage and with the proposed topology requires 10 switches. The new topology has the advantage of its reduced number of devices compared to conventional cascaded H-bridge multilevel inverter. The schematic diagram of cascaded H bridge nine level inverter and proposed new nine level topology built in MATLAB-Simulink is illustrated in Fig. 5 and Fig. 6 respectively. Figure 7. Output voltage waveform of nine level inverter The output current waveform of nine level inverter on resistive load is shown in Figure 8. Figure 5. Simulation diagram for cascaded H bridge nine level cascaded inverter Figure 8. Output current waveform (Resistive Load) The output current waveform of nine level inverter on inductive load is shown in Figure 9. Figure 6. Simulation diagram for proposed nine level cascaded inverter The nine level inverter is simulated with the implementation of switch reduction scheme. The input voltage is given as 2V DC supply to the inverter and R and RL load. The output voltage waveform of nine level inverter is shown in Figure 7. Figure 9. Output current waveform (inductive load) The gate pulses generated from the control circuit for the switching devices shown in Figure 10. 5. Experimental Results Fig. 12 shows an experimental prototype of a single phase Nine level cascaded inverter. The maximum rating of this inverter is 500 VA. The MOSFET drivers and isolation circuits are placed on each module itself. PIC 16F887A microcontroller has been chosen to control the switching signals. This microcontroller is programmed using the open-source software MPLAB_v810 761
Figure 10. Gate pulse of switching devices The frequency spectrum of output voltage is shown in Figure 11. Figure 13. output voltage waveform of nine level cascaded multilevel inverter 6. Conclusion The proposed topology has the advantage of its reduced number switches and harmonics are reduced with THD value of 9.03 at 96V is achieved. For proposed harmonic spectrum of the simulation system is as shown in the fig.11, which shows the results are well within the specified limits of IEEE standards. The results of both output voltage and FFT analysis are verified by simulating the main circuit using MATLAB. References [1] John N. Chiasson, Leon M. Tolbert, Keith J. McKenzie, Zhong Du, A Complete solution to the harmonic elimination problem, IEEE transactions on power electronics, Vol. 19, No.2, pp. 91-98, 91 March 200. Figure 11. FFT analysis [2] Jose Rodriguez, Jin-Sheng Sheng Lai and Fang Zheng, Multilevel Inverters: A survey of topologies, Control applications, IEEE transactions on Industrial [3] V. G. Agelidis and M. Calais, Application specific harmonic performance evaluation of multicarrier PWM techniques, in proc. p IEEE PESC 98, vol. 1, 1998, pp. 172 178. Figure 12. Experimental prototype nine level cascaded inverter. The output voltage waveform of nine level cascaded multilevel inverter is shown in Figure 13. 762 [] Y.Sahali, and M. K. Fellah, "Optimal Minimization of the Total Harmonic Distortion (OMTHD) Technique For The Symmetrical Multilevel Inverters Control"1st national conference on electrical engineering and its applications (CNEA0), Sidi-belSidi Abbes, May 2-25-200. [5] Y.Sahali, and M. K. Fellah, "Application of the Optimal Minimization of the Total Harmonic Distortion technique to the Multilevel Symmetrical Inverters and Study of its Performance in Comparison with the he Selective Harmonic Elimination technique" SPEEDAM 2006 International Symposium on Power
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