ANALOG CIRCUITS AND SIGNAL PROCESSING Series Editors Mohammed Ismail, The Ohio State University Mohamad Sawan, École Polytechnique de Montréal For further volumes: http://www.springer.com/series/7381
Yongjian Tang Hans Hegt Arthur van Roermund Dynamic-Mismatch Mapping for Digitally-Assisted DACs 123
Yongjian Tang MaxLinear Inc. Carlsbad, CA, USA Arthur van Roermund Department of Electrical Engineering Eindhoven University of Technology Eindhoven, The Netherlands Hans Hegt Department of Electrical Engineering Eindhoven University of Technology Eindhoven, The Netherlands ISBN 978-1-4614-1249-6 ISBN 978-1-4614-1250-2 (ebook) DOI 10.1007/978-1-4614-1250-2 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2012956311 Springer Science+Business Media New York 2013 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Contents 1 Introduction... 1 2 Digital-to-Analog Converters... 5 2.1 Introduction to DACs... 5 2.1.1 Time Domain Response... 5 2.1.2 Frequency Domain Response... 7 2.1.3 Applications... 8 2.2 Performance Specifications... 8 2.2.1 Static Performance (DC) Specifications... 8 2.2.2 Dynamic Performance (AC) Specifications... 10 2.3 Architectures... 12 2.3.1 Binary Architecture... 12 2.3.2 Thermometer (Unary) Architecture... 13 2.3.3 Segmented Architecture... 14 2.4 Physical Implementations... 14 2.4.1 Resistor DAC... 14 2.4.2 Capacitor DAC... 15 2.4.3 Current-Steering DAC (CS-DAC)... 16 2.5 State of The Art... 17 2.6 Conclusions... 21 3 Modeling and Analysis of Performance Limitations in CS-DACs... 23 3.1 Static Mismatch Error... 23 3.1.1 Error Source: Amplitude Error... 24 3.1.2 Effect on Static Performance... 26 3.1.3 Effect on Dynamic Performance... 26 3.2 Dynamic Mismatch Error... 32 3.2.1 Error Sources: Amplitude and Timing Errors... 32 3.2.2 Dynamic Mismatch in Frequency Domain... 45 3.2.3 New Parameters to Evaluate Dynamic Matching: Dynamic-DNL and Dynamic-INL... 47 3.2.4 Comparison to Traditional Static DNL & INL... 50 v
vi Contents 3.3 Non-mismatch Error... 51 3.3.1 Sampling Jitter... 51 3.3.2 Common Duty-Cycle Error... 56 3.3.3 Finite Output Impedance... 61 3.3.4 Data-Dependent Switching Interference... 64 3.4 Summary of Performance Limitations... 66 3.5 Conclusions... 68 4 Design Techniques for High-Performance Intrinsic and Smart CS-DACs... 69 4.1 Introduction to Smart DACs... 69 4.2 Design Techniques for Intrinsic DACs... 71 4.2.1 Non-mismatch-Error Focused Techniques... 71 4.2.2 Mismatch-Error Focused Techniques... 77 4.3 Design Techniques for Smart DACs... 79 4.3.1 Analog Calibration Techniques... 80 4.3.2 Digital Calibration Techniques... 81 4.4 Summary of Design Techniques for Intrinsic and Smart DACs... 86 4.5 Conclusions... 89 5 A Novel Digital Calibration Technique: Dynamic-Mismatch Mapping (DMM)... 91 5.1 Theory of Dynamic-Mismatch Mapping... 91 5.2 Measurement of Dynamic-Mismatch Error... 95 5.2.1 Measurement Flow... 95 5.2.2 Sine-Wave Demodulation vs. Square-Wave Demodulation... 100 5.2.3 Weight Function Between Amplitude and Timing Errors... 103 5.3 Theoretical Evaluation of DMM... 105 5.3.1 Effect of f m on Performance Improvement... 105 5.3.2 Robustness of DMM... 113 5.3.3 Application of DMM and Comparison to Other Techniques... 113 5.4 Conclusions... 116 6 An On-chip Dynamic-Mismatch Sensor Based on a Zero-IF Receiver 119 6.1 Architecture Considerations... 119 6.2 Analog Front-End Design... 121 6.2.1 Circuit Design... 121 6.2.2 Signal Transfer Function... 125 6.2.3 Noise Analysis... 128 6.3 ADC Design... 134 6.4 Overall Performance... 134 6.5 Conclusions... 135
Contents vii 7 Design Example... 137 7.1 Overview... 137 7.2 A 14-bit 650 MS/s Intrinsic DAC Core... 138 7.2.1 Circuit Design... 138 7.2.2 Experimental Results... 140 7.2.3 Comparison to Other Works... 142 7.3 A 14-bit 200 MS/s Smart DAC with DMM... 143 7.3.1 Circuit Design... 143 7.3.2 Experimental Results... 145 7.3.3 Benchmark... 149 7.4 Conclusions... 155 8 Conclusions... 157 References... 159 Index... 163
Symbols and Abbreviations Symbol Description Unit ADC Analog-to-digital converter CML Current-mode logic D com Common duty-cycle error seconds DAC Digital-to-analog converter DEM Dynamic element matching DMM Dynamic-mismatch mapping DNL Differential non-linearity LSB Dynamic-DNL Dynamic differential non-linearity LSB Dynamic-INL Dynamic integral non-linearity LSB DSP Digital signal processor ENOB Effective number of bits bit f i Input signal frequency Hz f m Modulation or measurement frequency Hz f s Sampling frequency Hz IM3 Third-order intermodulation dbc IMD Intermodulation distortion dbc INL Integral non-linearity LSB LO Local oscillator LVDS Low-voltage differential signaling NRZ Non-return-to-zero NSD Noise power spectral density dbm/hz OTA Operational transconductance amplifier RZ Return-to-zero SFDR Spurious-free dynamic range db SMM Static-mismatch mapping SNR Signal-to-noise ratio db SNDR Signal-to-(noise+distorion) ratio db TIA Trans-impedance amplifier THD Total harmonic distortion dbc ix
x Symbols and Abbreviations Symbol Description Unit T s Sampling period seconds ZOH Zero-order-hold Z out Output impedance amp Deviation of Gaussian distributed amplitude errors % timing Deviation of Gaussian distributed timing errors seconds jitter Deviation of Gaussian distributed jitter seconds