Computer-Based Project in VLSI Design Co 3/7

Computer-Based Project in VLSI Design Co 3/7 As outlined in an earlier section, the target design represents a Manchester encoder/decoder. It comprises the following elements: A ring oscillator module, which provides a master clock. An transmitter module. This element comprises a circuit which generates Manchester-coded data. A fuller description of Manchester code is given below. A receiver module, which decodes incoming Manchester-coded data. A 4-bit counter is required to generate additional clock waveforms to drive the coder and decoder modules. A single 2-input NOR gate is provided for introductory experiments. Each of these elements is dealt with in its own section below. The first stage of development involves creating a representation of the entire system using a hardware description language (HDL) to explore and verify its operation. It is helpful to present a block diagram showing the organisation of the listed elements. This is shown in Figure 1. Transmitter Counter Ring ill Receiver Figure 1 Block Diagram of complete ring design D M Holburn Mar 2004 C.4.2 29 C7ring.doc

Ring Oscillator A key element of this project is the ring oscillator, ringarray, whose development is intended to highlight all the various activities involved in integrated circuit design. During the project you will construct a definition in a hardware description language for it. You will develop a schematic representation of its constituent gates and a graphical symbol; you will have a chance to predict its performance using digital and analogue simulation techniques. You will design and verify the mask layout for the 2 input NOR gate used in its construction, and finally, you will use the ringarray module as the signal source in an encoder-decoder design which includes counters and other sequential logic devices. The following section describes the specification to which we shall work for the ringarray part of the design. Ring Oscillator Specification The simple theory of the ring oscillator is given in the Design of Logic Gates in CMOS pamphlet, and the relation between gate delay and oscillation frequency is derived. The initial design for ringarray will use the NOR2 part whose detailed specification is provided by Mietec; the salient details are given overleaf. We shall aim to produce a ring oscillator with a single Enable input ENB, and two outputs OUT1 and OUT2 taken direct from the ringarray module, with a stated oscillation frequency and phase difference between them. In order to specify the basic characteristics of the ring oscillator portion of the design, we shall use the criteria detailed opposite. A single instantiation of the NOR2 gate is also shown in the block diagram in Figure 1. This gate is entirely separate from the ring oscillator and all other parts of the design. It is included to provide a straightforward means of introducing some of the major concepts related to schematic design and simulation. Later on we shall develop our own NOR2 gate at the most detailed level possible, using individual MOS transistors. The result will be a gate which is broadly similar to the Mietec part, but whose delay characteristics will likely be quite different. With a little reflection and research, and with modest effort you should be able to design a part which works significantly faster than the original library part, and you should be able to identify ways of making the design more compact (and hence cheaper). D M Holburn Mar 2004 C.4.2 30 C7ring.doc

Ring Oscillator Specification Worst-case operating frequency ~6 MHz, based on Mietec NOR2 part with V dd = 5 volts and nominal loading capacitances (see overleaf for specification). Input ENB = 1 Input ENB = 0 Oscillator disabled Oscillator enabled Typical input/output waveforms Worst-case timing specifications (see waveforms) Parameter Description Lower limit (ns) Upper limit (ns) T Oscillation period 145 185 t1 Delay from ENB to OUT1 17 21 t2 Delay from OUT1 to OUT2 40 60 D M Holburn Mar 2004 C.4.2 31 C7ring.doc

D M Holburn Mar 2004 C.4.2 32 C7ring.doc

ELECTRICAL CHARACTERISTICS CAPACITANCES INPUT CAPACITANCE UNIT A,B 0.104 pf TYPICAL PROPAGATION DELAYS (T = 27 Celsius, Vdd = 5V, Cload = 0.2 pf) OUTPUT INTRINSIC DELAY UNIT A,B to Y Rising 2.7 ns Falling 2.8 ns D M Holburn Mar 2004 C.4.2 33 C7ring.doc

Digital sub-systems In addition to the ring oscillator core we need to develop various additional digital sub-systems to support the Manchester transmitter/receiver. As for the ring oscillator, we shall initially investigate and verify the design using HDL. We shall then consider implementation. Unlike the ring oscillator, which we shall design and model at the most detailed level possible (creating it from individual MOS transistors), the Manchester transmitter/receiver design will take advantage of pre-defined library components. These will include: A digital counter constructed from components taken from the Mietec library (combinational gates and D-type bistables). The counter s Clock input is driven by one of the ring oscillator outputs, and the outputs are used to supply clock waveforms needed in other parts of the design. This will emphasise the value of the hierarchical approach to design. The Manchester transmitter, which itself can be divided into two parts: a sequence generator, and an encoder to convert its output to Manchester format. The sequence generator produces a convenient predictable digital waveform to drive the Manchester encoder. It comprises a shift register, synthesised from library components, with feedback from two of the shift register outputs (to be determined), using an EXOR gate, forming the Data input to the register. This arrangement is known as Modulo-2 feedback, and this arrangement produces a characteristic periodic waveform with useful properties. The circuit is often referred to as a Pseudo-Random Binary Sequence Generator. The shift register receives a clock signal from one of the counter outputs. No schematic is provided for this part of the circuit, and you are recommended to research this part of the design in one of the standard works for example, The Art of Electronics, by Horowitz and Hill. This configuration will provide ample opportunity for you to investigate the facilities provided in the simulation tools for predicting the behaviour of digital designs. The Manchester encoder design. Manchester code is described in more detail below, and a schematic for the encoder appears at the end of this chapter. The encoder comprises only one EXOR gate. It receives the data signal from the sequence generator and a clock SR_CLK from the counter, and produces at its output an encoded waveform in Manchester format. This signal could be applied to a cable for transmission over a considerable distance to a remote receiver (or decoder); only one conductor (plus earth return), or a single-channel wireless or optical link would be required for this. The Manchester transmitter we shall develop will lie adjacent to the receiver, and for our test purposes it will receive the signal generated by the local transmitter, rather than a remote one. This simplified arrangement reduces complexity without significantly detracting from the value of the exercise. The receiver is the most complicated part of the circuit and a detailed explanation of its operation and a representative schematic are given later in this chapter. D M Holburn Mar 2004 C.4.2 34 C7ring.doc

Manchester Encoding and Decoding Manchester encoding is a synchronous clock encoding technique used by the OSI physical layer to encode the clock and data of a synchronous bit stream. In this technique, the actual binary data bits to be transmitted over the cable are not simply sent as a sequence of straight binary 1s and 0s (such a sequence is known technically as Non Return to Zero (NRZ)). Instead, the bits are translated into a slightly different format that has a number of advantages over using straight binary encoding (NRZ). Manchester encoding follows the rules shown below: Original Data Logic 0 Logic 1 Value Sent 0 to 1 (upward transition at bit centre) 1 to 0 (downward transition at bit centre) The following diagram shows a typical Manchester encoded signal with the corresponding binary representation of the data (1,1,0,1,0,0) being sent. Waveform for a Manchester-encoded bit stream carrying the sequence: 110100. In the Manchester encoding shown, a logic 0 is indicated by a 0 to 1 transition at the centre of the bit and a logic 1 is indicated by a 1 to 0 transition at the centre of the bit. Note that signal transitions (1 to 0 or 0 to 1) do not always occur at the 'bit boundaries' (the division between one bit and another), but that there is always a transition at the centre of each bit. The encoding may be alternatively viewed as a phase encoding where each bit is encoded by a positive 90 degree phase transition, or a negative 90 degree phase transition. Manchester code is sometimes known as a Biphase Code. A major advantage of a Manchester-encoded data stream is that it contains frequent level transitions which allow the receiver to extract the clock signal relatively easily - for example, using a Digital Phase Locked Loop (DPLL) - and correctly decode the value and timing of each bit. For reliable operation using a DPLL, the transmitted bit stream must contain a high density of bit transitions. Manchester encoding ensures this, allowing the receiving DPLL to correctly extract the clock signal, even in the presence of significant distortion in the transmission channel. The penalty for introducing frequent transitions is that the Manchester coded signal consumes more bandwidth than the original NRZ signal. There are other, more complex methods of coding that do not exhibit this inherent inefficiency. However, they call for more complex decoder designs. In many cases (for example, in Ethernet LAN systems), the additional bandwidth is not a significant issue. Example of Manchester Encoding The pattern of bits "0 1 1 1 1 0 0 1" encodes to "01 10 10 10 10 01 01 10". Another more curious example is the pattern "1 0 1 0 1 etc" which encodes to "10 01 10 01 10" which could also be viewed as "1 00 11 00 11 0" (note that the spacing D M Holburn Mar 2004 C.4.2 35 C7ring.doc

used here is just for clarity the bits are generated at regular intervals). Thus for a 10 Mbps Ethernet LAN, which uses such a pattern as a preamble sequence in advance of the data proper, the pattern encodes to a 5 MHz square wave! (i.e., one half cycle in each 0.1 microsecond bit period.) The Manchester Decoder The circuit below is widely used to decode Manchester-encoded data, and is the one used in our receiver design. It comprises six clocked bistable devices, and a handful of combinational gates. The inputs are: Manchester-coded data, and a clock which should have a frequency between 5 and 12 times the incoming data rate, although it need not be synchronised to the remote transmitter clock. In Manchester code, a logic 0 is encoded as a Low-to-High transition and a logic 1 is encoded as a High-to-Low transition. Between two identical bits of data there is thus an extra level transition, which must be ignored by the decoder. In order to do this, the decoder needs to extract information about the bit timing. This is achieved as follows. The decoder is supplied with a clock REC_CLOCK with timing that is several times higher than the encoding clock. This allows the incoming data DATA_IN to be sampled several times during the encoding period. In this design, a decode clock is specified at nominally eight times the incoming data rate, although this is not critical. After detecting a valid transition, the circuit ignores further transitions for six clock periods. This guarantees that the extra transition referred to will be ignored. Also, the design will tolerate substantial frequency errors between encoder and decoder. The signal RESET_decoder is provided to put the decoder into a known state before it starts operating. Q0 and Q1 are XORed by gate EXOR to detect any incoming level change. Q2, Q3 and Q4 form a divide-by-six Johnson counter that is designed to lock up when it reaches the 000 state. (It counts through the states 100, 110, 111, 011, 001 before reaching 000.) The state 010 is unused, but is detected and changed to 000 on the next clock edge. When the Johnson counter has timed out and is in the 000 state, any incoming level transition generates a pipelined STROBE signal whose presence confirms the signal RECEIVED_DATA from Q1 as valid data. This is latched in Q5 to produce the output signal DATA_OUT. On the next clock edge, the Johnson counter changes to 100, which terminates the strobe. For the following five clock periods, any incoming level changes are detected, but the XOR output is inhibited (by AND3) and is ignored. When the Johnson counter again reaches 000, it locks up and enables the STROBE signal. Any simultaneously or subsequently detected level change starts a new operation as described above. The decoder clock can be asynchronous to the incoming data, but must be faster than five times the incoming bit rate (in order to detect the next bit transition), and slower than 12 times the incoming bit rate (in order to suppress the between-bit transition). The nominal decode clock frequency should, therefore, be eight times the incoming data rate. D M Holburn Mar 2004 C.4.2 36 C7ring.doc

Manchester Decoder schematic D M Holburn Mar 2004 C.4.2 37 C7ring.doc

The Manchester Transmitter The schematic below represents both the sequence generator (shown as a rectangular block), and the encoder itself (the single exclusive-or gate EXOR). The signals SET and RESET are provided to allow the generator to be put into a standard state at the beginning of every transmission. Signal NRZ represents the unencoded non-returnto-zero data stream from the generator, and the signal MANCHESTER represents the Manchester-encoded output. D M Holburn Mar 2004 C.4.2 38 C7ring.doc