SupIBuck TM eatures Wide Input ltage ange.5 t 2 Wide Output ltage ange 0.7 t 0.9*in Cntinuus A Lad Capability Integrated Btstrap-dide High Bandwidth E/A fr excellent transient perfrmance Prgrammable Switching requency up t.2mhz Prgrammable Over Current Prtectin PGd utput Hiccup Current Limit Precisin eference ltage (0.7, +/-%) Prgrammable Sft-Start Enable Input with ltage Mnitring Capability Enhanced Pre-Bias Start-up Seq input fr Tracking applicatins -40 C t 25 C perating junctin temperature Thermal Prtectin Multiple current ratings in pin cmpatible ftprint 5mm x 6mm Pwer QN Package, 0.9 mm height Lead-free, halgen-free and HS cmpliant Applicatins Server Applicatins Strage Applicatins Embedded Telecm Systems Distributed Pint f Lad Pwer Architectures Descriptin HIGHLY EICIENT INTEGATED A SYNCHONOUS BUCK EGULATO.5 <in<6 The I84A SupIBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC synchrnus Buck regulatr. The MOSETs cpackaged with the n-chip PWM cntrller make I84A a space-efficient slutin, prviding accurate pwer delivery fr lw utput vltage applicatins. I84A is a versatile regulatr which ffers prgrammability f start up time, switching frequency and current limit while perating in wide input and utput vltage range. The switching frequency is prgrammable frm 250kHz t.2mhz fr an ptimum slutin. It als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t give required system level security in the event f fault cnditins. Netcm Applicatins Cmputing Peripheral ltage egulatrs General DC-DC Cnverters 4.5 <cc<5.5 Seq Enable in Bt cc SW PGd PGd OCSet t b SS/ SD Gnd Cmp PGnd ig.. Typical applicatin diagram
ABSOLUTE MAXIMUM ATINGS (ltages referenced t GND unless therwise specified) in. -0. t 25 cc...... -0. t 8 (Nte2) Bt.... -0. t SW.. -0. t 25(DC), -4 t 25(AC, 00ns) Bt t SW....... -0. t cc+0. (Nte) OCSet.. -0. t 0, 0mA Input / utput Pins..... -0. t cc+0. (Nte) PGND t GND..... -0. t +0. Strage Temperature ange... -55 C T 50 C Junctin Temperature ange... -40 C T 50 C (Nte2) ESD Classificatin JEDEC Class C Misture sensitivity level... JEDEC Level 2@260 C (Nte5) Nte: Must nt exceed 8 Nte2: cc must nt exceed 7.5 fr Junctin Temperature between -0 C and -40 C Stresses beynd thse listed under Abslute Maximum atings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins are nt implied. PACKAGE INOMATION 5mm x 6mm POWE QN SW IN 2 0 PGnd θ θ JA J-PCB 5 C / W 2 C / W Bt Enable 4 5 Gnd 9 8 CC PGd 2 4 5 6 7 ODEING INOMATION Seq B COMP Gnd t SS OCSet PACKAGE DESIGNATO PACKAGE DESCIPTION PIN COUNT PATS PE EEL M I84AMTPb 5 4000 M I84AMTPb 5 750 2
Blck Diagram ig. 2. Simplified blck diagram f the I84A
Pin Descriptin Pin Name Descriptin Seq 2 b Cmp Sequence pin. Use tw external resistrs t set Simultaneus Pwer up sequencing. If this pin is nt used cnnect t cc. Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier. Output f errr amplifier. An external resistr and capacitr netwrk is typically cnnected frm this pin t b pin t prvide lp cmpensatin. 4 Gnd Signal grund fr internal reference and cntrl circuitry. 5 t 6 SS/SD 7 OCSet 8 PGd 9 CC 0 PGnd Set the switching frequency. Cnnect an external resistr frm this pin t Gnd t set the switching frequency. Sft start / shutdwn. This pin prvides user prgrammable sft-start functin. Cnnect an external capacitr frm this pin t Gnd t set the start up time f the utput vltage. The cnverter can be shutdwn by pulling this pin belw 0.. Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld. Pwer Gd status pin. Output is pen drain. Cnnect a pull up resistr frm this pin t cc. If unused, it can be left pen. This pin pwers the internal IC and the drivers. A minimum f u high frequency capacitr must be cnnected frm this pin t the pwer grund (PGnd). Pwer Grund. This pin serves as a separated grund fr the MOSET drivers and shuld be cnnected t the system s pwer grund plane. SW Switch nde. This pin is cnnected t the utput inductr. 2 IN Input vltage cnnectin pin. Bt 4 Enable Supply vltage fr high side driver. A 0.u capacitr must be cnnected frm this pin t SW. Enable pin t turn n and ff the device. Use tw external resistrs t set the turn n threshld (see Enable sectin). Cnnect this pin t cc if it is nt used. 5 Gnd Signal grund fr internal reference and cntrl circuitry. 4
ecmmended Operating Cnditins Symbl Definitin Min Max Units in Input ltage.5 2* cc Supply ltage 4.5 5.5 Bt t SW Supply ltage 4.5 5.5 Output ltage 0.7 0.9*in I Output Current 0 A s Switching requency 225 20 khz T j Junctin Temperature -40 25 C * SW must nt exceed the Abs Max ating (25) Electrical Specificatins Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Pwer Lss Parameter Symbl Test Cnditin Min TYP MAX Units Pwer Lss P lss cc5, in 2,.8, I A, s600khz, L2.2uH, Nte4 0.682 W MOSET ds(n) Tp Switch ds(n)_tp Bt - sw 5, IDA, Tj25 C 24.5 2 Bttm Switch ds(n)_bt cc5, IDA, Tj25 C 24.5 2 mω eference ltage eedback ltage B 0.7 Accuracy Supply Current 0 C<Tj<25 C -.0 +.0-40 C<Tj<25 C, Nte -2.0 +2.0 % CC Supply Current (Standby) I CC(Standby) SS0, N Switching, Enable lw 500 μa cc Supply Current (Dyn) I CC(Dyn) SS, cc5, s500khz Enable high Under ltage Lckut 0 ma CC -Start-Threshld CC _ULO_Start cc ising Trip Level.95 4.5 4.5 CC -Stp-Threshld CC _ULO_Stp cc alling Trip Level.65.85 4.05 Enable-Start-Threshld Enable_ULO_Start Supply ramping up.4.2.6 Enable-Stp-Threshld Enable_ULO_Stp Supply ramping dwn 0.9.0.06 Enable leakage current Ien Enable. 5 μa 5
Electrical Specificatins (cntinued) Unless therwise specified, these specificatins apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Parameter Symbl Test Cnditin Min TYP MAX Units Oscillatr t ltage 0.665 0.7 0.75 requency S t59k 225 250 275 t28.7k 450 500 550 khz t.5k, Nte4 080 200 20 amp Amplitude ramp Nte4.8 p-p amp Offset amp (s) Nte4 0.6 Min Pulse Width Dmin(ctrl) Nte4 00 ixed Off Time Nte4 0 200 ns Max Duty Cycle Dmax s250khz 92 % Errr Amplifier Input Offset ltage s fb-seq, -0 0 +0 m seq0.8 Input Bias Current Ib(E/A) - + μa Input Bias Current Ip(E/A) - + Sink Current Isink(E/A) 0.40 0.85.2 Surce Current Isurce(E/A) 8 0 ma Slew ate S Nte4 7 2 20 /μs Gain-Bandwidth Prduct GBWP Nte4 20 0 40 MHz DC Gain Gain Nte4 00 0 20 db Maximum ltage max(e/a) cc4.5.4.5.75 Minimum ltage min(e/a) 20 220 m Cmmn Mde ltage Nte4 0 Sft Start/SD Sft Start Current ISS Surce 4 20 26 μa Sft Start Clamp ltage ss(clamp) 2.7.0. Shutdwn Output Threshld SD 0. Over Current Prtectin OCSET Current IOCSET s250khz 20.8 2.6 26.4 s500khz 4 48.8 54.6 s200khz, Nte4 2.7 μa OC Cmp Offset ltage OSET Nte4-0 0 +0 m SS ff time SS_Hiccup 4096 Cycles Btstrap Dide rward ltage I(Bt)0mA 80 260 470 m Deadband Deadband time Nte4 5 0 0 ns 6
Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Parameter SYM Test Cnditin Min TYP MAX Units Thermal Shutdwn Thermal Shutdwn Nte4 40 C Hysteresis Nte4 20 Pwer Gd Pwer Gd upper PG(upper) b ising 0.77 0.805 0.840 Threshld Upper Threshld PG(upper)_Dly b ising 256/s s Delay Pwer Gd lwer PG(lwer) b alling 0.560 0.595 0.60 Threshld Lwer Threshld PG(lwer)_Dly b alling 256/s s Delay Delay Cmparatr PG(Delay) elative t charge vltage, SS rising 2 2. 2. Threshld Delay Cmparatr Delay(hys) Nte4 260 00 40 m Hysteresis PGd ltage Lw PG(vltage) I PGd -5mA 0.5 Leakage Current I leakage 0 0 μa Switch Nde SW Bias Current Isw SW0, Enable0 SW0,Enablehigh,SS,seq0, Nte4 6 μa Nte: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte4: Guaranteed by Design but nt tested in prductin. Nte5: Upgrade t industrial/msl2 level applies frm date cdes 227 (marking explained n applicatin nte AN2 page 2). Prducts with prir date cde f 227 are qualified with MSL fr Cnsumer market. 7
[ma] 9.5 9.4 9. 9.2 9. 9.0 8.9 8.8 8.7 8.6 TYPICAL OPEATING CHAACTEISTICS (-40 C - 25 C) s 500 khz [ua] [khz] 290 270 250 20 20 90 70 50 550 540 50 520 50 500 490 480 470 460 Icc(Standby) -40-20 0 20 40 60 80 00 20 Temp[ C] EQUENCY 450-40 -20 0 20 40 60 80 00 20 Temp[ C] [ua] Icc(Dyn) 8.5-40 -20 0 20 40 60 80 00 20 54.0 5.0 52.0 5.0 50.0 49.0 48.0 47.0 46.0 45.0 44.0 Temp[ C] IOCSET(500kHz) 4.0-40 -20 0 20 40 60 80 00 20 Temp[ C] 4.46 cc(ulo) Start 4.6 cc(ulo) Stp 4.4 4. 4.6 4.06 4. 4.0 [] 4.26 [].96 4.2.9 4.6.86 4..8 4.06-40 -20 0 20 40 60 80 00 20.76-40 -20 0 20 40 60 80 00 20 Temp[ C] Temp[ C] [] Enable(ULO) Start.6.4.2.0.28.26.24.22.20.8.6.4-40 -20 0 20 40 60 80 00 20 Temp[ C] [] Enable(ULO) Stp.06.04.02.00 0.98 0.96 0.94 0.92 0.90-40 -20 0 20 40 60 80 00 20 Temp[ ο C] 26.0 ISS fb [ua] 24.0 22.0 20.0 8.0 [m] 7 706 70 696 6.0 69 4.0-40 -20 0 20 40 60 80 00 20 Temp[ C] 686-40 -20 0 20 40 60 80 00 20 Temp[ C] 8
dsn f MOSETs Over Temperature at cc5 Nte: Ctrl-ET and Sync-ET are identical. 6 4 2 esistance [mω] 0 28 26 24 22 20-40 -20 0 20 40 60 80 00 20 40 Temperature [ C] Ctrl-ET/Sync-ET 9
Typical Efficiency and Pwer Lss Curves in2, cc5, I0.A-A, s 600kHz, m Temperature, N Air lw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. ut () L (uh) P/N DC (mω) 0.9.5 PCMB065T-5MS 6.7.5 PCMB065T-5MS 6.7..5 PCMB065T-5MS 6.7.2.5 PCMB065T-5MS 6.7.5 2.2 IHLP2525EZ-0 2.2uH.8 2.2 IHLP2525EZ-0 2.2uH 2.5. IHLP2525EZ-0.uH 9.9.. IHLP2525EZ-0.uH 9.9 5 4.7 IHLP2525EZ-0 4.7uH 28.9 96 94 92 90 Efficiency (%) 88 86 84 82 80 78 76 74 0. 0.6 0.9.2.5.8 2. 2.4 2.7 Iut (A) 0.9..2.5.8 2.5. 5 Pwer Lss (W) 0.9 0.8 0.7 0.6 0.5 0.4 0. 0.2 0. 0 0. 0.6 0.9.2.5.8 2. 2.4 2.7 Iut (A) 0.9..2.5.8 2.5. 5 0
Typical Efficiency and Pwer Lss Curves in5, cc5, I0.A-A, s 600kHz, m Temperature, N Air lw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. ut () L (uh) P/N DC (mω) 0.7 0.82 IHLP2525EZ-0 2.2uH 4.6 0.75 0.82 IHLP2525EZ-0 2.2uH 4.6 0.9 PCMB065T-0MS 5.6.5 PCMB065T-5MS 6.7..5 PCMB065T-5MS 6.7.2.5 PCMB065T-5MS 6.7.5.5 PCMB065T-5MS 6.7.8.5 PCMB065T-5MS 6.7 2.5.5 PCMB065T-5MS 6.7..5 PCMB065T-5MS 6.7 Efficiency (%) 98 96 94 92 90 88 86 84 82 80 78 76 74 72 70 0. 0.6 0.9.2.5.8 2. 2.4 2.7 Iut (A) 0.7 0.75 0.9..2.5.8 2.5. Pwer Lss (W) 0.55 0.5 0.45 0.4 0.5 0. 0.25 0.2 0.5 0. 0.05 0. 0.6 0.9.2.5.8 2. 2.4 2.7 Iut (A) 0.7 0.75 0.9..2.5.8 2.5.
Circuit Descriptin THEOY O OPEATION Intrductin The I84A uses a PWM vltage mde cntrl scheme with external cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency is prgrammable frm 250kHz t.2mhz and prvides the capability f ptimizing the design in terms f size and perfrmance. I84A prvides precisely regulated utput vltage prgrammed via tw external resistrs frm 0.7 t 0.9*in. The I84A perates with an external bias supply frm 4.5 t 5.5, allwing an extended perating input vltage range frm.5 t 2. If the input t the Enable pin is derived frm the bus vltage by a suitably prgrammed resistive divider, it can be ensured that the I84A des nt turn n until the bus vltage reaches the desired level. Only after the bus vltage reaches r exceeds this level will the vltage at Enable pin exceed its threshld, thus enabling the I84A. Therefre, in additin t being a lgic input pin t enable the I84A, the Enable feature, with its precise threshld, als allws the user t implement an Under-ltage Lckut fr the bus vltage in. This is desirable particularly fr high utput vltage applicatins, where we might want the I84A t be disabled at least until in exceeds the desired utput vltage level. The device utilizes the n-resistance f the lw side MOSET as current sense element, this methd enhances the cnverter s efficiency and reduces cst by eliminating the need fr external current sense resistr. I84A includes tw lw ds(n) MOSETs using I s HEXET technlgy. These are specifically designed fr high efficiency applicatins. Under-ltage Lckut and PO The under-vltage lckut circuit mnitrs the input supply cc and the Enable input. It assures that the MOSET driver utputs remain in the ff state whenever either f these tw signals drp belw the set threshlds. Nrmal peratin resumes nce cc and Enable rise abve their threshlds. The PO (Pwer On eady) signal is generated when all these signals reach the valid lgic level (see system blck diagram). When the PO is asserted the sft start sequence starts (see sft start sectin). ig. a. Nrmal Start up, Device turns n when the Bus vltage reaches 0.2 igure b. shws the recmmended start-up sequence fr the nn-sequenced peratin f I84A. Enable The Enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by Under-ltage Lckut (ULO) circuit. Therefre, the I84A will turn n nly when the vltage at the Enable pin exceeds this threshld, typically,.2. ig. b. ecmmended startup sequence, Nn-Sequenced peratin igure c. shws the recmmended startup sequence fr sequenced peratin f I84A 2
ig. 5. Pre-Bias startup pulses ig. c. ecmmended startup sequence, Sequenced peratin Pre-Bias Startup I84A is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSET ff until the first gate signal fr cntrl MOSET is generated. igure 4 shws a typical Pre-Bias cnditin at start up. The synchrnus MOSET always starts with a narrw pulse width and gradually increases its duty cycle with a step f 25%, 50%, 75% and 00% until it reaches the steady state value. The number f these startup pulses fr the synchrnus MOSET is internally prgrammed. igure 5 shws a series f 2, 6, 8 startup pulses. Sft-Start The I84A has a prgrammable sft-start t cntrl the utput vltage rise and t limit the current surge at the start-up. T ensure crrect start-up, the sft-start sequence initiates when the Enable and cc rise abve their ULO threshlds and generate the Pwer On eady (PO) signal. The internal current surce (typically 20uA) charges the external capacitr C ss linearly frm 0 t. igure 6 shws the wavefrms during the sft start. The start up time can be estimated by: T start (.4-0.7) * C 20μA SS - - - - - - - - - - - - - - - - - - - - () During the sft start the OCP is enabled t prtect the device fr any shrt circuit and ver current cnditin. ig. 4. Pre-Bias startup ig. 6. Theretical peratin wavefrms during sft-start
Operating requency The switching frequency can be prgrammed between 250kHz 200kHz by cnnecting an external resistr frm t pin t Gnd. Table tabulates the scillatr frequency versus t. Table. Switching requency and I OCSet vs. External esistr ( t ) t (kω) 47.5 5.7 28.7 2.7 20.5 7.8 5.8 4. 2.7.5 s (khz) 00 400 500 600 700 800 900 000 00 200 I cset (μa) 29.4 9.2 48.7 59.07 68.2 78.6 88.6 97.9 0.2 2.7 I OCSet 400 (μa)...(2) (kω) t Table. shws I OCSet at different switching frequencies. The internal current surce develps a vltage acrss OCSet. When the lw side MOSET is turned n, the inductr current flws thrugh the Q2 and results in a vltage at OCSet which is given by: OCSet ( IOCSet OCSet ) ( ) I DS(n L )...() ig. 7. Cnnectin f ver current sensing resistr Shutdwn The I84A can be shutdwn by pulling the Enable pin belw its threshld. This will tristate bth, the high side driver as well as the lw side driver. Alternatively, the utput can be shutdwn by pulling the sft-start pin belw 0.. Nrmal peratin is resumed by cycling the vltage at the Sft Start pin. Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the DS(n) f lw side MOSET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr ( OCSet ) is cnnected between OCSet pin and the switch nde (SW) which sets the current limit set pint. An internal current surce surces current (I OCSet ) ut f the OCSet pin. This current is a functin f the switching frequency and hence, f t. An ver current is detected if the OCSet pin ges belw grund. Hence, at the current limit threshld, OCset 0. Then, fr a current limit setting I Limit, OCSet is calculated as fllws: OCSet DS( n) * I OCSet I Limit......(4) An vercurrent detectin trips the OCP cmparatr, latches OCP signal and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by shrting the sft-start capacitr t grund and cunting the number f switching cycles. The Sft Start pin is held lw until 4096 cycles have been cmpleted. The OCP signal resets and the cnverter recvers. After every sft start cycle, the cnverter stays in this mde until the verlad r shrt circuit is remved. The OCP circuit starts sampling current typically 60 ns after the lw gate drive rises t abut. This delay functins t filter ut switching nise. 4
Thermal Shutdwn Temperature sensing is prvided inside I84A. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSETs and discharges the sft start capacitr. Autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld..5 <in<6 4.5 <cc<5.5 PGd Enable cc PGd Seq t SS/ SD Gnd in Bt SW OCSet b Cmp PGnd A B (master) Output ltage Sequencing The I84A can accmmdate user prgrammable sequencing using Seq, Enable and Pwer Gd pins..5 <in<6 4.5 <cc<5.5 Enable in Bt (master) cc SW (slave) PGd 2 E PGd Seq t OCSet b C D SS/ SD Gnd Cmp PGnd Simultaneus Pwerup ig. 8a. Simultaneus Pwer-up f the slave with respect t the master. Thrugh these pins, vltage sequencing such as simultaneus and sequential can be implemented. igure 8. shws simultaneus sequencing cnfiguratins. In simultaneus pwer-up, the vltage at the Seq pin f the slave reaches 0.7 befre the b pin f the master. r E / C / D, therefre, the utput vltage f the slave fllws that f the master until the vltage at the Seq pin f the slave reaches 0.7. After the vltage at the Seq pin f the slave exceeds 0.85, the internal 0.7 reference f the slave dictates its utput vltage. It is recmmended that irrespective f the sequencing cnfiguratin used, the input vltage shuld be allwed t cme up t its nminal value first, fllwed by cc and Enable, befre the sequencing signal is applied. r nn-sequenced peratin, the Seq pin shuld be tied t a vltage greater than 0.85, such as. r cc. Again, the input vltage shuld be allwed t cme up befre cc and Enable. ig. 8b. Applicatin Circuit fr Simultaneus Sequencing Pwer Gd Output The IC cntinually mnitrs the utput vltage via eedback (b pin). The feedback vltage frms an input t a windw cmparatr whse upper and lwer threshlds are 0.805 and 0.595 respectively. Hence, the Pwer Gd signal is flagged when the b pin vltage is within the PGd windw, i. e., between 0.595 t 0.805, as shwn in ig.9 The PGd pin is pen drain and it needs t be externally pulled high. High state indicates that utput is in regulatin. ig. 9a shws the PGd timing diagram fr nntracking peratin. In this case, during startup, PGd ges high after the SS vltage reaches 2. if the b vltage is within the PGd cmparatr windw. ig. 9a. and ig 9.b. als shw a 256 cycle delay between the b vltage entering within the threshlds defined by the PGd windw and PGd ging high. 5
TIMING DIAGAM O PGOOD UNCTION ig.9a I84A Nn-Tracking Operatin (Seqcc) ig.9b I84A Tracking Operatin 6
Minimum n time Cnsideratins The minimum ON time is the shrtest amunt f time fr which the Cntrl ET may be reliably turned n, and this depends n the internal timing delays. r the I84A, the typical minimum n-time is specified as 00 ns. Any design r applicatin using the I84A must ensure peratin with a pulse width that is higher than this minimum n-time and preferably higher than 50 ns. This is necessary fr the circuit t perate withut jitter and pulseskipping, which can cause high inductr current ripple and high utput vltage ripple. In any applicatin that uses the I84A, the fllwing cnditin must be satisfied: t t n n(min) t n(min) in D s in t s n ut The minimum utput vltage is limited by the reference vltage and hence ut(min) 0.7. Therefre, fr ut(min) 0.7, s ut in t ut s n(min) Maximum Duty ati Cnsideratins A fixed ff-time f 200 ns maximum is specified fr the I84A. This prvides an upper limit n the perating duty rati at any given switching frequency. It is clear that, higher the switching frequency, the lwer is the maximum duty rati at which the I84A can perate. T allw a margin f 50ns, the maximum perating duty rati in any applicatin using the I84A shuld still accmmdate abut 250 ns ff-time. ig 0. shws a plt f the maximum duty rati v/s the switching frequency, with 250 ns ff-time. Max Duty Cycle (%) 95 90 85 80 75 70 00 400 500 600 700 800 900 000 00 200 Switching requency (khz) ig. 0. Maximum duty cycle v/s switching frequency. in in s t s ut(min) n(min) 0.7 50 ns 4. 67 0 6 /s Therefre, even at the minimum switching frequency 250 khz, n input vltage higher than 8.5 may be reliably cnverted dwn t 0.7 withut excessive jitter r pulse skipping ver the cmplete lad range. In general, practical cnsideratins dictate that any applicatin that demands a pulse width smaller than 75ns may nt exhibit jitter free peratin ver the entire lad range. 7
Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr I84A. The applicatin circuit is shwn n page 2. Enabling the I84A As explained earlier, the precise threshld f the Enable lends itself well t implementatin f a ULO fr the Bus ltage. r a typical Enable threshld f EN.2 r a in (min) 0.2, 49.9K and 2 7.5K is a gd chice. Prgramming the frequency r s 600 khz, select t 2.7 kω, using Table.. Output ltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The b pin is the inverting input f the errr amplifier, which is internally referenced t 0.7. The divider is ratied t prvide 0.7 at the b pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: I in Δ s 2 (.2 max).8 A 54m 600kHz I84A Enable + 8 ref 9 in 2 2 in (min) * EN.2... (5) 2 + 2 EN in( min ) EN... (6).........(7) when an external resistr divider is cnnected t the utput as shwn in figure. Equatin (7) can be rewritten as: 9 8 ref ref r the calculated values f 8 and 9 see feedback cmpensatin sectin. ig.. Typical applicatin f the I84A fr prgramming the utput vltage Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. rm (), fr a desired start-up time f the cnverter, the sft start capacitr can be calculated by using: C SS Where T start is the desired start-up time (ms). r a start-up time f.5ms, the sft-start capacitr will be 0.099μ. Chse a 0.μ ceramic capacitr. Btstrap Capacitr Selectin.........(8) T drive the Cntrl ET, it is necessary t supply a gate vltage at least 4 greater than the vltage at the SW pin, which is cnnected the surce f the Cntrl ET. This is achieved by using a btstrap cnfiguratin, which cmprises the internal btstrap dide and an external btstrap capacitr (C6), as shwn in ig.2. The peratin f the circuit is as fllws: When the lwer MOSET is turned n, the capacitr nde cnnected t SW is pulled dwn t grund. The capacitr charges twards cc thrugh the internal btstrap dide, which has a frward vltage drp D. The vltage c acrss the btstrap capacitr C6 is apprximately given as c I84A I624 cc b D OUT... (0) When the upper MOSET turns n in the next cycle, the capacitr nde cnnected t SW rises t the bus vltage in. Hwever, if the value f C6 is apprpriately chsen, 8 9 ( μ) T ( ms ) 0.02857... (9) start 8
the vltage c acrss C6 remains apprximately unchanged and the vltage at the Bt pin becmes Bt in + cc D... () advisable t have x0u 25 ceramic capacitrs C26X5E06M frm TDK. In additin t these, althugh nt mandatry, a X0u, 25 SMD capacitr EE-KEP may als be used as a bulk capacitr and is recmmended if the input pwer supply is nt lcated clse t the cnverter. ig. 2. Btstrap circuit t generate c vltage A btstrap capacitr f value 0.u is suitable fr mst applicatins. r applicatins with 2 input vltage, the switch nde may ring abve the 25 abslute maximum vltage rating. T prevent this, in additin t using best layut practices, it may be necessary t prvide a 0 hm resistr in series with the bt capacitr. Input Capacitr Selectin The ripple current generated during the n time f the upper MOSET shuld be prvided by the input capacitr. The MS value f this ripple is expressed by: I MS D Where: D is the Duty Cycle I MS is the MS value f the input capacitr current. I is the utput current. r I A and D 0.5, the I MS.07A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ES and ESL at higher frequency which enables better efficiency. r this applicatin, it is I D ( D).........(2) in.........() Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value causes large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr ( Δi). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. r the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing relatin: in L Where: Δi L ; Δt D Δt s Δi * ( ) in in Maximum input vltage Output ltage Δi Inductr ripple current Switching frequency s in Δt Turn n time D Duty cycle... (4) If Δi 40%(I ), then the utput inductr is calculated t be 2.μH. Select L2.2 μh. The PCMB065T-22MS frm ishay prvides a cmpact, lw prfile inductr suitable fr this applicatin s 9
Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series esistance (ES). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as Δ Δ Δ Δ ( ESL) Δ ( ES) ( ES) ( C) + Δ ΔI in ΔI 8 * C ( ESL) L L * ES L * ESL * + Δ s ( C)... (5) The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure ). The resnant frequency f the LC filter is expressed as fllws: Gain 0 db LC 2 π L C igure shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system runs the risk f being unstable. -40dB/decade.........(6) Phase 0 0 Δ Output vltage ripple ΔI L Inductr ripple current Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determines the result f transient respnse, selectin f the capacitr is critical. The I84A can perfrm well with all types f capacitrs. As a rule, the capacitr must have lw enugh ES t meet utput ripple and lad transient requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre it is advisable t select ceramic capacitrs due t their lw ES and ESL and small size. Three f the Panasnic ECJ- 2B0J226ML (22u, 6., mohm) capacitrs is a gd chice. eedback Cmpensatin The I84A is a vltage mde cntrller. The cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed-lp transfer functin with the highest 0 db crssing frequency and adequate phase margin (greater than 45 ). LC requency -80 0 requency LC ig.. Gain and Phase f LC filter The I84A uses a vltage-type errr amplifier with high-gain (0dB) and wide-bandwidth. The utput f the amplifier is available fr DC gain cntrl and AC phase cmpensatin. The errr amplifier can be cmpensated either in type II r type III cmpensatin. Lcal feedback with Type II cmpensatin is shwn in ig. 4. This methd requires that the utput capacitr shuld have enugh ES t satisfy stability requirements. In general the utput capacitr s ES generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ES zer f the utput capacitr is expressed as fllws: ES 2 π*es*c... (7) 20
Z IN OUT 8 C POLE C4 Z f Where: in Maximum Input ltage sc Oscillatr amp ltage Crssver requency ES Zer requency f the Output Capacitr LC esnant requency f the Output ilter 8 eedback esistr H(s) db Gain(dB) Z 9 E E/A The transfer functin ( e / ) is given by: POLE The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: b ig. 4. Type II cmpensatin netwrk and its asympttic gain plt ( ) H s e Zf + s C H( s) Z s C 8 z 2π * * C...(8) irst select the desired zer-crssver frequency ( ): ES Use the fllwing equatin t calculate : IN.........(9) 4.........(20) 8 4 4 ( /5~/0) s > and * sc * in * * ES 2 LC * 8.........(2) e Cmp requency T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: 75% z LC z 0. 75* 2π L * C............(22) Use equatins (20), (2) and (22) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: P 2π * C * C 4 4 * C + C POLE POLE............(2) The ple sets t ne half f the switching frequency which results in the capacitr C POLE : C POLE π* *s C 4 π* *......(24) r a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ES values, we shuld implement lcal feedback with a type III cmpensatin netwrk. The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 5. Again, the transfer functin is given by: e By replacing Z in and Z f accrding t figure 5, the transfer functin can be expressed as: H( s) s ( C 8 4 Zf H( s) Z ( + s C 4 IN C + C ) + s C s [ + sc ( + )] ) 4 4 7 8 * C + C 0 ( + s 0...(25) C ) 7 2
ZIN OUT C Cmpensatr Type ES vs Output Capacitr C7 0 8 C4 Zf Type II LC < ES < < s /2 Electrlytic Tantalum 9 b E/A e Cmp Type III LC < < ES Tantalum Ceramic ig.5. Type III Cmpensatin netwrk and its asympttic gain plt The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: H(s) db P P2 P Z Z2 0..................(26) 2π * C4 * C 2π * C4 + C 2π * * C 2π * C Crss ver frequency is expressed as: Gain(dB) 0 * C7 * 7 * C 4 7 * ( in sc............(27) 2π *............(29) 8 + 0 * 2π * L * C E Z Z2 P2 P ) 2π * C * C 7 *...(28) 8 requency...(0)...........() Based n the frequency f the zer generated by the utput capacitr and its ES, relative t crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f the crssver frequency. The higher the crssver frequency, the ptentially faster the lad transient respnse. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. Typically, the cntrl lp bandwidth r crssver frequency is selected such that The DC gain shuld be large enugh t prvide high DC-regulatin accuracy. The phase margin shuld be greater than 45 fr verall stability. r this design we have: in 2.8 sc.8 ref 0.7 L 2.2 uh C x22u, ESmOhm each It must be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. r instance, the small signal capacitance f the 22u capacitr used in this design is 2u at.8 DC bias and 600 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency LC and using equatin (6) t cmpute the small signal C. These result t: LC 7.88 khz ES 4.4 MHz s /200 khz ( /5~/0) s * Select crssver frequency: 80 khz Since LC < < s /2< ES, TypeIII is selected t place the ple and zers. 22
Detailed calculatin f cmpensatin TypeIII Desired Phase Margin Θ 70 Z2 P2 Select: P Select: 0.5* Select:C Calculate sin Θ 4. khz + sin Θ + sin Θ 45.7kHz sin Θ Z 7 0. 5* 00 khz 2.2n Calculate, C 2π * * L * C * C * s C4 2π * * Z C 2π * * P 7 0, ; C ; C 8 Z2 7.05kHz and and C in 2.74 kω 4 4 sc 9.62p, and : ; : 2.7 kω 8.24 n, Select: 9 4 Select: C C 8.2 n 80p Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr ( OCSET ) frm the SW pin t the OCSet pin. The resistr can be calculated by using equatin (4). This resistr OCSET must be placed clse t the IC. The DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrst case peratin. I SET I I I DS( n) SET I 24.5 mω *.25 0.625mΩ A*.5 4.5 A (50% ver nminal utput current ) OCSet OCSet L( critical ) ( LIM) OCSet I DS( n) 59.07μA (at OCSet 2. kω Select 600kHz) 2.26kΩ Setting the Pwer Gd Threshld A windw cmparatr internally sets a lwer Pwer Gd threshld at 0.6 and an upper Pwer Gd threshld at 0.8. When the vltage at the B pin is within the windw set by these threshlds, PGd is asserted. The PGd is an pen drain utput. Hence, it is necessary t use a pull up resistr PG frm PGd pin t cc. The value f the pull-up resistr must be chsen such as t limit the current flwing int the PGd pin, when the utput vltage is nt in regulatin, t less than 5 ma. A typical value used is 0kΩ. s.........(2) 7 0 2π * C * 7 P2 ; 0 60 Ω, Select: 0 58 Ω 8 2π * C * Select: 8 7 Z2-4.99kΩ 0 ; 8 5 kω, ref 9 - ref * ; 8 9.8kΩ Select: 9.6kΩ 2
Applicatin Diagram: ig. 6. Applicatin circuit diagram fr a 2 t.8, A Pint Of Lad Cnverter Suggested Bill f Materials fr the applicatin circuit: Part eference Quantity alue Descriptin Manufacturer Part Number 0u SMD Elecrlytic, size, 25, 20% Panasnic EE-KEP Cin 0u 206, 6, X5, 20% TDK C26X5E06M 0.u 060, 25, X7, 0% Panasnic ECJ-BE04K L 2.2uH 7x6.5x5mm, 20%, 8A Cyntec PCMB065T-22MS C 22u 0805, 6., X5, 20% Panasnic ECJ-2B0J226ML 49.9k Thick ilm, 060,/0 W,% hm MC0EZPX4992 2 7.5k Thick ilm, 060,/0W,% hm MC0EZPX750 t 2.7k Thick ilm, 060,/0W,% hm MC0EZPX272 cset 2.26k Thick ilm, 060,/0W,% hm MC0EZPX226 PG 0k Thick ilm, 060,/0W,% hm MC0EZPX002 C ss C6 2 0.u 060, 25, X7, 0% Panasnic ECJ-BE04K 2.74k Thick ilm, 060,/0W,% hm MC0EZPX274 C 80p 50, 060, NPO, 5% Panasnic ECJ-CH8J C4 8.2n 060, 50, X7, 0% Panasnic ECJ-BH822K 8 4.99k Thick ilm, 060,/0W,% hm MC0EZPX499 9.6k Thick ilm, 060,/0W,% hm MC0EZPX6 0 58 Thick ilm, 060,/0W,% hm EJ-EK580 C7 2200p 060, 50, X7, 0% Panasnic ECJ-BH222K C cc.0u 060, 6, X5, 20% Panasnic ECJ-BBC05M U I84A SupIBuck, A, PQN 5x6mm Internatinal ectifier 24
TYPICAL OPEATING WAEOMS in2.0, cc5,.8, I0-A, m Temperature, N Air lw ig. 7. Start up at A Lad Ch : in, Ch 2 :, Ch : ss, Ch 4 :Enable ig. 8. Start up at A Lad, Ch : in, Ch 2 :, Ch : ss, Ch 4 : PGd ig. 9. Start up with.62 Pre Bias, 0A Lad, Ch 2 :, Ch : SS ig. 20. Output ltage ipple, A lad Ch 2 : ig. 2. Inductr nde at A lad Ch :LX ig. 22. Shrt (Hiccup) ecvery Ch 2 :, Ch : SS 25
TYPICAL OPEATING WAEOMS in2, cc5,.8, I.5A-A, m Temperature, N Air lw ig. 2. Transient espnse,.5a t A step 2.5A/μs Ch 2 :, Ch 4 :I 26
TYPICAL OPEATING WAEOMS in2, cc5,.8, IA, m Temperature, N Air lw ig. 24. Bde Plt at A lad shws a bandwidth f 82kHz and phase margin f 56 degrees 27
Simultaneus Tracking at Pwer Up and Pwer Dwn in2,.8, IA, m Temperature, N Air lw. 4.99K s I84A I624 Seq b OUT 8 4.99K.6K s2 9.6K ig. 25: Simultaneus Tracking a. input at pwer-up and shut-dwn Ch2: ut Ch:SS Ch4: Seq 28
eedback trace shuld be kept away frm nise surces PGnd ig. 26b. IDC84A dembard layut cnsideratins Bttm Layer Analg Grund plane Single pint cnnectin between AGND & PGND, shuld be clse t the SupIBuck, kept away frm nise surces. Pwer in Grund Plane AGnd ig. 26c. IDC84A dembard layut cnsideratins Mid Layer Use separate traces fr cnnecting Bt cap and cset t the switch nde and with the minimum length traces. Avid big lps. ig. 26d. IDC84A dembard layut cnsideratins Mid Layer 2 29
PCB Metal and Cmpnents Placement Lead lands (the IC pins) width shuld be equal t nminal part lead width. The minimum lead t lead spacing shuld be 0.2mm t minimize shrting. Lead land length shuld be equal t maximum part lead length + 0. mm utbard extensin. The utbard extensin ensures a large and inspectable te fillet. Pad lands (the 4 big pads ther than the IC pins) length and width shuld be equal t maximum part pad length and width. Hwever, the minimum metal t metal spacing shuld be n less than 0.7mm fr 2 z. Cpper; n less than 0.mm fr z. Cpper and n less than 0.2mm fr z. Cpper. 0
Slder esist It is recmmended that the lead lands are Nn Slder Mask Defined (NSMD). The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.025mm t ensure NSMD pads. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.05mm t accmmdate slder resist mis-alignment. Ensure that the slder resist in-between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land.
Stencil Design The Stencil apertures fr the lead lands shuld be apprximately 80% f the area f the lead lads. educing the amunt f slder depsited will minimize the ccurrences f lead shrts. If t much slder is depsited n the center pad the part will flat and the lead lands will be pen. The maximum length and width f the land pad stencil aperture shuld be equal t the slder resist pening minus an annular 0.2mm pull back t decrease the incidence f shrting the center land t the lead lands when the part is pushed int the slder paste. 2
BOTTOM IEW I WOLD HEADQUATES: 2 Kansas St., El Segund, Califrnia 90245, USA Tel: (0) 252-705 TAC ax: (0) 252-790 This prduct has been designed and qualified fr the Industrial market (Nte5) isit us at www.irf.cm fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 08/2