Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto. High Speed 64kb SRAM. ECE 4332 Fall 2013

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Transcription:

Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto High Speed 64kb SRAM ECE 4332 Fall 2013

Outline Problem Design Approach & Choices Circuit Block Architecture Novelties Layout Simulations & Metrics Future Work

Problem Portable Instruments Company (PICo) desires SRAM for a new mobile node o o High Speed 64kb cache, or 2 Mb Low Power SRAM Team VLSE s problem: o o First priority: delay Seek to also minimize area, power, and energy

Design Approach Architecture Level o Pareto Curve 32-Blocks Carr D., Park J., Reyno D. A High Speed 64kb SRAM Cache in 45nm Technology (2010)

Pins Decoders Final Schematic Block 0 Block 1 0 1 31

Block Diagram

Block Level Transmission gates o AND, MUXes, etc.

Bit Cell Level Traditional design

Bit Cell Level Pass Gate PDN NMOS γ = I SD = W D L A I SA L D W A I cell < I SD γ I cell > γ I SA γ+1 I cell > I SD I cell < I SA γ+1 All equations and images on this page are from Ding-Ming Kwai & IP Library Company

Bit Cell Level Carr D., Park J., Reyno D. High Speed Cache Powerpoint Presentation to PICo (2010) Desire: small area & stable Q Reality: only need to get below V M, don t need to get below V T We ended up with a cell ratio of 1.2 and Pull-up ratio of 1.11, following Carr et al. s (2010) successful design choices as well

Device Level W/L determined by sweeping and using previously mentioned ratios o o o PMOS: 180n NMOS: 240n Pass Gate: 200n Compared to previous years, industry standard, etc. o Short Answer: bigger

Novelties Latching Voltage Sense Amplifier Stacked Transmission Gate Decoders

Sense Amplifier Differential Main Idea: BL > BLB: Output = high BL < BLB: Output = low ΔV BL = I cell Δt / C BL Pros Easy to implement Dynamic Low Power ECE410 Chapter 13 Lecture at Michigan State Cons Dynamic

Latching Voltage Sense Amplifier Pros ~23% Faster Reads* o Therefore, ~23% smaller ΔV Low power Cons More FETs/Larger area *Based on 2011 Team 1 measurement Ryan, J. F., & Calhoun, B. H. Minimizing offset for latching voltagemode sense amplifiers for sub-threshold operation (2008)

Layout Note: No taps are present in the layout We attempted to optimize area as well Clutter

6T Cell Layout 1.0675 μm 2.16 μm

2x2 Cell Layout

Block Layout 60.295 μm 69.12 μm

Block with Peripherals 69.63μm x 74.365μm

Sense Amp Differential Voltage Latching Sense Amplifier Messy, Cluttered

Transmission Gate Versatile, Used in most of the peripherals Helpful with other layouts

32b Decoder Layout

64b Decoder Layout

Testbench Simulation setup for SRAM Reads and Writes To emulate conditions seen in full array: Recreate worst case paths For both inputs and outputs

Simulation Results PRECHARGE WORDLINE READ WRITE DATA Q QB OUT

Metrics Metrics Our Group Comparison to Team XOR (2010) Total Metric 1.024 x 10-29 J s 2 mm2 W Better by 882% 1 Bitcell Area 2.3 μm 2 Worse by 130% Total Area 0.1657 mm 2 Worse by 22% Total Energy 3.0348 nj Worse by 20% Read Delay 0.54 ns Better by 63% Write Delay 0.11 ns Better by 58% Total Delay 0.54 ns Better by 63% Idle Power.0698 W Better by 41%

Future Refinement SKILL and OCEAN Move further on the Pareto curve Predecoding Error Correcting Code Vectorize signals Ultra-thin Layout Carr D., Park J., Reyno D. A High Speed 64kb SRAM Cache in 45nm Technology (2010)

Acknowledgments Divya Akella University of Virginia Aatmesh Shrivastava, PICo liaison Dr. Benton Calhoun, PICo liaison & Team XOR (2010), Team 2 (2010), Team 1 (2011), and many others! We also acknowledge and offer good luck to Team Innovation!

Questions? ಠ_ಠ

References [All pictures are cited in their captions] Calhoun, B., Design Principles for Digital CMOS Integrated Circuits, (March 7, 2012) L. Hamouche and B. Allard, Low power options for 32nm always-on SRAM architecture, Solid State Electronics, 2011. Mann, R., and B. Calhoun, "New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm", ISQED, 2011. Rabaey, J., Chandrakasan A., Nikolic, B., Digital Integrated Circuits (2nd Edition), (Dec 24, 2002) Rabaey, J. Digital Integrated Circuits: A Design Perspective. Prentice Hall, 2003. Ryan, J. F., & Calhoun, B. H. Minimizing Offset for Latching Voltage Mode Sense Amplifiers for Sub-Threshold Operation. 9th International Symposium on Quality Electronic Design, 2008. Wang, A., Calhoun, B. H., & Chandrakasan, A. P. Sub-Threshold Design for Ultra Low-Power Systems. Springer, 2006. Previous Groups from ECE 4332 VLSI Design at University of Virginia (e.g. 2009, 2010, 2011, 2012)

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