POWER-MANAGEMENT circuits are becoming more important

174 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 3, MARCH 2011 Dynamic Bias-Current Boosting Technique for Ultralow-Power Low-Dropout Regulator in Biomedical Applications Marco Ho, Student Member, IEEE, and Ka Nang Leung, Senior Member, IEEE Abstract A dynamic bias-current boosting technique that concurrently enables ultralow-power operation and fast-transient behavior is presented in this brief. It is applied to an ultralow-power output-capacitor-free low-dropout regulator (LDO) to demonstrate the bandwidth extension provided during the transient periods. The proposed LDO is capable of providing 50 ma of output current with a minimum dropout voltage of 0.1 V. The ultralow-power LDO is implemented in a commercial 0.13-µm CMOS process, with power consumption of 1.20 µw only. Experimental results verify that both the load- and line-transient responses of the proposed LDO are significantly improved, and the settling times during load and line transients are shortened by as much as 33 and 3 times, respectively. Index Terms Dynamic biasing, low-dropout regulator (LDO), transient enhancement. I. INTRODUCTION POWER-MANAGEMENT circuits are becoming more important in mobile systems such as radio frequency identification tags and implantable medical devices [1] [3], where the energy supplied to the systems are severely limited. Moreover, off-chip capacitors that can act as energy reservoirs and stabilize output voltages are usually not available in those embedded systems. As a result, low-power output-capacitor-free lowdropout regulator (LDO) is one of the widely used regulators in such mobile systems due to its low-noise characteristics and relatively simple structure [4] [7]. However, the mutually exclusive characteristics of the LDO low power, outputcapacitor-free, fast transient, and enhanced slew rate are essential for mobile systems but difficult to be attained. Recently, nonstatic biasing has been shown to be an effective way to improve transient responses in low-power design [8] [11]. Both adaptive biasing [8], [9] and dynamic biasing [10], [11], as demonstrated in Fig. 1, enable bias current to be dramatically increased for bandwidth extension and slewrate improvement. Slewing detection can be made by either monitoring an internal node, which is generally faster, or at the output, which is slightly slower due to longer signal path. Manuscript received September 1, 2010; revised October 27, 2010 and December 24, 2010; accepted January 7, 2011. Date of publication February 24, 2011; date of current version March 16, 2011. This work was supported by a grant from the Research Grant Council of Hong Kong SAR Government, under Project CUHK414209. This paper was recommended by Associate Editor M. Ghovanloo. The authors are with the Department of Electronic Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong (e-mail: mho@ee.cuhk.edu.hk; knleung@ee.cuhk.edu.hk). Digital Object Identifier 10.1109/TCSII.2011.2110330 Fig. 1. Biasing current of the LDO in (a) adaptive biasing and (b) dynamic biasing. TABLE I COMPARISON WITH OTHER SLEW-RATE ENHANCEMENT TECHNIQUES Moreover, extra current can be injected to the gate of the power transistor to facilitate faster slewing [8], [9], [11] or to be provided to the error amplifier to simultaneously improve both slewing and bandwidth. Furthermore, since bandwidth extension is only required when there are rapid changes in load currents or output voltages, dynamic biasing boost bias current only in the slewing period instead. A comparison with other nonstatic biasing technique is shown in Table I. This brief introduces a simple yet effective dynamic biascurrent boosting technique. To demonstrate its benefits in ultralow-power design, the proposed technique is applied to an output-capacitor-free LDO to show improvements in both load- and line-transient responses. This brief is organized as follows. Section II explains the concept of the proposed dynamic bias-current boosting technique. The technique is applied to a low-power output-capacitor-free LDO and is discussed in Section III. The experimental results of the LDOs with and 1549-7747/$26.00 2011 IEEE

HO AND LEUNG: BIAS-CURRENT BOOSTING TECHNIQUE FOR LDO IN BIOMEDICAL APPLICATIONS 175 Fig. 4. I V characteristics of the slewing-detection circuit with different transistor sizes. Fig. 2. Conceptual diagram of the proposed dynamic bias-current boosting technique. Fig. 3. circuit. (a) Conventional current-mirror amplifier. (b) Slewing-detection without the proposed technique are shown in Section IV. Finally, conclusions are given in Section V. II. PROPOSED DYNAMIC BIAS-CURRENT BOOSTING TECHNIQUE The conceptual diagram of the proposed dynamic biascurrent boosting circuit applied to an LDO is shown in Fig. 2. It consists of slewing-detection, amplification, and bias-boosting circuits. A. Slewing-Detection Circuit Consider a conventional current-mirror amplifier shown in Fig. 3(a). During slewing period, the inputs V IN+ and V IN are highly unbalanced and cause the internal node of V N to be abruptly changed. Based on the detection mechanism reported in [8], the improved complementary slewing-detection circuits are shown in Fig. 3(b). The voltages of V P and V N in a steady state are biased by the current-mirror amplifier. V HI is biased to be close to the supply voltage, and V LO is set to be close to ground in the steady state, which can be explained by the I V characteristics of the transistor pair shown in Fig. 4. The solid line shows the relationship between the V DS and I DS of the NMOS transistor of a particular (W/L) N, whereas the dashed lines show the relationships between V SD and I SD of the p-channel MOS (PMOS) transistor of different (W/L) P. Since the n-channel MOS (NMOS) and PMOS transistors in the slewing-detection circuit are connected in series, I DSN = I SDP and V DSN = V DD V SDP, where V DD is the supply voltage. For a particular (W/L) N and (W/L) P, the output voltage (V HI Fig. 5. Internal signals of the amplification and bias-boosting circuits during slewing. or V LO )isbiasedatv 2 (about 1/2 V DD ), with current flowing through both transistors being I 2. If the aspect ratio of the PMOS transistor is increased to, for example, 3/2 (W/L) P = 1.5(W/L) P, the output voltage must settle to a higher voltage, i.e., V 3, in order to allow for the same drain current, i.e., I 3,to flow through both transistors. It means that the NMOS transistor is forced into linear region. Similarly, if the aspect ratio of thepmosissetto2/3 (W/L) P =0.67 (W/L) P, the output voltage lowers to V 1, and the drain currents becomes I 1, where the PMOS transistor is operating in linear region. Consequently, V HI and V LO can be set close to the supply voltage and to the ground, respectively, by employing different transistor sizes, as shown in Fig. 3(b), to provide more swinging room for the triggering signal and to allow easier triggering mechanism by the amplification circuit shown in the next section. B. Amplification Circuit To effectively produce fast and large-magnitude triggering signals to the bias-boosting circuits, rail-to-rail amplification circuits are appended to the slewing-detection circuit. The amplification circuit is, in fact, composed of a simple CMOS inverter structure, which can effectively convert a slow-changing detection signal into a fast-transition rail-to-rail swing. The waveforms of the signals in the amplification circuit are shown in Fig. 5. V HI and V LO are connected to the inverter inputs,

176 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 3, MARCH 2011 can be reduced to save a chip area. The low on-resistance of the transistors in parallel of R B2 would drastically reduce the equivalent resistance. More current would flow through the diode-connected transistor in a short instant. As a result, V X is increased; thus, I B is boosted. The high-pass networks would also provide automatic shut-off feature to the bias-boosting circuit. After the change step of the triggering signal, which is coupled to M BN or M BP, the high-pass network naturally returns to its original biased state and automatically turns off the bias-boosting mechanism, thus guaranteeing fail-safe biasboosting operation and preventing the hard turn-on of the transistors, which unnecessarily increases the bias current outside of the slewing period. Fig. 6. Bias-boosting circuit. and the outputs are V UP and V DOWN, respectively. When a positive slewing period is detected, V O is slowly rises according to the slew rate. At this time, the voltage at V P is swung low to generate a large V SG for the PMOS transistor to provide the maximum current. Both V HI and V LO are consequently pulled up. V HI saturates close to the supply voltage, and V LO is pulled up from a low voltage level, which crosses the threshold level of the CMOS inverter structure and causes a full supplyto-ground swing at V DOWN. Similarly, if a negative slewing takes place, V N is swung high, both V HI and V LO are pulled down, and the inverter converts the high-to-low V HI signal to a full ground-to-supply swing at V UP. Hence, the amplification circuit generates fast-transition full-swing triggering signals, i.e., V UP and V DOWN. C. Bias-Boosting Circuit The bias-boosting circuit, providing complementary singleshot boosting in both positive and negative slewing periods, is shown in Fig. 6. V UP and V DOWN are rail-to-rail signals generated by slewing-detection and amplification circuits. During the steady state, V UP is set low, and V DOWN is pulled high so that both transistors M BN and M BP are turned off. The bias current I B is therefore defined by V B and the series-connected resistors R B1 and R B2. When slewing is detected, a rail-torail triggering signal is produced at either V UP or V DOWN.The high-pass network consisting of C N and R N, and C P and R P would couple the signal to momentarily turn on either M BN or M BP.ThevalueofR N controls the isolation between V GN and the ground, whereas C N controls the coupling capability of the triggering signal. The larger the time constant τ N = R N C N, the slower V GN will decay back to the steady state after bias boosting. However, extra care must be made to guarantee that the charge injected by C N would not cause gate-oxide breakdown. As a result, R N and C N are set to be 1 MΩ and 5 pf, respectively, to generate a bias-boosting pulse that lasts for 1 μs with 20-μA peak in order to drive the 6-pF gate capacitance of the power transistor for a minimum supply of 0.9 V. Since the amplitudes of the triggering signals are rail to rail and the edge times of the triggering signals are shortened by the amplification circuit, the size of the coupling capacitors III. ULTRALOW-POWER OUTPUT-CAPACITOR-FREE LDO WITH THE PROPOSED TECHNIQUE The proposed dynamic bias-current boosting circuit is applied to an ultralow-power output-capacitor-free LDO, designed using United Microelectronics Corporation 0.13-μm CMOS technology, which is shown in Fig. 7. The component parameters are listed in Table II. Since I B is designed to be as low as 10 na, the quiescent current for the whole LDO is only 1.24 μa. Fig. 8 shows the simulated frequency response of the proposed LDO under normal biasing (I B =10 na) and under maximum bias-current boosting (I B =20μA), with an output capacitor of 10 nf to model the loading parasitic capacitance. It is shown that the unity-gain frequency of the proposed LDO is extended from 8.5 to 217.9 khz, while the phase margin is only reduced from 89.4 to 87.0. Therefore, the dynamic biasboosting technique that significantly improves the response time of the LDO is with negligible effect on the stability. The pole at the output of the error amplifier p EA is pushed to a higher frequency when the bias is boosted. It would be less effective if this technique is applied to a generic LDO with an output capacitor where p EA is no longer the dominant pole, and care should be made so that the relocation of p EA can still be compensated by, e.g., pole-zero cancellation. To show the load- and line-transient improvements by the bias-boosting technique, the proposed LDO is simulated along with a conventional LDO, which is the same as the proposed LDO without C N and R N, and C P and R P. Both LDOs regulate a 0.9-V supply to a 0.8-V output with maximum load current of 50 ma. The load-transient responses of both LDOs are shown in Fig. 9. Both output-capacitor-free LDOs are subject to a load-current change between 0 A and 50 ma in 200 ns. It is noticed that I B of the proposed LDO is momentarily boosted during both positive and negative slewing. Therefore, the respond time of the proposed LDO is much faster than that of the conventional LDO. Line-transient responses of both LDOs are also simulated and shown in Fig. 10. The supply voltages of the LDOs are switched between 0.9 and 1.5 V in 500 ns. Again, I B of the proposed LDO is boosted during the supply fluctuations, and its settling time is significantly shortened. In both transient responses, the momentarily boosted I B recovers to its original state after load and line transients to

HO AND LEUNG: BIAS-CURRENT BOOSTING TECHNIQUE FOR LDO IN BIOMEDICAL APPLICATIONS 177 Fig. 7. Circuit implementation of the LDO with the proposed dynamic bias-current boosting circuit. TABLE II COMPONENT PARAMETERS OF THE PROPOSED LDO Fig. 9. Simulated load transient response of the (dashed) conventional and (solid) proposed LDOs (V IN =0.9V). Fig. 8. Simulated frequency response of the proposed LDO when (solid) I B =10nA and (dashed) I B =20µA. efficiently reduce the power consumption. It is shown that a minimum change of I O by +5/ 1 ma in 200 ns or a change of V IN by +0.1/ 0.3 V in 500 ns is capable of generating a bias boost to a maximum of 20 μa. The dynamic biasing technique is thus shown to be effective in enhancing the transient responses when applied to an ultralow-power LDO. Fig. 10. Simulated line transient response of the (dashed) conventional and (solid) proposed LDOs (I O =50mA). IV. EXPERIMENTAL RESULTS The output-capacitor-free LDO with the proposed dynamic bias-current boosting circuit has been implemented using a 0.13-μm CMOS process. A conventional LDO without the

178 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 58, NO. 3, MARCH 2011 Fig. 11. Micrograph of the proposed LDO. Fig. 12. Measured load transient response of the conventional and proposed LDOs (V IN =0.9V). from the positive and negative supply changes in 36 and 140 μs, respectively, whereas the conventional LDO requires 118 and 220 μs under the same change. It is shown that the dynamic bias-boosting technique can effectively provide extra energy during both load and line transients to improve the responses of the ultralow-power LDO. V. C ONCLUSION A dynamic bias-current boosting technique has been presented in this brief, and it has been applied to an ultralowpower output-capacitor-free LDO to demonstrate its advantages in enhancing transient responses. The measurement results verify that the proposed technique is effective in improving both the load- and line-transient responses of the LDO, with insignificant increase in quiescent current. The settling times of the proposed LDO during load- and line-transients have been reduced by as much as 33 and 3 times, respectively. The dynamic biasing technique is particularly useful in ultralow-power embedded design such as wearable or implantable biomedical devices, where quiescent current must be kept at minimum, but the transient response performances cannot be compromised. ACKNOWLEDGMENT The authors would like to thank J. Guo and K.-L. Mak for their suggestions and discussions. Fig. 13. Measured line transient response of the conventional and proposed LDOs (I O =50mA). proposed circuit has been also implemented for comparison. The capacitance and resistance values are 5 pf and 1 MΩ, respectively. Fig. 11 shows the micrograph of the proposed LDO, with an active area of 435 μm 70 μm. Both LDOs are shown to be stable with an output capacitance up to 10 nf. The LDOs can provide a 50-mA output current at 0.8 V, with a minimum supply of 0.9 V. The measured quiescent currents of the conventional and proposed LDOs are 1.30 and 1.33 μa, respectively. The load-transient responses of the LDOs are measured and shown in Fig. 12. The load current is switched between 0 A and 50 ma in 200 ns, with V IN =0.9 V. While the conventional LDO requires about 300 μs to settle from the step change, the proposed LDO can settle within 9 and 28 μs for the load increase and decrease, respectively. The bias current is boosted from about 10 na to a maximum of 20 μa. Fig. 13 shows the line-transient responses of both LDO under full load (i.e., I O =50mA). The supply voltages are changed between 0.9 and 1.5 V in 500 ns. The proposed LDO recovers REFERENCES [1] L. S. Y. Wong, S. Hossain, A. Ta, J. Edvinsson, D. H. Rivas, and H. Nääs, A very low-power CMOS mixed-signal IC for implantable pacemaker applications, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2446 2456, Dec. 2004. [2] H. Jiang, L. Zhang, C. Zhang, and Z. Wang, Wireless switch for implantable medical devices based on passive RF receiver, Electron. Lett., vol. 44, no. 17, pp. 1006 1008, Aug. 2008. [3] O. Omeni, A. C. W. Wong, A. J. Burdett, and C. Toumazou, Energy efficient medium access protocol for wireless medical body area sensor networks, IEEE Trans. Biomed. Circuits Syst.,vol.2,no.4,pp.251 259, Dec. 2008. [4] G. A. Rincon-Mora and P. E. Allen, A low-voltage, low quiescent current, low drop-out regulator, IEEE J. Solid-State Circuits, vol. 33, no. 1, pp. 36 44, Jan. 1998. [5] G. A. Rincon-Mora and P. E. Allen, Optimized frequency-shaping circuit topologies for LDOs, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 6, pp. 703 708, Jun. 1998. [6] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S. Borkar, Area-efficient linear regulator with ultra-fast load regulation, IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933 940, Apr. 2005. [7] K. N. Leung and P. K. T. Mok, A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation, IEEE J. Solid-State Circuits, vol. 38, no. 10, pp. 1691 1702, Oct. 2003. [8] H. Lee, P. K. T. Mok, and K. N. Leung, Design of low-power analog drivers based on slew-rate enhancement circuits for CMOS low-dropout regulators, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 9, pp. 563 567, Sep. 2005. [9] T. Y. Man, P. K. T. Mok, and M. Chan, A high slew-rate push pull output amplifier for low-quiescent current low-dropout regulators with transientresponse improvement, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 9, pp. 755 759, Sep. 2007. [10] P. Y. Or and K. N. Leung, An output-capacitorless low-dropout regulator with direct voltage-spike detection, IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 458 466, Feb. 2010. [11] E. N. Y. Ho and P. K. T. Mok, A capacitor-less CMOS active feedback low-dropout regulator with slew-rate enhancement for portable on-chip application, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 2, pp. 80 84, Feb. 2010.