SP and SP RS- or RS- Quad ifferential Line rivers Operates from a single +.V supply Interoperable +.0V logic Tri-state Output Control -V to +V Common-Mode Input Voltage Range Common river Enable Control (SP) Independent river Enable Controls for each pair of rivers (SP) Compatibility LTC and SN (SP) Compatibility LTC and SN (SP) +.V Low Power Quad RS-/RS- Line rivers Now Available in Lead Free Packaging ESCRIPTION The SP and the SP are +.V low power quad drivers that meet the specifications of the RS- and RS- serial protocols. These devices are pin-to-pin compatible Sipex's SP and SP devices as well as popular industry standards. The SP and SP feature Sipex's BiCMOS process allowing low power operation out sacrificing performance. The SP and SP meet the electrical specifications of RS- and RS- serial protocols up to 0Mbps under load. The SP features a common driver enable control. The SP provides independent driver enable controls for each pair of drivers. Both devices feature tri-state outputs and a -V to +V common-mode input voltage range. I O A O B SP I O A I O A O B SP I O A EN O B EN /EN O B O B EN O B EN /EN O A I GN 0 O B O A I O A I GN 0 O B O A I //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.... +.0V Input Voltages Logic... 0.V to +.0V rivers... 0.V to +.0V river Output Voltage... ±V Input Currents Logic... ±ma river... ±ma Storage Temperature... C to +0 C Power issipation Plastic IP... mw (derate mw/ C above +0 C) Small Outline... mw (derate mw/ C above +0 C) Lead Temperature (soldering, 0 sec)... 00 C SPECIFICATIONS =.V±%; typicals at C; T MIN T A T MAX unless otherwise noted. PARAMETER MIN. TYP. MAX. UNIT CONITIONS C CHARACTERISTICS igital Inputs I, EN, EN, EN /EN, EN /EN Voltage V IL 0. Volts V IH.0 Volts Input Current ± µa V IN = 0V to RIVER OUTPUTS ifferential Voltage Volts unloaded Volts R = 0Ω(RS-). Volts R = Ω (RS-); Figure Common Mode Output Voltage Volts R = Ω or 0Ω; Figure Change in Common Mode Output Magnitude 0. Volts R = Ω or 0Ω; Figure for Complementary Output State R = 0Ω (RS-) R = Ω (RS-) Maximum ata Rate 0 Mbps Short circuit Current V OH ±0 ma -V V O +V V OL ±0 ma -V V O +V High Impedance Output Current µa V O = -V to +V, T A = o C POWER REQUIREMENTS Supply Voltage.00.0.0 Volts Supply Current.00 µa No load, output enabled 0.0 µa No load, output disabled ENVIRONMENTAL AN MECHANICAL Operating Temperature C 0 +0 C E -0 + C Storage Temperature - +0 C Package _P pin Plastic IP _T pin SOIC //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
PINOUT SP VM I O A O B EN SP I O A O B GENERATOR (NOTE ) 0Ω VCC S RL = Ω CL = PF (NOTE ) OUT O B EN O A O B = + VOL.V I GN 0 O A I Figure. river Propagation elay Test Circuit Pin GN igital Ground. SP PINOUT Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O Pin O A river output A. Pin O B river output B. Pin EN river Output Enable. Please refer to SP Truth Table (). Pin O B river output B. Pin O A river output A. Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O Pin 0 O A river output A. Pin O B river output B. Pin EN river Output isable. Please refer to SP Truth Table (). GENERATOR (NOTE ) 0Ω Figure. river Enable and isable Timing Circuit, Output HIGH S CL = 0pF (NOTE ) = + VOL.V OUT RL = 0Ω VCC R S RL = 0Ω VCC VO R VOC 0V OR V GENERATOR (NOTE ) 0Ω CL = 0pF (NOTE ) OUT Figure. river C Test Load Circuit Figure. river Enable and isable Timing Circuit, Output LOW //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
PINOUT SP I O A O B SP I O A INPUT ENABLES OUTPUTS I EN EN OUTA OUTB H H X H L L H X L H EN /EN O B H X L H L O B EN /EN L X L L H O A I GN 0 O B O A I X L H Hi Z Hi Z Table. SP Truth Table Pin GN igital Ground. Pin O B river output B. Pin O A river output A. Pin I river Input If river output is enabled, logic 0 on I forces driver output O A low and O B high. A logic on I river output enabled forces driver O A high and O Pin Positive Supply +.00V< <+.0V SP PINOUT Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O Pin O A river output A. Pin O B river output B. Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O Pin 0 O A river output A. Pin O B river output B. Pin EN /EN river and Output Enable. Please refer to SP Truth Table (). Pin O B river output B. Pin O A river output A. Pin I river Input If river output is enabled, logic 0 on I forces driver output O A low and O B high. A logic on I river output enabled forces driver O A high and O Pin Positive Supply +.00V < < +.0V Pin EN /EN river and Output Enable. Please refer to SP Truth Table (). Pin O B river output B. Pin O A river output A. Pin I river Input If river output is enabled, logic 0 on I O A low and O B high. A logic on I river output enabled forces driver O and O INPUT ENABLES OUTPUTS I EN/EN or EN/EN OUTA OUTB H H H L L H L H X L Hi Z Hi Z Table. SP Truth Table //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
FEATURES The SP and the SP are +.V low power quad line drivers that meet the specifications of the RS- and RS- serial protocols. These devices are pin-to-pin compatible Sipex's SP and SP devices as well as popular industry standards. The SP and SP devices feature Sipex's BiCMOS process allowing low power operation out sacrificing performance. The RS- standard is ideal for multi-drop applications or for long distance interfaces. RS- allows up to drivers and receivers to be connected to a data bus, making it an ideal choice for multi-drop applications. Since the cabling can be as long as,000 feet, RS- transceivers are equipped a wide (-V to +V) common mode range to accomodate ground potential differences. ata is virtually immune to noise in the transmission line because the RS- protocol is a differential interface. river The drivers for both the SP and SP have differential outputs. The typical voltage output swing no load will be 0V to +V. With worst case loading of Ω across the differential outputs, the driver can maintain greater than +.V voltage levels. The drivers of the SP feature active HIGH and active LOW common driver enable controls. Refer to SP Truth Table in Table. The SP provides independent, active high driver enable controls for each pair of drivers. Refer to SP Truth Table in Table. The driver outputs are short-circuit limited to 0mA. The SP and SP drivers meet the electrical specifications of RS- and RS- serial protocols up to 0Mbps under load. AC PARAMETERS = +.V±%; typicals at C; T AMB = C unless otherwise noted. PARAMETER MIN. TYP. MAX. UNIT CONITIONS PROPAGATION ELAY river Input to Output Figure and Low to High (t PLH ) 0 0 0 ns High to Low (t PHL ) 0 0 0 ns ifferential river Skew 0 ns t PHL (Y) - t PLH (Y), t PHL (Z) - t PLH (Z), Figures and river Rise Time (t R ) 0% to 0% R IFF = 0Ω SP 0 ns SP 0 ns river Fall Time (t F ) 0% to 0% R IFF = 0Ω SP 0 ns SP 0 ns RIVER ENABLE To Output High 0 ns Figures and To Output Low 0 ns Figures and RIVER ISABLE From Output Low 0 ns Figures and From Output High 0 ns Figures and //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
INPUT V 0V.V.V tplh tphl Y OUTPUT VOL tphl tplh Z OUTPUT VOL = + VOL.V Figure. river Propagation elay Waveforms INPUT V 0V.V.V tpzh tphz OUTPUT HIGH 0V 0.V OUTPUT LOW VCC VOL tpzl tplz 0.V = Figure. river Enable and isable Timing Waveforms + VOL.V NOTE : The input pulse is supplied by a generator the following characteristics: INPUT=0kHz, 0% duty cycle, t r <.0ns, Z o =0Ω. NOTE : C L includes probe and stray capacitance. //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
PACKAGE: PIN PIP INEX AREA E E c ea TOP VIEW eb FRONT VIEW SIE VIEW Base Plane A A b b e b L A Seating Plane SYMBOL PIP JEEC MS-00 VARIATION BB N = Pins imensions in Inches: Controlling imension imensions in Millimeters Conversion Factor: Inch =.0 mm MIN NOM MAX MIN NOM MAX A - - 0.0 - -. A 0.0 - - 0. - - A 0. 0.0 0...0. b 0.0 0.0 0.0 0. 0. 0. b 0.0 0.00 0.00... b 0.00 0.0 0.0 0. 0.. c 0.00 0.00 0.0 0.0 0. 0. 0.00 - - 0.00 - - E 0.00 0.0 0.... E 0.0 0.0 0.0.0.. e 0.00 BSC 0.00 BSC ea 0.00 BSC 0.0 BSC eb - - 0.0 - - 0. L 0. 0.0 0.0..0. 0. 0. 0.... SIPEX Pkg Signoff ate/rev: JL Nov-0/ Rev A //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
SIE VIEW E/ E/ E E A A A Seating Plane INEX AREA (0. X 0.E) TOP VIEW e b (L) FRONT VIEW Gauge Plane h h ø ø R R ø L L Seating Plane ø c PIN WSOIC JEEC MS-0 Variation AA imensions in Inches Conversion Factor: SYMBOL imensions in Millimeters: Controlling imension Inch =.0 mm MIN NOM MAX MIN NOM MAX A. -. 0.0-0.0 A 0.0-0.0 0.00-0.0 A.0 -. 0.0-0.00 b 0. - 0. 0.0-0.00 c 0.0-0. 0.00-0.0 E E e h 0. 0.0 BSC.0 BSC. BSC - 0. 0.00 0.0 BSC 0. BSC 0.00 BSC - 0.00 L 0.0 -. 0.0-0.00 L L R 0.0.0 REF 0. BSC - - 0.00 0.0 REF 0.00 BSC - - R 0.0 - - 0.00 - - ø 0º - º 0º - º ø º - º º - º ø 0º - - 0º - - 0.0 REF 0.0 REF SIPEX Pkg Signoff ate/rev: JL Oct-0/ Rev A //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation
ORERING INFORMATION Quad RS rivers: Model... Enable/isable... Temperature Range... Package SPCP... Common; active Low and Active High... 0 C to +0 C... pin Plastic IP SPCT... Common; active Low and Active High... 0 C to +0 C... pin WSOIC SPEP... Common; active Low and Active High... 0 C to + C... pin Plastic IP SPET... Common; active Low and Active High... 0 C to + C... pin WSOIC SPCP... One per driver pair; active High... 0 C to +0 C... pin Plastic IP SPCT... One per driver pair; active High... 0 C to +0 C... pin WSOIC SPEP... One per driver pair; active High... 0 C to + C... pin Plastic IP SPET... One per driver pair; active High... 0 C to + C... pin WSOIC Please consult the factory for pricing and availability on a Tape-On-Reel option. Now available in Lead Free. To order add -L to the part number. Example: SPCT = normal, SPCT-L = Lead free. Note: SP is not recommended for new designs. Contact factory for availability options. Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation Headquarters and Sales Office South Hillview rive Milpitas, CA 0 TEL: (0) -00 FAX: (0) -00 Sales Office Linnell Circle Billerica, MA 0 TEL: () -00 FAX: () 0-00 e-mail: sales@sipex.com Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. //0 SP/ Low Power Quad RS/ Line rivers Copyright 00 Sipex Corporation