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N-channel 30 V, 0.012 Ω, 8 A - PowerFLAT (3.3x3.3) ultra low gate charge STripFET Power MOSFET Features Type V DSS R DS(on) I D 30V <0.015Ω 8A (1) Improved die-to-footprint ratio Very low profile package (1mm max) Very low thermal resistance Very low gate charge Low threshold device In compliance with the 2002/95/EC European directive Description This application specific Power MOSFET is the latest generation of STMicroelectronics unique STripFET technology. The resulting transistor is optimized for low on-resistance and minimal gate charge. The chip-scaled PowerFLAT package allows a significant board space saving, still boosting the performance. Applications Switching application Table 1. Device summary Figure 1. PowerFLAT (3.3x3.3) (Chip Scale Package) Internal schematic diagram TOP VIEW Order code Marking Package Packaging 8NH3L PowerFLAT (3.3x3.3) Tape and reel September 2009 Doc ID 10681 Rev 8 1/12 www.st.com 12

Contents Contents 1 Electrical ratings............................................ 3 2 Electrical characteristics..................................... 4 2.1 Electrical characteristics (curves)............................ 6 3 Test circuits.............................................. 8 4 Package mechanical data..................................... 9 5 Revision history........................................... 11 2/12 Doc ID 10681 Rev 8

Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V DS Drain-source voltage (V GS = 0) 30 V V GS Gate-source voltage ± 18 V (1) I D Drain current (continuous) at T C = 25 C 8 A I D (1) Drain current (continuous) at T C =100 C 5 A I DM (2) P TOT (3) Drain current (pulsed) 32 A Total dissipation at T C = 25 C 50 W P TOT (1) Total dissipation at T C = 25 C 2 W T J T stg Derating factor 0.4 W/ C Operating junction temperature Storage temperature 1. The value is rated according Rthj-pcb 2. Pulse width limited by safe operating area. 3. The vaule is rated according Rthj-c Table 3. Thermal resistance -55 to 150 C Symbol Parameter Value Unit R thj-case Thermal resistance junction-case (drain) 2.5 C/W R (1) thj-pcb Thermal resistance junction-pcb 42.8 C/W (2) R thj-pcb Thermal resistance junction-pcb 63.5 C/W 1. When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 sec 2. Steady state Doc ID 10681 Rev 8 3/12

Electrical characteristics 2 Electrical characteristics (T CASE = 25 C unless otherwise specified) Table 4. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS I GSS Drain-Source breakdown voltage Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) I D = 250 µa, V GS = 0 30 V V DS = max rating, V DS = max rating @125 C 1 10 µa µa V GS = ±18 V ±100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa 1 2.5 V R DS(on) Table 5. Static drain-source on resistance Dynamic V GS = 10 V, I D = 4 A V GS = 4.5 V, I D = 4 A 0.012 0.0135 0.015 0.017 Symbol Parameter Test conditions Min. Typ. Max. Unit g fs (1) C iss C oss C rss Q g Q gs Q gd R G Forward transconductance V DS =15 V, I D = 4 A 30 S Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge 1. Pulsed: pulse duration= 300 µs, duty cycle 1.5% Table 6. Gate input resistance Switching times V DS =25 V, f=1 MHz, V GS =0 V DD =15 V, I D = 8 A V GS =4.5 V (see Figure 8) f=1 MHz gate DC bias = 0 test signal level = 20mV open drain 965 285 38 9 3.7 3 Ω Ω pf pf pf 12 nc nc nc 0.5 1.5 2.5 Ω Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) t r t d(off) t f Turn-on delay time Rise time Turn-off delay time Fall Time V DD =15 V, I D = 4 A, R G =4.7 Ω, V GS =4.5 V (see Figure 14) - 15 32 18 8.5 - ns ns ns ns 4/12 Doc ID 10681 Rev 8

Electrical characteristics Table 7. Source drain diode Symbol Parameter Test conditions Min Typ. Max Unit I SD Source-drain current - 8 A I SDM (1) V SD (2) Source-drain current (pulsed) - 32 A Forward on voltage I SD = 8 A, V GS = 0-1.3 V t rr Q rr I RRM Reverse recovery time Reverse recovery charge Reverse recovery current 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration= 300 µs, duty cycle 1.5 % I SD =8 A, di/dt = 100 A/µs, V DD =20 V, Tj=150 C (see Figure 16) - 24 17.4 1.45 ns nc A Doc ID 10681 Rev 8 5/12

Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/12 Doc ID 10681 Rev 8

Electrical characteristics Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations Figure 10. Figure 12. Normalized gate threshold voltage vs temperature Source-drain diode forward characteristics Figure 11. Normalized on resistance vs temperature Figure 13. Normalized B VDSS vs temperature Doc ID 10681 Rev 8 7/12

Test circuits 3 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit Figure 16. Inductive load switching and diode recovery times Figure 17. Unclamped inductive load test circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 8/12 Doc ID 10681 Rev 8

Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 8. Package dimensions Dim. mm. inch Min. Typ Max. Min. Typ. Max. A 0.80 0.90 1.00 0.031 0.035 0.039 A1 0.02 0.05 0.0007 0.0019 A3 0.20 0.007 b 0.23 0.30 0.38 0.009 0.011 0.015 C 0.328 0.012 C1 0.12 0.004 D 3.30 0.13 D2 2.50 2.65 2.75 0.098 0.104 0.108 E 3.30 0.13 E2 1.25 1.40 1.50 0.049 0.055 0.059 F 1.325 0.052 F1 0.975 0.038 e 0.65 0.025 L 0.30 0.50 0.011 0.019 Doc ID 10681 Rev 8 9/12

Package mechanical data Figure 20. Package drawing Figure 21. Recommended footprint (dimensions in mm) AM03834v1 10/12 Doc ID 10681 Rev 8

Revision history 5 Revision history Table 9. Document revision history Date Revision Changes 21-Jul-2004 1 First release 05-Oct-2004 2 Values changed 19-Oct-2004 3 New value inserted 22-Nov-2004 4 Document updated 21-Feb-2005 5 Final version 18-Apr-2005 6 Modified Figure 4, Figure 6., Figure 9.,Figure 10. 14-Mar-2006 7 New template 10-Sep-2009 8 Inserted Figure 21 Doc ID 10681 Rev 8 11/12

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