EE47 Lecture 7 DAC Converters (continued) DAC dynamic non-idealities DAC design considerations Self calibration techniques Current copiers Dynamic element matching DAC reconstruction filter ADC Converters Sampling Sampling switch induced distortion Sampling switch charge injection EECS 47 Lecture 7: Data Converters 006 H.K. Page Summary of Last Lecture D/A converters continued: Current based DACs-unit element versus binary weighted R-R type DACs Static performance Component matching-systematic & random errors Component variations Gaussian pdf INL for both unit-element and binary-weighted DACs σ DNL= σ ε x B/- DNL for unit-element σ DNL= σ ε DNL for binary-weight DAC: σ DNL= σ ε x B/ Practical aspects of current-switched DACs Segmented current-switched DACs EECS 47 Lecture 7: Data Converters 006 H.K. Page
DAC Dynamic Non-Idealities Finite settling time Linear settling issues: (e.g. RC time constants) Slew limited settling Spurious signal coupling Coupling of clock/control signals to the output via switches Timing error related glitches Control signal timing skews EECS 47 Lecture 7: Data Converters 006 H.K. Page 3 Dynamic DAC Error: Timing Glitch Consider binary weighted DAC transition 0 00 DAC output depends on timing Plot shows situation where the control signals for LSB & MSB LSB/MSBs on time LSB early, MSB late LSB late, MSB early Ideal Late 0 5 0 Early0 5 0 0 5 0.5.5 3.5.5 3.5.5 3 Time EECS 47 Lecture 7: Data Converters 006 H.K. Page 4
Glitch Energy Glitch energy (worst case) proportional to: dt x B- dt error in timing & B- associated with half of the switches changing state LSB energy proportional to: T=/f s Need dt x B- << T or dt << -B+ T Examples: f s [MHz] 0 000 B 6 0 dt [ps] << 488 <<.5 << EECS 47 Lecture 7: Data Converters 006 H.K. Page 5 DAC Dynamic Errors To suppress effect of non-idealities: Retiming of current source control signals Each current source has its own clocked latch incorporated in the current cell Minimization of latch clock skew by careful layout ensuring simultaneous change of bits To minimize control and clock feed through to the output via G-D of the switches Use of low-swing digital circuitry EECS 47 Lecture 7: Data Converters 006 H.K. Page 6
DAC Implementation Examples Untrimmed segmented T. Miki et al, An 80-MHz 8-bit CMOS D/A Converter, JSSC December 986, pp. 983 A. Van den Bosch et al, A -GSample/s Nyquist Current-Steering CMOS D/A Converter, JSSC March 00, pp. 35 Current copiers: D. W. J. Groeneveld et al, A Self-Calibration Technique for Monolithic High-Resolution D/A Converters, JSSC December 989, pp. 57 Dynamic element matching: R. J. van de Plassche, Dynamic Element Matching for High- Accuracy Monolithic D/A Converters, JSSC December 976, pp. 795 EECS 47 Lecture 7: Data Converters 006 H.K. Page 7 8x8 array μ tech., 5Vsupply 6+ segmented EECS 47 Lecture 7: Data Converters 006 H.K. Page 8
Two sources of systematic error: - Finite current source output resistance - Voltage drop due to finite ground bus resistance EECS 47 Lecture 7: Data Converters 006 H.K. Page 9 Current-Switched DACs in CMOS I = k( VGS V ) M th VGS = V M GS 4RI, V M GS = V M3 GS 7RI I M out VGS = V M4 GS 9RI, V M GS = V M5 GS 0RI M 4RI I k( VGS V ) M th I V = = DD VGS V M th I gm = M I M M I M 3 VGS V I M 4 3 I M 5 4 I 5 M th 4Rgm M I = I I ( 4Rgm ) M 7Rgm Rx4I Rx3I RxI RxI M I3 = I I ( 7Rgm ) M 9Rgm M I4 = I I ( 9Rgm ) Example: 5 unit element current sources M 0Rgm M I5 = I I ( 0Rgm ) M Assumption: RI is small compared to transistor gate overdrive Desirable to have gm small EECS 47 Lecture 7: Data Converters 006 H.K. Page 0
INL [LSB] 0.3 0. 0. 0-0. 0 Current-Switched DACs in CMOS Example: INL of 3-Bit unit element DAC 3 4 5 6 7 Input Sequential current source switching Symmetrical current source switching Example: 7 unit element current source DAC- assume g m R=/00 If switching of current sources sequential (--3-4-5-6-7) INL= +0.5LSB If switching of current sources symmetrical (4-3-5--6--7 ) INL = +0.09, -0.058LSB INL reduced by a factor of.6 EECS 47 Lecture 7: Data Converters 006 H.K. Page Current-Switched DACs in CMOS Example: DNL of 7 unit element DAC 0. DNL [LSB] 0. 0-0. -0. Sequential current source switching Symmetrical current source switching 3 4 5 6 7 Input Example: 7 unit element current source DAC- assume gamer=/00 If switching of current sources sequential (--3-4-5-6-7) DNL max = + 0.5LSB If switching of current sources symmetrical (4-3-5--6--7 ) DNL max = + 0.5LSB DNL unchanged EECS 47 Lecture 7: Data Converters 006 H.K. Page
(5+5) More recent published DAC using symmetrical switching built in 0.35μ/3V analog/.9v digital, area x0 smaller compared to previous example EECS 47 Lecture 7: Data Converters 006 H.K. Page 3 Layout of Current sources -each current source made of 4 devices in parallel each located in one of the 4 quadrants Thermometer decoder used to convert incoming binary digital control for the 5 MSB bits Dummy decoder used on the LSB side to match the latency due to the MSB decoder EECS 47 Lecture 7: Data Converters 006 H.K. Page 4
Current source layout MSB current sources layout in the mid sections of the four quad LSB current sources on the periphery Two rows of dummy current sources added to create identical environment for devices in the center versus the ones on the outer sections EECS 47 Lecture 7: Data Converters 006 H.K. Page 5 Note that each current cell has its clocked latch and clock signal laid out to be close to its switch to ensure simultaneous switching of current sources Special attention paid to the final latch to have the cross point of the complementary switch control signal such that the two switches are not both turned off during transition EECS 47 Lecture 7: Data Converters 006 H.K. Page 6
Measured DNL/INL with current associated with the cells as a variable EECS 47 Lecture 7: Data Converters 006 H.K. Page 7 EECS 47 Lecture 7: Data Converters 006 H.K. Page 8
6bit DAC (6+0)- MSB DAC uses calibrated current sources I/ I/ Current Divider I EECS 47 Lecture 7: Data Converters 006 H.K. Page 9 EECS 47 Lecture 7: Data Converters 006 H.K. Page 0
Current Divider Accuracy Id+ I Id = di I = I I I d d d d d d W di d d L = dvth W + I d V GS V th L I/ I/ M M I Ideal Current Divider I/+dI d / M M I I/-dI d / Real Current Divider M& M mismatched Problem: Device mismatch could severely limit DAC accuracy EECS 47 Lecture 7: Data Converters 006 H.K. Page EECS 47 Lecture 7: Data Converters 006 H.K. Page
Dynamic Element Matching During Φ During Φ () I = I o +Δ () I = I o Δ ( ) ( ) () () I + I I = ( Δ ) + ( +Δ ) Io = Io I () = I o Δ () I = I o +Δ ( ) ( ) f clk I o / I o / I I / error Δ I o EECS 47 Lecture 7: Data Converters 006 H.K. Page 3 EECS 47 Lecture 7: Data Converters 006 H.K. Page 4
Dynamic Element Matching () () I = Io( + Δ) I = Io( Δ) () () I = I ( Δ ) I = I ( + Δ ) During Φ During Φ I I I o / o /4 o /4 o o f clk I 3 I 4 I I () 3 = = I () I 4 o ( + Δ ) ( + Δ )( + Δ ) I () 3 = = I () I 4 o ( Δ ) ( Δ )( Δ ) / error Δ I 3 () I3 + I = Io = 4 Io = 4 () 3 ( + Δ )( + Δ ) + ( Δ )( Δ ) ( + Δ Δ ) f clk I / error Δ E.g. Δ = Δ = % matching error is (%) = 0.0% I o EECS 47 Lecture 7: Data Converters 006 H.K. Page 5 Bipolar -bit DAC using dynamic element matching built in 976 Element matching clock frequency 00kHz INL <0.5LSB! EECS 47 Lecture 7: Data Converters 006 H.K. Page 6
DAC In the Big Picture Analog Input Learned to build DACs Convert the incoming digital signal to analog DAC output staircase form Some applications require filtering of DAC output reconstruction filter Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization 000...00... 0 "Bits to Staircase" Reconstruction Filter EECS 47 Lecture 7: Data Converters 006 H.K. Page 7 DAC Reconstruction Filter Need for and requirements depend on application Tasks: Correct for sinc droop Remove aliases (stair-case approximation) DAC Input sinc DAC Output B f s / 0.5 0 0 0.5.5.5 3 x 0 6 0.5 0 0 0.5.5.5 3 x 0 6 0.5 0 0 0.5.5.5 3 Frequency x 0 6 EECS 47 Lecture 7: Data Converters 006 H.K. Page 8
Reconstruction Filter Options Digital Filter DAC SC Filter CT Filter Digital and SC filter possible only in combination with oversampling (signal bandwidth B << f s /) Digital filter Band limits the input signal prevent aliasing Could also provide high-frequency pre-emphasis to compensate in-band sinc amplitude droop associated with the inherent DAC S/H function EECS 47 Lecture 7: Data Converters 006 H.K. Page 9 DAC Reconstruction Filter Example: Voice-Band CODEC Receive Path f s = 04kHz f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz f s = 8kHz Ref: D. Senderowicz et. al, A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip, IEEE Journal of Solid-State Circuits, Vol.-SC-7, No. 6, pp.04-03, Dec. 98. EECS 47 Lecture 7: Data Converters 006 H.K. Page 30
Summary D/A Converter D/A architecture Unit element complexity proportional to B - excellent DNL Binary weighted- complexity proportional to B- poor DNL Segmented- unit element MSB(B )+ binary weighted LSB(B ) complexity proportional ( B -) + B DNL compromise between the two Static performance Component matching Dynamic performance Time constants, Glitches DAC improvement techniques Symmetrical switching rather than sequential switching Current source self calibration Dynamic element matching Depending of the application, reconstruction filter may be needed EECS 47 Lecture 7: Data Converters 006 H.K. Page 3 Re-Cap Analog Input ADC Converters: Need to build circuits that "sample Need to build circuits for amplitude quantization Analog Preprocessing A/D Conversion DSP D/A Conversion Analog Post processing Analog Output Anti-Aliasing Filter Sampling +Quantization 000...00... 0 "Bits to Staircase" Reconstruction Filter EECS 47 Lecture 7: Data Converters 006 H.K. Page 3
MOS Sampling Circuits EECS 47 Lecture 7: Data Converters 006 H.K. Page 33 Ideal Sampling In an ideal world, zero resistance sampling switches would close for the briefest instant to sample a continuous voltage v IN onto the capacitor C v IN φ S C v OUT Output Dirac-like pulses with amplitude equal to V IN at the time of sampling φ In practice not realizable! T=/f S EECS 47 Lecture 7: Data Converters 006 H.K. Page 34
Ideal T/H Sampling φ v IN S C v OUT φ T=/f S V out tracks input when switch is closed Grab exact value of V in when switch opens "Track and Hold" (T/H) (often called Sample & Hold!) EECS 47 Lecture 7: Data Converters 006 H.K. Page 35 Ideal T/H Sampling Continuous Time time T/H signal (Sampled-Data Signal) Clock Discrete-Time Signal EECS 47 Lecture 7: Data Converters 006 H.K. Page 36
Practical Sampling Issues φ v IN M C v OUT Switch induced noise power due to M finite channel resistance Finite R sw limited bandwidth finite acquisition time R sw = f(v in ) distortion Switch charge injection & clock feedthrough Clock jitter EECS 47 Lecture 7: Data Converters 006 H.K. Page 37 kt/c Noise φ 4kTRΔf v IN M C v OUT v IN R S C v OUT Switch resistance & sampling capacitor form a low-pass filter Noise associated with the switch resistance results in Total noise variance= kt/c @ the output (see noise analysis in Lecture ) In high resolution ADCs kt/c noise often dominates overall error (power dissipation considerations). EECS 47 Lecture 7: Data Converters 006 H.K. Page 38
Sampling Network kt/c Noise For ADCs usually sampling capacitor size is chosen based on having thermal noise smaller or equal to quantization noise: B k BT Δ C kbt C VFS Required C min as a Function of ADC Resolution B 8 4 6 0 C min (V FS = V) 0.003 pf 0.8 pf 3 pf 06 pf 5,800 pf For high resolution ADCs oversampling results in reduction of required value for C (will cover in oversampled converter lectures) EECS 47 Lecture 7: Data Converters 006 H.K. Page 39 Acquisition Bandwidth The resistance R of switch S turns the sampling network into a lowpass filter with finite time constant: τ = RC v IN R φ S C v OUT Assuming V in is constant during the sampling period and C is initially discharged v out ( t) = v in t /τ ( e ) EECS 47 Lecture 7: Data Converters 006 H.K. Page 40
Switch On-Resistance Vin Vout t = <<Δ fs fsτ in V e Worst Case: Vin = V T τ << ln B ( ) FS R << fcln s << Δ B ( ) v IN φ R φ S C v OUT Example: B = 4, C = 3pF, f s = 00MHz T/τ >> 9.4, R << 40Ω T=/f S EECS 47 Lecture 7: Data Converters 006 H.K. Page 4 Switch On-Resistance Switch MOS operating in triode mode: W VDS di IDtriode ( ) = μcox VGS VTH VDS, L R dv D( triode) ON DS V 0 DS R R ON ON = = W W μc V V C V V V L L ( ) μ ( ) ox GS th ox DD th in for Ro = W μc V V L Ro = Vin V V DD th ( ) ox DD th EECS 47 Lecture 7: Data Converters 006 H.K. Page 4
Sampling Distortion Simulated 0bit ADC & T/τ = 0 V DD V th = V V FS = V Sampling Switch modeled: v out v in = e τ T V in VDD V th Results in HD=-4dBFS & HD3=-5.4dBFS EECS 47 Lecture 7: Data Converters 006 H.K. Page 43 Doubling sampling time (or ½ time constant) Results in: HD improved from -4dBFS to -70dBFS ~30dB HD3 improved from - 5.4dBFS to -76.3dBFS ~5dB Sampling Distortion Allowing enough time for the sampling network settling Reduces distortion due to switch R non-linear behavior 0bit ADC T/τ = 0 V DD V th = V V FS = V EECS 47 Lecture 7: Data Converters 006 H.K. Page 44
Sampling Distortion SFDR sensitive to sampling distortion Solutions: Overdesign Larger switches Increased switch charge injection Increased switch drain & source C Complementary switch Maximize V DD /V FS Decreased dynamic range Constant V GS f(v in ) 0bit ADC T/τ = 0 V DD V th = V V FS = V EECS 47 Lecture 7: Data Converters 006 H.K. Page 45 kt/c noise B C kbt VFS Sampling Practical Considerations Finite R sw limited bandwidth R << fcln s B ( ) g sw = f(v in ) distortion Vin W g = g for g μc V V VDD V = th L ( ) ON o o ox DD th Switch charge injection Clock jitter v IN φ M v OUT C EECS 47 Lecture 7: Data Converters 006 H.K. Page 46
Sampling Distortion Effect of Supply Voltage 0bit ADC & T/τ = 0 V DD V th = V V FS = V Effect of lower supply voltage on sampling distortion HD3 increases by (V DD /V DD ) HD increases by (V DD /V DD ) 0bit ADC & T/τ = 0 V DD V th = 4V V FS = V EECS 47 Lecture 7: Data Converters 006 H.K. Page 47 Sampling Distortion SFDR sensitive to sampling distortion - improve linearity by: Larger VDD Higher sampling bandwidth Solutions: Overdesign Larger switches Increased switch charge injection Increased nonlinear S &D junction cap. Maximize VDD/VFS Decreased dynamic range if VDD const. Complementary switch Constant & max. V GS f(v in ) 0bit ADC T/τ = 0 V DD V th = V V FS = V EECS 47 Lecture 7: Data Converters 006 H.K. Page 48
kt/c noise B C kbt VFS R << fcln Practical Sampling Summary So Far! Finite R sw limited bandwidth s B ( ) g sw = f(v in ) distortion Vin W g = g for g μc V V VDD V = th L ( ) ON o o ox DD th Switch charge injection Clock jitter v IN φ M v OUT C EECS 47 Lecture 7: Data Converters 006 H.K. Page 49 Complementary Switch φ g o g n o g o T =g on + g o p φ B g o p φ φ B Complementary n & p switch advantages: Increases the overall conductance Linearize the switch conductance for the range Vtp< Vin <Vdd-Vtn EECS 47 Lecture 7: Data Converters 006 H.K. Page 50
Complementary Switch φ g o g n o g o T =g on + g o p φ B g o p φ φ B Complementary n & p switch advantages: Increase in the overall conductance Linearize the switch conductance for the range V thp < Vin < Vdd - V thn EECS 47 Lecture 7: Data Converters 006 H.K. Page 5 Complementary Switch Issues Supply Voltage Evolution Supply voltage scales down with technology scaling Threshold voltages do not scale accordingly Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp. 599. EECS 47 Lecture 7: Data Converters 006 H.K. Page 5
Complementary Switch Effect of Supply Voltage Scaling g effective g o n g o T =go n + g o p φ g o p φ B φ φ B As supply voltage scales down input voltage range for constant g o shrinks Complementary switch not effective when V DD becomes comparable to V th EECS 47 Lecture 7: Data Converters 006 H.K. Page 53 Boosted & Constant V GS Sampling V GS =const. OFF ON Gate voltage V GS =low Device off Beware of signal feedthrough due to parasitic capacitors Increase gate overdrive voltage as much as possible + keep V GS constant Switch overdrive voltage independent of signal level Error due to finite R ON linear (to st order) Lower R on lower time constant EECS 47 Lecture 7: Data Converters 006 H.K. Page 54
Constant V GS Sampling (= voltage @ the switch input terminal) EECS 47 Lecture 7: Data Converters 006 H.K. Page 55 Constant V GS Sampling Circuit VDD=3V P_N M M M3 M8 M6 VP 00ns P C PB C C3 M P M4 M5 M9 VS.5V MHz Va Vg M Vb Chold Sampling switch & C This Example: All device sizes:0μ/0.35μ All capacitor size: pf (except for Chold) EECS 47 Lecture 7: Data Converters 006 H.K. Page 56
VDD=0 3V M 0ff C PB 0 3V Clock Voltage Doubler C 0 0 M Saturation mode 0 3V 0 (3V-V th M ) M Triode VDD=3V M off 3V 0 3V (3V-V th M ) (6V-V th M ) Acquire charge C C PB 3V 0 0 3V P P VP 0 3V VP 3V 0 a) Start up b) Next clock phase EECS 47 Lecture 7: Data Converters 006 H.K. Page 57 Clock Voltage Doubler M 0ff 3V ~6V VDD=3V C PB 0 3V M 3V 0 M Triode (6V-V M th ) (3V-V M th ) ~ 3V Acquires C charge Both C & C charged to VDD after one clock cycle P VP 0 3V c) Next clock phase EECS 47 Lecture 7: Data Converters 006 H.K. Page 58
Clock Voltage Doubler VDD=3V VDD M M P_Boost R R VDD C C PB P 0 VP Clock period: 00ns *R & R=GOhm dummy resistors added for simulation only EECS 47 Lecture 7: Data Converters 006 H.K. Page 59 Constant V GS Sampler: Φ LOW VDD=3V ~ VDD (boosted clock) M3 Triode OFF VDD C3 M4 Sampling switch M is OFF VDD M Triode Input voltage source OFF M OFF VS.5V MHz Chold pf Device OFF C3 charged to VDD EECS 47 Lecture 7: Data Converters 006 H.K. Page 60
Constant V GS Sampler: Φ HIGH M8 C3 previously charged to VDD VDD C3 pf M9 VS.5V MHz M Chold pf M8 & M9 are on: C3 across G-S of M M on with constant VGS = VDD EECS 47 Lecture 7: Data Converters 006 H.K. Page 6 Constant V GS Sampling Input Switch V Gate Chold Signal Input Signal EECS 47 Lecture 7: Data Converters 006 H.K. Page 6
Complete Circuit Clock Multiplier M7 & M3 for reliability Remaining issues: -V GS constant only for V in <V out -Nonlinearity due to Vth dependence of Mon bodysource voltage Ref: A. Abo et al, A.5-V, 0-bit, 4.3-MS/s CMOS Pipeline Analog-to-Digital Converter, JSSC May 999, pp. 599. Switch EECS 47 Lecture 7: Data Converters 006 H.K. Page 63 Constant Conductance Switch Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 769-780, Dec. 000 EECS 47 Lecture 7: Data Converters 006 H.K. Page 64
Constant Conductance Switch OFF Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 769-780, Dec. 000 EECS 47 Lecture 7: Data Converters 006 H.K. Page 65 Constant Conductance Switch M Constant current constant g ds M replica of M & same VGS as M M also constant g ds ON * Note: Authors report a requirement of 80MHz GBW for the opamp for bit 50Ms/s ADC Ref: H. Pan et al., "A 3.3-V -b 50-MS/s A/D converter in 0.6um CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, pp. 769-780, Dec. 000 EECS 47 Lecture 7: Data Converters 006 H.K. Page 66
Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch EECS 47 Lecture 7: Data Converters 006 H.K. Page 67 Advanced Clock Boosting Technique clk low Sampling Switch clk low Capacitors Ca & Cb charged to VDD MS off Hold mode EECS 47 Lecture 7: Data Converters 006 H.K. Page 68
Advanced Clock Boosting Technique clk high Sampling Switch clk high Top plate of Ca & Cb connected to gate of sampling switch Bottom plate of Ca connected to V IN Bottom plate of Cb connected to V OUT VGS & VGD of MS both @ VDD & ac signal on G of MS average of V IN & V OUT EECS 47 Lecture 7: Data Converters 006 H.K. Page 69 Advanced Clock Boosting Technique Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IFsampling frontend," ISSCC 00, Dig. Tech. Papers, pp. 34 Sampling Switch Gate tracks average of input and output, reduces effect of I R drop at high frequencies Bulk also tracks signal reduced body effect (technology used allows connecting bulk to S) Reported measured SFDR = 76.5dB at f in =00MHz EECS 47 Lecture 7: Data Converters 006 H.K. Page 70
Switch Off-Mode Feedthrough Cancellation Ref: M. Waltari et al., "A self-calibrated pipeline ADC with 00MHz IF-sampling frontend," ISSCC 00, Dig. Techn. Papers, pp. 34 EECS 47 Lecture 7: Data Converters 006 H.K. Page 7