Advanced Process Technoogy Utra Low On-Resistance Dynamic dv/dt Rating 175 C Operating Temperature Fast Switching Fuy Avaanche Rated Lead-Free Description Advanced HEXFET Power MOSFETs from Internationa Rectifier utiize advanced processing techniques to achieve extremey ow on-resistance per siicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET power MOSFETs are we known for, provides the designer with an extremey efficient and reiabe device for use in a wide variety of appications. G IRFR3411PbF IRFU3411PbF HEXFET Power MOSFET D S PD - 95371B V DSS = V R DS(on) = 44mΩ I D = 32A The D-Pak is designed for surface mounting using vapor phase, infrared, or wave sodering techniques. The straight ead, I-Pak, version (IRFU series) is for throughhoe mounting appications. Power dissipation eves up to 1.5 watts are possibe in typica surface mount appications. Absoute Maximum Ratings D-Pak IRFR3411PbF I-Pak IRFU3411PbF Parameter Max. Units I D @ T C = 25 C Continuous Drain Current, @ V 32 I D @ T C = C Continuous Drain Current, @ V 23 A I DM Pused Drain Current 1 P D @T C = 25 C Power Dissipation 130 W Linear Derating Factor 0.83 W/ C Gate-to-Source Votage ± 20 V I AR Avaanche Current 16 A E AR Repetitive Avaanche Energy 13 mj dv/dt Peak Diode Recovery dv/dt ƒ 7.0 V/ns T J Operating Junction and -55 to 175 T STG Storage Temperature Range Sodering Temperature, for seconds 300 (1.6mm from case ) C Therma Resistance Parameter Typ. Max. Units R θjc Junction-to-Case 1.2 R θja Junction-to-Ambient (PCB mount)* 50 C/W R θja Junction-to-Ambient 1 www.irf.com 1 09/16/
Eectrica Characteristics @ T J = 25 C (uness otherwise specified) Parameter Min. Typ. Max. Units Conditions V (BR)DSS Drain-to-Source Breakdown Votage V = 0V, I D = 250µA V (BR)DSS/ T J Breakdown Votage Temp. Coefficient 0.12 V/ C Reference to 25 C, I D = 1mA R DS(on) Static Drain-to-Source On-Resistance 36 44 mω = V, I D = 16A (th) Gate Threshod Votage 2.0 4.0 V V DS =, I D = 250µA g fs Forward Transconductance 21 S V DS = 50V, I D = 16A I DSS Drain-to-Source Leakage Current 25 V µa DS = V, = 0V 250 V DS = 80V, = 0V, T J = 150 C I GSS Gate-to-Source Forward Leakage = 20V na Gate-to-Source Reverse Leakage - = -20V Q g Tota Gate Charge 48 71 I D = 16A Q gs Gate-to-Source Charge 9.0 14 nc V DS = 80V Q gd Gate-to-Drain ("Mier") Charge 14 21 = V, See Fig. 6 and 13 t d(on) Turn-On Deay Time 11 V DD = 50V t r Rise Time 35 I D = 16A ns t d(off) Turn-Off Deay Time 39 R G = 5.1Ω t f Fa Time 35 = V, See Fig. Between ead, L D Interna Drain Inductance 4.5 6mm (0.25in.) nh G from package L S Interna Source Inductance 7.5 and center of die contact C iss Input Capacitance 1960 = 0V C oss Output Capacitance 250 V DS = 25V C rss Reverse Transfer Capacitance 40 pf ƒ = 1.0MHz, See Fig. 5 E AS Singe Puse Avaanche Energy 700 185 mj I AS = 16A, L = 1.5mH D S Source-Drain Ratings and Characteristics Parameter Min. Typ. Max. Units Conditions D I S Continuous Source Current MOSFET symbo 33 (Body Diode) showing the A G I SM Pused Source Current integra reverse 1 (Body Diode) p-n junction diode. S V SD Diode Forward Votage 1.2 V T J = 25 C, I S = 16A, = 0V t rr Reverse Recovery Time 115 170 ns T J = 25 C, I F = 16A Q rr Reverse Recovery Charge 505 760 nc di/dt = A/µs t on Forward Turn-On Time Intrinsic turn-on time is negigibe (turn-on is dominated by L S L D ) Notes: Repetitive rating; puse width imited by max. junction temperature. (See fig. 11) Starting T J = 25 C, L =1.5mH R G = 25Ω, I AS = 16A. (See Figure 12) ƒ I SD 16A, di/dt 340A/µs, V DD V (BR)DSS, T J 175 C. Puse width 400µs; duty cyce 2%. This is a typica vaue at device destruction and represents operation outside rated imits. This is a cacuated vaue imited to T J = 175 C. * When mounted on 1" square PCB (FR-4 or G- Materia). For recommended footprint dering techniques refer to appication note #AN-994. 2 www.irf.com
I D, Drain-to-Source Current (A) VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V I D, Drain-to-Source Current (A) VGS TOP 15V V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V 4.5V 20µs PULSE WIDTH 1 T J = 25 C 0.1 1 V DS, Drain-to-Source Votage (V) 20µs PULSE WIDTH 1 T J = 175 C 0.1 1 V DS, Drain-to-Source Votage (V) Fig 1. Typica Output Characteristics Fig 2. Typica Output Characteristics I D, Drain-to-Source Current (A) T J = 25 C T J = 175 C V DS= 50V 20µs PULSE WIDTH 4.0 5.0 6.0 7.0 8.0 9.0, Gate-to-Source Votage (V) R DS(on), Drain-to-Source On Resistance (Normaized) 3.5 I D = 33A 3.0 2.5 2.0 1.5 1.0 0.5 = V 0.0-60 -40-20 0 20 40 60 80 120 140 160 180 T J, Junction Temperature ( C) Fig 3. Typica Transfer Characteristics Fig 4. Normaized On-Resistance Vs. Temperature www.irf.com 3
I D, Drain-to-Source Current (A) C, Capacitance (pf) 3000 VGS = 0V, f = 1MHz Ciss = Cgs Cgd, C ds SHORTED C = 2500 rss Cgd Coss = Cds Cgd C 2000 iss 1500 C oss 500 C rss 0 1 V DS, Drain-to-Source Votage (V), Gate-to-Source Votage (V) 20 16 12 8 4 I = D 16A V DS = 80V V DS = 50V V DS = 20V FOR TEST CIRCUIT SEE FIGURE 13 0 0 20 40 60 80 Q G, Tota Gate Charge (nc) Fig 5. Typica Capacitance Vs. Drain-to-Source Votage Fig 6. Typica Gate Charge Vs. Gate-to-Source Votage I SD, Reverse Drain Current (A) 1 T J = 175 C T J = 25 C = 0 V 0.1 0.2 0.6 1.0 1.4 1.8 V SD,Source-to-Drain Votage (V) 1 0.1 T A = 25 C T J = 175 C Singe Puse OPERATION IN THIS AREA LIMITED BY R DS (on) µsec 1msec msec 1 V DS, Drain-toSource Votage (V) Fig 7. Typica Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Votage 4 www.irf.com
35 V DS R D 30 25 R G D.U.T. - V DD I D, Drain Current (A) 20 15 5 0 25 50 75 125 150 175 T, Case Temperature ( C C) Fig 9. Maximum Drain Current Vs. Case Temperature V DS 90% Puse Width 1 µs Duty Factor 0.1 % Fig a. Switching Time Test Circuit % t d(on) t r t d(off) t f Fig b. Switching Time Waveforms Therma Response (Z thjc ) 1 0.1 D = 0.50 0.20 0. 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t 1 t 2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thjc T C 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t 1, Rectanguar Puse Duration (sec) Fig 11. Maximum Effective Transient Therma Impedance, Junction-to-Case www.irf.com 5
15V V DS L DRIVER R G D.U.T IAS - V DD A 20V tp 0.01Ω Fig 12a. Uncamped Inductive Test Circuit V (BR)DSS tp E AS, Singe Puse Avaanche Energy (mj) 400 300 200 I D TOP 6.5A 11.3A BOTTOM 16A 0 25 50 75 125 150 175 Starting T, Junction Temperature ( J C) Fig 12c. Maximum Avaanche Energy Vs. Drain Current I AS Fig 12b. Uncamped Inductive Waveforms Current Reguator Same Type as D.U.T. 50KΩ Q G 12V.2µF.3µF Q GS Q GD D.U.T. V - DS V G 3mA Charge Fig 13a. Basic Gate Charge Waveform I G I D Current Samping Resistors Fig 13b. Gate Charge Test Circuit 6 www.irf.com
Peak Diode Recovery dv/dt Test Circuit D.U.T* ƒ - Circuit Layout Considerations Low Stray Inductance Ground Pane Low Leakage Inductance Current Transformer - - R G dv/dt controed by R G I SD controed by Duty Factor "D" D.U.T. - Device Under Test - V DD * Reverse Poarity of D.U.T for P-Channe Driver Gate Drive Period P.W. D = P.W. Period [ =V ] *** D.U.T. I SD Waveform Reverse Recovery Current Re-Appied Votage Body Diode Forward Current di/dt D.U.T. V DS Waveform Diode Recovery dv/dt Inductor Curent Body Diode Rippe 5% Forward Drop [ V DD ] [ ] I SD *** = 5.0V for Logic Leve and 3V Drive Devices Fig 14. For N-channe HEXFET power MOSFETs www.irf.com 7
D-Pak (TO-252AA) Package Outine Dimensions are shown in miimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 AS SEMBLED ON WW 16, 2001 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates "Lead-Free" "P" in assemby ine position indicates "Lead-F ree" quaification to the cons umer-eve INTERNATIONAL RECTIFIER LOGO AS S E MBLY LOT CODE IRFR120 116A 12 34 PART NUMBER DATE CODE YEAR 1 = 2001 WEEK 16 LINE A OR INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFR120 12 34 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) P = DESIGNATES LEAD-FREE PRODUCT QUALIFIED TO THE CONSUMER LEVEL (OPTIONAL) YEAR 1 = 2001 WEEK 16 A = ASSEMBLY SITE CODE Notes: 1. For an Automotive Quaified version of this part pease seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing pease refer to IR website at http://www.irf.com/package/ 8 www.irf.com
I-Pak (TO-251AA) Package Outine Dimensions are shown in miimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: THIS IS AN IRFU120 WITH ASSEMBLY LOT CODE 5678 ASSEMBLED ON WW 19, 2001 IN THE ASSEMBLY LINE "A" Note: "P" in assemby ine position indicates Lead-Free" INTERNATIONAL RECTIFIER LOGO AS S EMBL Y LOT CODE IRFU120 119A 56 78 PART NUMBER DATE CODE YEAR 1 = 2001 WEEK 19 LINE A OR INT ERNATIONAL RECTIFIER LOGO ASSEMBLY LOT CODE IRFU120 56 78 PART NUMBER DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 1 = 2001 WEEK 19 A = ASSEMBLY SITE CODE Notes: 1. For an Automotive Quaified version of this part pease seehttp://www.irf.com/product-info/auto/ 2. For the most current drawing pease refer to IR website at http://www.irf.com/package/ www.irf.com 9
D-Pak (TO-252AA) Tape & Ree Information Dimensions are shown in miimeters (inches) TR TRR TRL 16.3 (.641 ) 15.7 (.619 ) 16.3 (.641 ) 15.7 (.619 ) 12.1 (.476 ) 11.9 (.469 ) FEED DIRECTION 8.1 (.318 ) 7.9 (.312 ) FEED DIRECTION NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541. 13 INCH NOTES : 1. OUTLINE CONFORMS TO EIA-481. 16 mm Data and specifications subject to change without notice. This product has been designed and quaified for the Industria market. Quaification Standards can be found on IR s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., E Segundo, Caifornia 90245, USA Te: (3) 252-75 TAC Fax: (3) 252-7903 Visit us at www.irf.com for saes contact information.09/20 www.irf.com