Digital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders

Similar documents
Encoders. Lecture 23 5

Chapter 3 Combinational Logic Design

(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Unit 3. Logic Design

MSI Design Examples. Designing a circuit that adds three 4-bit numbers

COMBINATIONAL CIRCUIT

CHW 261: Logic Design

TABLE 3-2 Truth Table for Code Converter Example

Combinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations

Digital Electronics. Functions of Combinational Logic

BCD Adder. Lecture 21 1

Solutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature

ICS 151 Final. (Last Name) (First Name)

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

Analog Electronics (Course Code: EE314) Lecture 9 10: BJT Small Signal, Biasing, Amplifiers

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

Gates and Circuits 1

Function Table of 74LS138, 3-to-8 Decoder +5V 6 G1 4 G2A 5 G2B. 4-to-16 Decoder using two 74LS139, 3-to-8 Decoder

Digital Electronics 8. Multiplexer & Demultiplexer

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

EEE 301 Digital Electronics

Gates and and Circuits


Combinational Logic Design CH002

4:Combinational logic circuits. 3 July

University of Technology

UNIT-2: BOOLEAN EXPRESSIONS AND COMBINATIONAL LOGIC CIRCUITS

Function Table of an Odd-Parity Generator Circuit

Experiment # 4. Binary Addition & Subtraction. Eng. Waleed Y. Mousa

UNIT-IV Combinational Logic

COMPUTER TECHNOLOGY 2015/2016 Exercises. Unit 7

Project Part 1 A. The task was to design a 4 to 1 multiplexer that uses 8 bit buses on the inputs with an output of a single 8 bit bus.

Serial Addition. Lecture 29 1

2 Building Blocks. There is often the need to compare two binary values.

In this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions

6.1 In this section, you will design (but NOT build) a circuit with 4 inputs,

Lecture 02: Digital Logic Review

BJT Amplifiers: Overview

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices

Digital Logic Design ELCT 201

Chapter 3 Digital Logic Structures

Combinational Logic Circuits. Combinational Logic

Combinational logic. ! Regular logic: multiplexers, decoders, LUTs and FPGAs. ! Switches, basic logic and truth tables, logic functions

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Binary Addition. Boolean Algebra & Logic Gates. Recap from Monday. CSC 103 September 12, Binary numbers ( 1.1.1) How Computers Work

Department of Electrical and Electronics Engineering Logic Circuits Laboratory EXPERIMENT-5 COMBINATIONAL LOGIC CIRCUITS

7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 4: Combinational Logic Circuits. Name: Date:

Chapter 3 Digital Logic Structures

This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.

Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405

Course Overview. Course Overview

ECE 172 Digital Systems. Chapter 2 Digital Hardware. Herbert G. Mayer, PSU Status 6/30/2018

CSCI "Decoders & Demultiplexers"

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

Combinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science

Topic Notes: Digital Logic

Lecture 3: Logic circuit. Combinational circuit and sequential circuit

Reference. Wayne Wolf, FPGA-Based System Design Pearson Education, N Krishna Prakash,, Amrita School of Engineering

Logic Design I (17.341) Fall Lecture Outline

UNIT III. Designing Combinatorial Circuits. Adders

LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.

Digital Fundamentals

ECE COMBINATIONAL BUILDING BLOCKS - INVEST 14 DATA TRANSFER

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

Lab 2: Combinational Circuits Design

In this lecture: Lecture 8: ROM & Programmable Logic Devices

Positive and Negative Logic

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)

Logic Circuit Design

Laboratory Manual CS (P) Digital Systems Lab

(a) (b) (c) (d) (e) (a) (b) (c) (d) (e)

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

Chapter 4: The Building Blocks: Binary Numbers, Boolean Logic, and Gates

Digital Electronic Concepts

Logic diagram: a graphical representation of a circuit

Programmable Logic Arrays (PLAs)

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON

GUJARAT TECHNOLOGICAL UNIVERSITY, AHMEDABAD, GUJARAT COURSE CURRICULUM. Course Title: Digital Electronics (Code: )

ELEC1 (JUN13ELEC101) General Certificate of Education Advanced Subsidiary Examination June Introductory Electronics TOTAL. Time allowed 1 hour

Integrated Circuit Technology (Course Code: EE662) Lecture 1: Introduction

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

The book has excellent descrip/ons of this topic. Please read the book before watching this lecture. The reading assignment is on the website.

Programmable Logic Arrays (PLAs)

Overview. This lab exercise requires. A windows computer running Xilinx WebPack A Digilent board. Contains material Digilent, Inc.

DIGITAL LOGIC CIRCUITS

7.1. Unit 7. Fundamental Digital Building Blocks: Decoders & Multiplexers

Large Signal Model for Saturation Mode

Subtractor Logic Schematic

CS302 - Digital Logic Design Glossary By

SKP Engineering College

Exercise 1: AND/NAND Logic Functions

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Lecture 2: Digital Logic Basis

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1

Transcription:

Indian Institute of Technology Jodhpur, Year 28 29 Digital Logic and Design (Course Code: EE222) Lecture 4: Combinational Contd.. Decoders/Encoders Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in Webpage: http://home.iitj.ac.in/~sptiwari/ / / Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/dld/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only Decoders/Encoders Binary decoders Converts an n-bit code to a single active output Can be developed using AND/OR gates Can be used to implement logic circuits. Binary encoders Converts one of 2 n inputs to an n-bit output Useful for compressing data Can be developed using AND/OR gates Both encoders and decoders are extensively used in digital systems

Binary Decoder Black box with n input lines and 2 n output lines Only one output is a for any given input n inputs Binary Decoder 2 n outputs 2-to-4 Binary Decoder Truth Table: X Y F F F 2 F 3 F = X'Y' F = X'Y From truth table, circuit for 2x4 decoder is: Note: Each output is a 2- variable minterm (X'Y', X'Y, XY' or XY) F 2 = XY' F 3 = XY X Y 2-to-4 Decoder F F F2 F3 X Y 2

3-to-8 Binary Decoder Truth Table: x y z F F F 2 F 3 F 4 F 5 F 6 F 7 F = x'y'z' F = x'y'z F 2 =x'yz' xyz F 3 = x'yz F 4 = xy'z' F 5 = xy'z F 6 = xyz' X Y Z 3-to-8 Decoder F F F2 F3 F4 F5 F6 x y z F 7 =xyz F7 Implementing Functions Using Decoders Any n-variable logic function can be implemented using a single n-to-2 n decoder to generate the minterms OR gate forms the sum. The output lines of the decoder corresponding to the minterms of the function are used as inputs to the or gate. Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates. Suitable when a circuit has many outputs, and each output function is expressed with few minterms. 3

Implementing Functions Using Decoders F = m(,2) Implementing Functions Using Decoders Exercise: Design a circuit, using a 3-to-8 Decoder to realize the Boolean expression given below. F X,Y,Z = m(,2,5,7) 4

Implementing Functions Using Decoders Exercise: Design a Full Adder using a 3-to-8 Decoder. Implementing Functions Using Decoders Example: Full adder S(x, y, z) = (,2,4,7) C(x, y, z) = (3,5,6,7) x y z C S x y z 3-to-8 Decoder S 2 S S 2 3 4 5 6 7 S C 5

Building a Binary Decoder with NAND Gates Start with a 2-bit decoder Add an enable signal (E) Note: use of NANDs only one active! if E = Use two 3 to 8 decoders to make 4 to 6 decoder Enable can also be active high In this example, only one decoder can be active at a time. x, y, z effectively select output line for w 6

Encoders If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. e.g. 2 n -to-n The simplest encoder is a 2 n -to-n binary encoder One of 2 n inputs = Output is an n-bit binary number 2 n inputs... Binary encoder... n outputs 4-to-2 Binary Encoder At any one time, only one input line has a value of. w 3 w 2 w w y y w w y w 2 w 3 y 7

8-to-3 Binary Encoder At any one time, only one input line has a value of. I Inputs Outputs I I I 2 I 3 I 4 I 5 I 6 I 7 y 2 y y I I 2 y 2 = I 4 + I 5 + I 6 + I 7 I 3 y = I 2 + I 3 + I 6 + I 7 I 4 I 5 I 6 I 7 y = I + I 3 + I 5 + I 7 Priority Encoder Higher-order input has priority of lower-order input Order of the input determined by its binary value I has binary value () I has binary value () I2 has binary value (2) I3 has binary value (3) etc. So, I selected over I I2 selected over I and I I3 selected over I2, I, and I Etc. 8

Priority Encoder Valid indicator Output signal of the (priority) encoder that indicates the validity of the encoded output Encoded output is invalid when no inputs are selected or when the encoder is disabled V = (indicates invalid encoded output; active high) Encoded output when one, or more, input(s) is (are) selected, and encoder is enabled V = (indicates valid encoded output; active high) 4-to-2 Priority Encoder Valid indicator invalid valid 9

Priority Encoder 4-to-2 Priority Encoder

8-to-3 Priority Encoder What if more than one input line has a value of? Ignore lower priority inputs. Idle indicates that no input is a. Note that polarity of Idle is opposite from Table 4-8 in Mano Inputs Outputs I I I 2 I 3 I 4 I 5 I 6 I 7 y 2 y y Idle x x x X X X X X X X X X X X X X X X X X X X X X X X X X X X X Encoder Application (Monitoring Unit) Encoder identifies the requester and encodes the value Controller accepts digital inputs. Alarm Signal Contoller Response Machine Machine 2 Encoder Machine Code Controller Action Machine n

Multiplexers A multiplexer switches (or routes) data from 2 N inputs to one output, where N is the number of select (or control) inputs. A multiplexer (mux) is a digital switch. Multiplexers What next 24 2