The Layout Implementations of High-Speed Low-Power Sequential Logic Cells Based on MOS Current-Mode Logic

The Layout mplementations of High-Speed Low-Power Sequential Logic Cells Based on MOS Current-Mode Logic 1 Ni Haiyan, 2 Li Zhenli *1,Corresponding Author Ningbo University, nbuhjp@yahoo.cn 2 Ningbo University, nbuli@yahoo.com.cn Abstract MOS Current-Mode Logic (MCML) is usually used for high-speed applications. n this paper, the design method of the high-speed low-power MCML is addressed. The layout implementations of MCML D-Flip flop cells are presented at a NCSU FreePDK 45nm technology. A mod-10 counter based on the proposed D-Flip flop cells is implemented to verify the efficiency of the proposed design method. The post-layout simulations are carried out. For normal supply voltage, the MCML sequential logic circuit can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Scaling down the supply voltage of MCML circuits is investigated. The results show that the power consumption of MCML circuits can be reduced by lowering the supply voltage without performance degrading. Keywords: MOS current mode logic, near-threshold, low voltage, low power, flip flop, high-speed applications 1. ntroduction With the growing uses of portable and wireless electronic systems, energy-efficient designs have become more and more important in integrated circuits [1, 2]. MOS current mode logic (MCML) techniques could be used to realize high-speed circuits, and thus it is usually used for high-speed applications such as high-speed processors and Gbps multiplexers for optical transceivers [3, 4]. The circuits designed with the MCML techniques can operate over a wide range of frequencies. Another interesting advantage of this technique is that their speed and power consumption can be simply adjusted by altering the bias current of the gates without the need for resizing the devices. MCML has large static power consumption due to its constant operation current. Therefore, the power dissipation of MCML circuits is much larger than the conventional CMOS ones at low operating frequencies. Recently, the low power MCML designs have obtained some attentions. P. Heydari and G. Caruso presented the methodologies for the low-power design of MCML-based buffer chain and ring oscillators, respectively [5, 6]. M. H. Anis et al. proposed the multi-threshold MCML (MTMCML) technology that allows the reduction of the minimum supply voltage of the two-level MCML circuits, hence reduces the power dissipations of the MCML circuits [7]. However the analysis presented in [7] for MTMCML was based on inaccurate long-channel modeling equations, which is inappropriate for today s nanometer CMOS technologies. n [8], J. Beom et al. presented a low-power MOS current mode logic circuit with sleep-transistor to reduce the leakage current with 0.35mm process, but the parameters need redesign for the adaption to nowadays nanometer process. F. Cannillo et al. presented low power MCML circuits with a sub-threshold configuration and achieved significant reductions in power dissipation [9-10], but the degraded performance of the sub-threshold MCML is not suitable the mainstream applications today. n this work, we proposed a near-threshold design for high-speed low-power sequential logic circuit. This paper is organized as follows. n section 2, the basic MCML inverter/buffer, MCML design by using binary decision diagram method, and power and delay analysis for MCML circuits are reviewed. n section 3, the MCML circuits for near-threshold operating is introduced, and the minimum operating supply voltage for MCML circuits analyzed in detail. The layout implementations of MCML D-latches and D-Flip flops (DFF) with a NCSU FreePDK 45nm technology is given in section 4. The experimental results of near-threshold computing for a mod-10 counter based on the proposed MCML flip flop cells is are presented in section 5. Finally, our work of this paper is summarized in the last section. Journal of Convergence nformation Technology(JCT) Volume7, Number10, June 2012 doi:10.4156/jcit.vol7.issue10.1 1

2. Review of MCML circuits The basic MCML inverter/buffer and its bias circuit are shown in Fig. 1, and the operation waveforms are shown in Fig. 2. The MCML inverter is composed of three main parts: the load transistors P1 and P2, the full differential pull down switch network consisting of N1 and N2, and the current source transistor Ns. The load transistors are designed to operate at linear region with the auxiliary of the control voltage Vref produced by the bias circuit, which also controls the output logic swings [11]. The pull-down network (PDN) NMOS N1 and N2 are used to perform logic operation. The NMOS Ns is used to provide the constant current source, which is mirrored from the current source in the bias circuit. n the MCML, the two signals Vrfp and Vrfn are generated from the bias circuit to ensure the proper operating for output voltage swings and to provide the constant bias current. V DD V DD Vx + - Vrfp V DD P1 P2 OUTb OUT N N1 N2 Nb Vrfn Ns Bias Circuit Figure 1. MCML inverter/buffer and its bias circuit. The operation of MCML circuits is performed in the current domain. The pull down network switches the constant current between two branches in the control of input signals, and then the load converts the current to output voltage swings. The high and low digital logic levels are V OH = V DD and V OL = V DD - B R D, respectively, where R D is the PMOS load resistance. The logic swing is ΔV = V OH - V OL = B R D. Figure 2. The operation waveforms of the MCML inverter/buffer. MCML is a type of differential logic circuit with dual-terminal input and dual-terminal output ports like DCVSL and DSL [12, 13]. n general, differential circuits have much higher noise immunity and are inherently faster than their CMOS counterparts at the cost of larger area. The core of the differential logic cell is the PDN logic tree. When designing the topology structure of the MCML complicated gates or functional circuits, a binary decision diagram (BDD) [14] method is always used to represent 2

and simply the MCML circuit, whose PDN logic tree can be represented using BDD where each node is a differential pair and each branch is a connection between one drain and the source of another differential pair or an output [13]. The square 0 and 1 nodes represent the complementary outputs of the MCML gate. BDD is a very practical way to capture the behavior of the MCML, and furthermore, it can help to simplify the logic tree of the MCML. Fig. 3 shows the original and the simplified BDD, and the schematic view of a positive MCML D-latch, which is an important basic cell in sequential logic circuit. Clk Clk V DD 0 1 0 1 Vrfp Qb Q D D Q D D Db 0 1 0 0 1 1 Clkb Clk Q 0 1 0 1 Vrfn (a) (b) (c) Figure 3.(a) Original BDD, (b) Simplified BDD, and (c) Schematic view of the positive MCML D- latch. The optimization performance metrics of the MCML cells mainly include propagation delay, power dissipation, and power-delay product [15-17]. Due to the operating constant current whenever it is either in activate mode or in standby mode, the power consumption of a MCML cell is independent of the switching frequency, and it can been written as P N V DD B (1) where N is the number of basic parts in a MCML circuit, V DD is the supply voltage, and B is the bias current of the MCML cell. From (1), the power dissipation of MCML circuit can be reduced by using near-threshold techniques. The delay time of a MCML cell can be calculated assuming that, at each transition, the whole B, ideally, flows through one branch of the differential pair and charges the total load capacitance C, is given by Eq.2 t 0.69 RC 0.69C V / (2) d B Where B is the operating constant current, R is the equivalent resistance of one branch of the load PMOS transistor, C is identical load capacitance on an output node, and ΔV is the output voltage swing that is generated from the bias circuit. The power-delay product is independent of the switching frequency and can be calculated as PDP P t N 0. 69V V C (3) d For given V DD and B, the power dissipation of MCML cells is a constant value. t is independent of both the operation frequencies and fan-outs. Therefore, the power dissipation of MCML cells is also independent of the logic function. The power dissipation of conventional CMOS circuits can be expressed as DD P fv 2 DD C L (4) where f is operation frequency of conventional CMOS circuits, and C L is load capacitance of conventional CMOS circuits. The power dissipation of CMOS circuits depends on the operation 3

frequency linearly. Therefore, there exists a cross-frequency, above which MCML circuits is more power efficient than conventional CMOS counterparts. t is importance to estimating the crossfrequency for effectively using MCML circuits from the power point of view. There is a simple method to estimate the cross-frequency according to the power dissipations of the MCML and conventional CMOS gates. When P CMOS =P MCML, the cross-frequency f c can be derived as f / V C (5) c B DD L t is assumed that the MCML and conventional CMOS circuits operate in the same supply voltage. According to Eq. (5), the cross-frequency f c can be estimated. The power dissipation and power-delay product can be optimized from Eq. (1) to Eq. (3). An optimization has been carried out for the proposed cells at the NCSU FreePDK 45nm technology. 3. Near-threshold configuration Power consumption is a key factor of limiting circuit performance. n MCML circuits, the static power consumption is very large proportion, and dynamic power consumption is relatively small, almost negligible [6]. The static power dissipation of the MCML circuits is expressed as P=V DD B, where V DD is the supply voltage and B is the current flowing through the constant current source. Therefore, the power dissipation of the MCML circuits can be reduced by lowering either V DD or B. Reducing B would results in the increase of delay time. Therefore, reducing the supply voltage is an effective method to lower the power consumption of the MCML circuits. The literature [18] presented some current mode logic circuits operating at sub-threshold regime and obtained very small power consumption. However, these sub-threshold MCML circuits can only work at very low frequencies from 1KHz to 100KHz. n the sub-threshold MCML circuits, the performance is limited due to the exponential relationship between delay and supply voltage, and the rising leakage power in a near-exponential fashion. Scaling supply voltage to sub-threshold region only suits for ultra-low operation frequencies. Moreover, the robustness of sub-threshold logic circuits must carefully be considered, since their operation relies only on leakage currents that are exponentially dependent on V TH and are therefore more sensitive to process variation than traditional super-threshold designs [19]. Recently, the near-threshold computing is presented [19, 20]. The supply voltage of near-threshold circuits is slightly above the threshold voltage of the transistors. The MCML circuit with nearthreshold configuration, where the transistors are operating at moderate regime, is a merging approach to obtain lower power dissipation than the nominal voltage supply configuration. The near-threshold MCML circuits can achieve higher performance than sub-threshold configuration. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived in [19]. This region retains much of the energy savings of sub-threshold operation with more favorable performance and variability characteristics [20]. This makes it applicable to a broad range of power-constrained computing segments from wireless sensors, biomedical applications to high performance servers. n order to get the most efficient point of the near-threshold MCML circuit, the minimum supply voltage should be estimated. The minimum operating supply voltage for an MCML circuit is defined as the lowest voltage at which the differential pairs as well as the current source are made to operate in the uration region to ensure correct functionality and adequate performance [19]. The V min of MCML universal logic gate, shown in Fig. 1, can be expressed as V min V V V (6) ds1, dss, n the configuration, the minimum operation voltage of the MCML gate is about 0.7V according to the Eq. (7) derived in [18]. gs3 V min 2W C V 1 th3 OX 2W C 3 OX 4E 1 1 W1L 1C OX 4E 1 1 2Ws COX W3L3C OX 4E 1 WsLsC OX 1 (7) 4

4. MCML sequential logic circuits For the convenient of observing the performance of the MCML circuits, a compact MCML cell library based on NCSU FreePDK45nm technology library [22] is presented, in which the Master-Slave DFFs with driving strength of X1 and X2 and the corresponding ones with reset terminal are implemented using Cadence Virtuosuo C design tools. The schematic view are all captured and the full-custom layout views are all drawn, from which full netlists with parasitic parameters is extracted. The schematic and the full-custom layout view of the basic DFF cell with X1 drive strength is shown in Fig. 4. The DFF is composed of two D type latch designed using BDD method mentioned previously. Fig. 5 shows the layout view of MCML DFF. n the layout deigns, the metal lines are placed horizontally at the top and the bottom that are used for the power supply (VDD) and ground (VSS), respectively. The inputs and outputs are placed in the middle. All gates have the same height. This allows fast and regular design for large circuit blocks. Fig. 6 shows the C 2 MOS positive edge-triggered DFF cell extracted from the NCSU FreePDK45 osu_soc standard cell library and Nangate Open standard cell library, which is used for comparing with the proposed MCML flip flop. The C 2 MOS (clocked CMOS) logic is widely used in the standard cell libraries of various process technologies nodes due to its lower overhead than the CMOS counterparts [23]. Figure 4. Schematic of the Master-Slave positive edge-triggered MCML D flip flop. Figure 5. The layout view of master-slave positive edge-triggered MCML D-Flip flop. 5

5. Simulation results Figure 6. The C 2 MOS master-slave D flip flop based on transmission gate. With the purpose of the further verification of the performance of the MCML DFF cells, a mod-10 counter based on the proposed DFF cells and other combinational cells is implemented, as shown in Fig. 7. These cells is selected from the MCML cell library that we fully created. The full custom layout is drawn, as shown in Fig. 8. The full parasitic parameters are extracted. The mod-10 counter based on C 2 MOS DFFs from FreePDK 45nm library and Nangate open library are also implemented. The post-layout simulations based on the three kinds of counters are carried out. Fig. 9 illustrates measurement bench of the counters for post-layout simulations. Each input is driven by buffered signals and each output is loaded with buffers, which provide a realistic simulation environment reflecting the counters operation in actual applications. Fig. 10 shows the operation waveform of the MCML mod-10 counter. Qb 3 Qb 1 Q 0 Q 1 Qb 0 Q 0 Q 1 Q 2 Q 2 Q 1 Q 0 Q 3 Qb 0 D 0 Q 0 D 1 Q 1 D 2 Q 2 D 3 Q 3 clk Qb 0 Qb 1 Qb 2 Figure 7. Schematic view of a mod-10 counter. Qb 3 Figure 8. The layout of the mod-10 based on the proposed MCML cells. 6

Q 3 clk Q 2 Q 1 Q 0 Figure 9. The measurement bench. The power dissipation of the mod-10 counters based on the proposed MCML cells and the other conventional CMOS libraries at different operation frequency is shown in Fig. 11 at the NCSU FreePDK 45nm technology and 1.0V supply voltage. As the operation frequency rises from 10MHz to 2GHz, the power dissipations of the counter based on traditional CMOS libraries increase rapidly, while the counterpart based on MCML cells keeps a constant value. From Fig. 11, the cross-frequency f c is about 1GHz. When the MCML counter operates at higher frequencies than 1GHz, the power dissipation is lower than the traditional CMOS counterparts. This character of MCML circuits makes it fit for high-speed applications. 1.0V 0.8V 1.0V 0.8V 1.0V 0.8V 1.0V 0.8V 1.0V 0.8V Clk Q3 Q2 Q1 Q0 0 5 10 15 20 Time (ns) Figure 10. Post-layout simulation waveform of the MCML mod-10 counter at 1GHz operation frequency and 1.0V supply voltage. 7

Power dissipations (mw) Figure 11. The power dissipation of the mod-10 counters based on MCML and conventional CMOS libraries at different operation frequency. The supply voltage is 1.0V. Layout post simulations have been also carried out for the MCML mod-10 counter and the C 2 MOS counterparts by varying the supply voltage from nominal 1.1V to near-threshold 0.7V at 1GHz operation frequency using HSPCE tool. Fig. 12 illustrates the energy dissipations of the mod-10 counters based on the MCML DFF from proposed cell library and conventional C 2 MOS DFF from the comparative cell libraries at different supply voltages. From the curves, we can see that the power dissipated in the MCML mod-10 counter decreased while the supply voltage falls from nominal voltage to near- threshold voltage, as the same trend as the conventional CMOS counterparts. The power dissipation of the MCML mod-10 counter can save about 44.6% at 0.7V near-threshold voltage than 1.1V nominal voltage without performance degradation. Power disiipations (mw) Figure 12. The power dissipation of the mod-10 counters based on cells from MCML cell library and ones from conventional CMOS cell libraries at different supply voltages. 6. Conclusions 8

MCML is usually used for high-speed applications. The design method of the high-speed low-power MCML has been addressed in this paper. The layout implementations of MCML DFF cells are presented at a NCSU FreePDK 45nm technology. A mod-10 counter based on the proposed cells is implemented to verify the efficiency of the proposed design method. The post-layout simulations are carried out. For normal supply voltage, the MCML sequential logic circuit can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. n order to show energy efficiency and performance of the MCML circuits in near-threshold configuration applications, scaling down the supply voltage of MCML circuits is also investigated. The post-layout simulations show that the power consumption of the MCML basic gates can be reduced by lowering the supply voltage without performance degrading. 7. Acknowledgments Project is supported by National Natural Science Foundation of China (No. 61071049), Zhejiang Science and Technology Project of China (No. 2010C31116), Scientific Research Fund of Zhejiang Provincial Education Department (No. Z200908632 and No. Y201120962). 8. References [1] X. G. Guan, Z. M. Zhu, D. Zhou, Y. T. Yang, Low power asynchronous wrapper for network on chips with dynamic frequency scaling and power cut off, JDCTA: nternational Journal of Digital Content Technology and its Applications, vol. 5, no. 5, pp. 72-83, 2011. [2] X. J. Zhang, P. D. Liu, D. R. Wang, The design and implementation of smart battery management system balance technology, JCT: Journal of Convergence nformation Technology, vol. 6, no. 5, pp. 108-116, 2011. [3] M. Yamashina, H. Yamada, An MOS current mode logic (MCML) circuit for low-power sub- GHz processors, ECE Transactions on Electronics, vol. E75-C, no. 3, pp.1181-1187, 1992. [4] A. Tanabe, 0.18 m CMOS 10-Gb/s multiplexer/demultiplexer Cs using current mode logic with tolerance to threshold voltage fluctuation, EEE Journal of Solid State Circuits, vol. 36, no.6, pp. 988-996, 2001. [5] P. Heydari, Design and analysis of low-voltage current-mode logic buffers, n Proceeding(s) of nternational Symposium on Quality Electronic Design, pp. 293-298, 2003. [6] G. Caruso, A. Macchiarella, A design methodology for low-power MCML ring oscillators, n Proceeding(s) of European Conference on Circuit Theory and Design, pp. 675-678, 2007. [7] M. H. Anis, M.. Elmasry, Power reduction via an MTCMOS implementation of MOS current mode logic, n Proceeding(s) of EEE nternational ASC/SOC Conference, pp.193-197, 2002. [8] J. Beom and Kim, Low-power MCML circuit with sleep-transistor, n Proceeding(s) of EEE 8th nternational Conference on in ASC, pp. 25-28, 2009. [9] A. Tajalli, E. J. Brauer, Y. Leblebici, E. Vittoz, Subthreshold source-coupled logic circuits for ultra-low-power applications, EEE Journal of Solid-State Circuits, vol. 43, no. 7, pp. 1699-1710, 2008. [10] A. Tajalli, E. J. Brauer, Y. Leblebici, Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5fJ/stage PDP, Microelectronics Journal, vol. 40, no. 6, pp. 973-978, 2009. [11] J. M. Musicer, J. Rabaey, MOS current mode logic for low power, low noise CORDC computation in mixed-signal environments", n Proceeding(s) of nternational Symposium on Low Power Electron, pp. 102-107, 2000. [12] D. Somasekhar and K. Roy, LVDCSL: a high fan-in, high performance, low-voltage differential current switch logic family, EEE Transactions on Very Large Scale ntegration (VLS) Systems, vol. 6, no. 4, pp. 573-577, 1998. [13] D. Somasekhar and K. Roy, Differential current switch logic: a low power DCVS logic family, EEE Journal of Solid-State Circuits, vol.31, no. 7, pp.981-991, 1996. [14] S. B. Akers, Binary decision diagrams, EEE Transactions on Computers, vol.c-27, no. 6, pp. 509-516, 1978. 9

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