Features Macroblock Advance Information CN 5001CN MBI5001CN 8 constant-current output channels Constant output current invariant to load voltage change Excellent output current accuracy: between channels: < ±4% (max.), and between ICs: < ±6% (max.) Output current adjusted through an external resistor Constant output current range: 5-120 ma Fast response of output current, / (min.): 400 ns 25MHz clock frequency Schmitt trigger input 5V supply voltage DIP16-P-300-2.54 CD BI5001CD SOP16-P-150-1.27 CP Weight: 1.02g(typ) Weight: 0.13g(typ) SSOP16-P-150-0.64 Weight: 0.07g(typ) Current Accuracy Between Channels Between ICs Conditions < ±4% < ±6% I OUT = 10 ma to 60 ma, V DS = 0.6V < ±6% < ±12% I OUT = 60 ma to100 ma, V DS = 0.8V Product Description is designed for D displays. As an enhancement of its predecessor, MBI5001, exploits PrecisionDrive technology to enhance its output characteristics. contains a serial buffer and data latches which convert serial input data into parallel output format. At output stage, eight regulated current ports are designed to provide uniform and constant current sinks for driving Ds within a large range of Vf variations. provides users with great flexibility and device performance while using in their system design for D display applications, e.g. D panels. Users may adjust the output current from 5 ma to 120 ma through an external resistor, R ext, which gives users flexibility in controlling the light intensity of Ds. guarantees to endure maximum 17V at the output port. The high clock frequency, 25 MHz, also satisfies the system requirements of high volume data transmission. Macroblock, Inc. 2003 Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC. TEL: +886-3-579-0068, FAX: +886-3-579-7534 E-mail: info@mblock.com.tw - 1 - This datasheet has been downloaded from http://www.digchip.com at this page
Terminal Description Pin Description PIN NO. PIN NAME FUNCTION 1 GND Ground terminal for control logic and current sink 2 SDI Serial-data input to the shift register 3 CLK 4 Clock input terminal for data shift on rising edge Data strobe input terminal Serial data is transferred to the respective latch when is high. The data is latched when goes low. GND SDI CLK OUT 0 OUT 1 OUT 2 OUT 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD R-EXT OUT 7 OUT 6 OUT 5 OUT 4 5-12 OUT0 ~ OUT 7 Constant current output terminals Output enable terminal 13 14 15 R-EXT When (active) low, the output drivers are enabled; when high, all output drivers are turned OFF (blanked). Serial-data output to the following SDI of next driver IC Input terminal used to connect an external resistor for setting up output current for all output channels 16 VDD 5V supply voltage terminal Block Diagram OUT0 OUT1 OUT6 OUT7 R-EXT I O Regulator VDD 8-Bit Output Driver 8 8-Bit Output Latch GND 8 SDI 8-Bit Shift Register CLK - 2 -
Equivalent Circuits of Inputs and Outputs terminal terminal VDD VDD CLK, SDI terminal VDD terminal VDD CLK, SDI - 3 -
Timing Diagram N = 0 1 2 3 4 5 6 7 CLK SDI OUT0 OUT 1 OUT2 OUT3 OFF ON OFF ON OFF ON OFF ON OUT6 OUT 7 OFF ON OFF ON : don t care - 4 -
Truth Table CLK SDI OUT0 OUT5 OUT 7 H L D n D n.. D n - 5. D n - 7 D n-7 L L D n+1 No Change D n-6 H L D n+2 D n + 2. D n - 3. D n - 5 D n-5 X L D n+3 D n + 2. D n - 3. D D n - 5 n-5 X H D n+3 Off D n-5 Maximum Ratings CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage V DD 0~7.0 V Input Voltage V IN -0.4~V DD + 0.4 V Output Current I OUT +120 ma Output Voltage V DS -0.5~+20.0 V Clock Frequency F CLK 25 MHz GND Terminal Current I GND 960 ma Power Dissipation (On PCB, Ta=25 C) Thermal Resistance (On PCB, Ta=25 C) CN type 1.64 CD type 1.06 CP type P D 0.88 CN type 76 CD type 117 CP type R th(j-a) Operating Temperature T opr -40~+85 C Storage Temperature T stg -55~+150 C 141 W C/W - 5 -
Recommended Operating Conditions CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT Supply Voltage V DD - 4.5 5.0 5.5 V Output Voltage V DS OUT0 ~ OUT 7 - - 17.0 V Output Current Input Voltage I OUT DC Test Circuit 5-120 ma I OH - - -1.0 ma I OL - - 1.0 ma V IH CLK,, and SDI 0.8V DD - V DD +0.3 V V IL CLK,, and SDI -0.3-0.3V DD V Pulse Width t w(l) 40 - - ns CLK Pulse Width t w(clk) 20 - - ns Pulse Width t w() 400 - - ns Setup Time for SDI t su(d) V DD =4.5~5.5V 5 - - ns Hold Time for SDI t h(d) 10 - - ns Setup Time for t su(l) 15 - - ns Hold Time for t h(l) 15 - - ns Clock Frequency F CLK Cascade Operation - - 25.0 MHz Power Dissipation P D Ta=85 C - - 0.85 - - 0.55 - - 0.46 W - 6 -
Electrical Characteristics CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT Input Voltage H level V IH Ta = -40~85ºC 0.8V DD - V DD V L level V IL Ta = -40~85ºC GND - 0.3V DD V Output Leakage Current I OH V OH =17.0V - - 0.5 μa Output Voltage V OL I OL =+1.0mA - - 0.4 V V OH I OH =-1.0mA 4.6 - - V Output Current 1 I OUT1 V DS =0.6V R ext =744 Ω - 25.0 - ma Current Skew di OUT1 I OUT =25mA V DS =0.6V R ext =744 Ω - ±1 ±4 % Output Current 2 I OUT2 V DS =0.6V R ext =372 Ω - 50.0 - ma Current Skew di OUT2 I OUT =50mA V DS =0.6V R ext =372 Ω - ±1 ±4 % Output Current 3 I OUT3 V DS =0.8V R ext =186 Ω - 100 - ma Current Skew Output Current vs. Output Voltage Regulation Output Current vs. Supply Voltage Regulation di OUT3 I OUT =100mA V DS =0.8V R ext =186 Ω - ±1 ±6 % %/dv DS V DS within 1.0V and 3.0V - ±0.1 - % / V %/dv DD V DD within 4.5V and 5.5V - ±1 - % / V Pull-up Resistor R IN (up) 250 500 800 KΩ Pull-down Resistor R IN (down) 250 500 800 KΩ Supply Current OFF ON Test Circuit for Electrical Characteristics I DD (off) 1 R ext =Open, OUT0 ~ OUT 7 =Off - 9 - I DD (off) 2 R ext =744 Ω, OUT0 ~ OUT 7 =Off - 10 - I DD (off) 3 R ext =372 Ω, OUT0 ~ OUT 7 =Off - 11 - I DD (on) 1 R ext =744 Ω, OUT0 ~ OUT 7 =On - 10 - I DD (on) 2 R ext =372 Ω, OUT0 ~ OUT 7 =On - 11 - ma I DD I IH,IIL CLK V DD. OUT0 I OUT OUT7 V IH, VIL SDI R - EXT GND I ref - 7 -
Switching Characteristics CHARACTERISTIC SYMBOL CONDITION MIN. TYP. MAX. UNIT Propagation Delay Time ( L to H ) Propagation Delay Time ( H to L ) Pulse Width CLK - OUTn t plh1-50 100 ns - OUTn t plh2-50 100 ns - OUTn t plh3-20 100 ns CLK - t plh 15 20 - ns CLK - OUTn t phl1 V DD =5.0 V V DS =0.8 V - 100 150 ns - OUTn t phl2 V IH =V DD - 100 150 ns V IL =GND - OUTn t phl3 R ext =366 Ω - 50 150 ns CLK - t phl V L =4.0 V R L =52 Ω 15 20 - ns CLK t w(clk) C L =10 pf 20 - - ns t w(l) 20 - - ns t w() 400 - - ns Hold Time for t h(l) 5 - - ns Setup Time for t su(l) 5 - - ns Maximum CLK Rise Time t r ** - - 500 ns Maximum CLK Fall Time t f ** - - 500 ns Output Rise Time of Iout t or - 70 200 ns Output Fall Time of Iout t of - 40 120 ns **If the devices are connected in cascade and t r or t f is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Test Circuit for Switching Characteristics I DD VIH = 5V Function Generator Logic input waveform V IH, VIL CLK SDI I ref V DD OUT0. OUT7 R - EXT GND C L I OUT R L C L V L VIL = 0V t r = tf = 10 ns - 8 -
Timing Waveform t W(CLK) CLK t su(d) t h(d) SDI t plh, t phl t W(L) t h(l) t su(l) LOW = OUTPUTS ENABD HIGH = OUTPUT OFF OUTn t plh1, t phl1 t plh2, t phl2 LOW = OUTPUT ON t W() t phl3 t plh3 OUTn 90% 90% 10% 10% t of t or - 9 -
Application Information Constant Current To design D displays, provides nearly no variations in current from channel to channel and from IC to IC. This can be achieved by: 1) While I OUT is 60mA, the maximum current variation between channels is less than ±4%, and that between ICs is less than ±6%. 2) In addition, the current characteristic of output stage is flat and users can refer to the figure as shown below. The output current can be kept constant regardless of the variations of D forward voltages (Vf). This performs as a perfection of load regulation. Adjusting Output Current The output current of each channel (I OUT ) is set by an external resistor, R ext. The relationship between I out and R ext is shown in the following figure. I OUT (ma) 120 100 80 60 40 V DS = 1.0V 20 0 0 500 1000 1500 2000 2500 3000 3500 4000 Resistance of the external resistor, R ext, in Ω Also, the output current in milliamps can be calculated from the equation: I OUT is (620 / R ext ) x 30, approximately, where R ext, in Ω, is the resistance of the external resistor connected to R-EXT terminal. The magnitude of current (as a function of R ext ) is around 50mA at 372Ω and 25mA at 744Ω. - 10 -
Package Power Dissipation (P D ) The maximum allowable package power dissipation is determined as P D (max) = (Tj Ta) / R th(j-a). When 16 output channels are turned on simultaneously, the actual package power dissipation is P D (act) = (I DD x V DD ) + (I OUT x Duty x V DS x 8). Therefore, to keep P D (act) P D (max), the allowable maximum output current as a function of duty cycle is: I OUT = { [ (Tj Ta) / R th(j-a) ] (I DD x V DD ) } / V DS / Duty / 8, where Tj = 150 C. Load Supply Voltage (V D ) are designed to operate with V DS ranging from 0.4V to 1.0V considering the package power dissipating limits. V DS may be higher enough to make P D(act) > P D(max) when V D = 5V and V DS = V D Vf, in which V D is the load supply voltage. In this case, it is recommended to use the lowest possible supply voltage or to set an external voltage reducer, V DROP. A voltage reducer lets V DS = (V D Vf) V DROP. Resistors or Zener diode can be used in the applications as shown in the following figures. V D V D V DROP V DROP Vf Vf V DS V DS - 11 -
Outline Drawings CN DIP-16-P-300-2.54 Units: mm Weight: 1.02g (typ) CD SOP-16-P-150-1.27 Units: mm Weight: 0.13g (typ) CP SSOP-16-P-150-0.64 Units: mm Weight: 0.07g (typ) - 12 -