PLL LSI with Built-In Prescaler Overview The is a CMOS LSI for a phase-locked loop (PLL) frequency synthesizer with serial data parameter input. It consists of a two-coefficient prescaler, variable frequency divider, phase comparator, and charge pump. It offers high-speed operation on a low power supply voltage (1.0 to 1.4 V) and low power consumption (1.65 mw for V DD =1.1 V, F IN = R IN =90 MHz). Other features include intermittent operation by the power save (PS) control signal and high-speed pull-in that rapidly corrects the phase differences occurring at the start of operation. It also offers two choices for the reference signal: selfexcited operation using the built-in inverter amplifier or use of an external, separately excited oscillator. Features Low power supply voltage: V DD =1.0 to 1.4V Low power consumption: 1.65mW(V DD =1.10V, F IN =90MHz, R IN =90MHz) High-speed operation: F IN =90MHz, R IN =90MHz (V DD =1.1V) Frequency dividing ratios in reference frequency dividing stage 6 to 131,070 for RSL at "H" level (even number setting is available) 272 to 131,071 for RSL at "L" level Frequency dividing ratios for comparator stage: 272 to 262,143 Power supply pin for built-in charge pump V CP =2.5 to 3.2V Output monitor pins for both comparator and reference frequency dividing stages Pin Assignment X IN X OUT FV V DD D OP V SS V CP F IN 1 2 3 4 5 6 7 8 (TOP VIEW) 16 15 14 13 12 11 10 9 SSOP016-P-0225 R IN RSL LC FR PS includes following four Product lifecycle stage.
Block Diagram RSL R IN X IN X OUT Swallow counter Prescaler and phase adjustment PS Switching circuit 3-bit counter F IN 13-bit programmable counter Prescaler Phase adjustment 17-bit latch 18-bit shift register Data control 18-bit latch Control 14-bit programmable counter Swallow counter Prescaler and phase adjustment 15 16 1 2 9 10 11 12 8 4 6 13 7 5 14 3 V DD V SS FR V CP D OP LC FV Phase comparator includes following four Product lifecycle stage.
Pin Descriptions Pin No. Symbol Function Description 1 X IN Crystal oscillator connection pins: 2 X OUT X IN =Oscillator circuit input pin; (X IN is attached to a pull-up resistor when the PS or RSL pin is at "L" level.) X OUT =Oscillator circuit output pin. 3 FV Frequency divider output signal in comparator stage. 4 V DD Power supply Phase comparator input monitor. 5 D OP Low-pass filter connection pin. Use a passive filter. 6 V SS Ground 7 V CP Power supply pin for built-in charge pump 8 F IN Frequency divider input pin in comparator stage. 9 Shift register clock input pin. 10 Shift register data input pin. The chip latches data at the rising edge of the signal. The final two bits in the data select the write latch: "11" for R-latch; "01" for N-latch. 11 Load enable signal input pin. This is the latch-write-enable signal. It is at "H" level for write. 12 PS Power save control signal input pin. "H" level input starts the frequency divider and places the chip in operational mode. "L" level input places the chip in standby mode, which saves power. The chip switches the internal charge pump output to the H-z state and the loop is opened. 13 FR Reference frequency divider output signal. Phase comparator input monitor. 14 LC Charge pump control signal output pin. When frequency divider operation is stopped, this pin is at "L" level, the internal charge pump output is in the high-impedance state, and the loop is opened. 15 RSL Reference signal selection pin. "H" level selects self-excited oscillator (X IN and X OUT ). "L" level selects external oscillator (R IN ). 16 R IN External reference oscillation input pin. This pin is attached to a pull-up resistor when the PS pin is at "L" level or the RSL pin is at "H" level. includes following four Product lifecycle stage.
Frequency Dividing Data Settings 1) Comparator side frequency dividing data FV = F IN {(16 N) + A} 2) Reference side frequency dividing data a) Low-speed operation (RSL pin at "H" level, using X IN ) FR = X IN R b) High-speed operation (RSL pin at "L" level, using R IN ) FR =R IN {(16 NR) + AR} where F IN : Comparator side frequency R IN : High-speed reference frequency X IN : Low-speed reference oscillator frequency FV : Comparator frequency divider stage output frequency FR : Reference frequency divider stage output frequency N : Setting for 14-bit programmable counter on comparator side A : Setting for 4-bit swallow counter on comparator side R : Setting for 17-bit programmable counter on low-speed reference side NR : Setting for 13-bit programmable counter on high-speed reference side AR : Setting for 4-bit swallow counter on low-speed reference side (Note that N should be greater than A; NR, greater than AR.) N-Side Latch Data R-Side Latch Data Low-speed operation High-speed operation 13 bits 14 bits 4 bits LSB Programmable counter setting (N) Programmable counter setting (NR) 17 bits Programmable counter setting (N) Swallow counter setting (A) 4 bits Swallow counter setting (AR) includes following four Product lifecycle stage. LSB LSB
Note on Setting Frequency Dividing Data Input 1) Frequency dividing data input (1) Reference side Data input direction LSB Control bits (2) Comparating side *1 17-bit frequency dividing data Data input direction 1 2 3 4 5 21 22 23 Notes 1.*1: Preceding the input of the frequency dividing data for the comparating side, input test pattern consisting of three "L" level bits to produce normal operation. Never use any other pattern. 2. When the power is first applied, internal operation remains in an unstable state until data is written. To eliminate the risk of excessive current consumption, keep the PS pin at "L" level. 3. When the power is first applied, the data settings are indeterminate. Always write data to the chip before starting operation. 4. Enter the data to fill the entire latch: Reference side: 19 bits (17 bits for the frequency divider setting and 2 for control bits) Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 for control bits) 5. Drive the pin at "L" level while writing the data. 6. "H" level input from the pin causes the chip to read the data only when the pin and the pin are both at "L" level. 7. Writes are possible when the PS pin is either "H" or "L" level. 8. Input the data first. 9. The data are inputted at the rising edge of the signal. 1 bit Control bits 1 bit 1 bit 1 bit "L" Frequencey Write selection dividing stage "H" level selection "H" level 1 2 17 18 19 3-bit test data 3 bits "L" level LSB 18-bit frequency dividing data LSB Frequencey Write selection dividing stage "H" level selection "L" level includes following four Product lifecycle stage. "L"
Absolute Maximum Ratings Parameter Symbol Rating Unit Power supply voltage V DD 0.3 to +3.0 Power supply voltage V CP 0.3 to +4.0 Input pin voltage V I V SS 0.3 to V DD +0.3 Output pin voltage V O V SS 0.3 to V DD +0.3 Power dissipation P D 20 mw Operating ambient temperature T opr 10 to +60 Storage temperature T stg 55 to +125 Operating Conditions V SS =0V, Ta= 10 to +60 C Parameter Symbol Test Conditions min typ max Unit Power supply voltage V DD 1.0 1.1 1.4 V Power supply voltage V CP 2.5 3.0 3.2 V Electric Characteristics V CP =2.5V, Ta= 10 to +60 C Parameter Symbol Test Conditions min typ max Unit Power supply pin V DD V DD =1.1V Power supply current I DD F IN =90MHz, RIN=90MHz, 2.3 ma PS="H", RSL="L" Input Pins,,, and PS V DD =1.0 to 1.4 V I Dstop PS="L" (Power Save operation) 3 µa "H" level input voltage V IH V DD 0.2 V DD V "L" level input voltage V IL V SS 0.2 Input leakage current I LI ±1.0 µa Input Pins F IN, R IN V DD =1.0 to 1.4V Input voltage V IN 0.4 V p-p Input current I IF Pull-up resistor is present 10 µa (PS="L") Input leakage current I LIF V IN =0 or V DD (PS="H") ±20 µa Maximum operating frequency F INMAX V IN =0.4 V p-p 90 MHz R INMAX Minimum operating frequency F INMIN V IN =0.4 V p-p 1.0 MHz Input Pin X IN V DD =1.0 to 1.4V R INMIN Input voltage V IN 0.4 V p-p Input current I IX Pull-up resistor is present 0.1 1.5 ma (PS="L") includes following four Product lifecycle stage. Input leakage current I LIX V IN =0 or V DD 5.0 µa Maximum operating frequency X INMAX V IN =0.4 V p-p 15 MHz V C
Electrical Characteristics (continued) V CP =2.5V, Ta= 10 to +60 C Parameter Symbol Test Conditions min typ max Unit Crystal Oscillator Pins X IN, X OUT V DD =1.0 to 1.4V Crystal oscillator frequency f Xtal 15 MHz Output Pins FV, FR, LC V DD =1.0 to 1.4V "H" level output voltage V OH I OH = 10µA V DD 0.3 V DD V "L" level output voltage V OL I OL =10µA V SS 0.3 Output Pin X OUT V DD =1.0 to 1.4V "H" level output voltage V XOH I XOH = 100µA V DD 0.3 V DD V "L" level output voltage V XOL I XOL =100µA V SS 0.3 Output Pin D OP V DD =1.0 to 1.4V "H" level output voltage I DOH V Dop =V CP 0.3V 100 µa "L" level output voltage I DOL V Dop =0.3V 100 Output leakage current I LOH V Dop =V CP 2.0 Output leakage current I LOL V Dop =0.0V 2.0 V DD =1.0 to 1.4V Setup time *1 t sul 500 ns t su2 500 ns Hold time *1 t H 500 ns Note*1: The following timing chart shows the setup and hold times. 50% t su1 t H t su2 Usage Note Be particularly careful with this product as it is more sensitive on the static electricity damage than most of our other products. includes following four Product lifecycle stage.
Application Circuit Example 0.22µF *1 Loop filter VF V DD =1.0V to 1.4V 10kΩ 100Ω VCO VCC 35kΩ 1µF 10µF V CP =3V 80 to 90MHz 390Ω 0.1µF 0.1µF 1000pF V CC =3V Amplifier 1 2 3 4 5 6 7 8 X IN X OUT FV V DD D OP V SS V CP F IN R IN RSL LC FR PS 16 15 14 13 12 11 10 9 Separately excited oscillator Intermittent operation control Frequency dividing data input Frequency dividing data input Frequency dividing data input includes following four Product lifecycle stage. *1 VCO characteristics may necessitate design revisions.
Package Dimensions (Unit: mm) SSOP016-P-0225 16 1 (0.45) 0.8 0.15 6.5±0.2 9 1.0±0.1 0.35±0.10 8 4.3±0.2 1.45±0.20 0.1±0.1 6.3±0.2 1.55±0.30 0.15 +0.10 SEATING PLANE -0.05 0.5±0.1 0 to 10 includes following four Product lifecycle stage.
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