EiceDRIVER Getting started with 1EDS -SRC 1EDS20I12SV 1EDU20I12SV 1EDI20I12SV Application Note AN2015-01 About this document Scope and purpose This document explains the 5 basic design steps to create a reliable design using the gate current control ICs of the 1EDS-SRC family. Intended audience The application note addresses hardware engineers who want to go through the design-in process quickly with a minimum of redesign cycles. Application Note AN2015-01 1 <Revision 1.3>, <2018-06-07> AN2015-01
Introduction Table of Contents 1 Introduction... 3 2 Signal interfacing at the IC s input side... 4 3 Design of the gate current control circuit... 5 4 Value and component selection for the turn-off section... 10 5 Two-level turn-off design... 13 6 Hints for the layout of the desaturation detection... 14 Application Note AN2015-01 2 <Revision 1.3>, <2018-06-07>
Introduction 1 Introduction The gate current control IC 1EDS20I12SV is an advanced, innovative gate driver IC. It uses a closed loop gate current control for charging the gate of an IGBT. Furthermore, the IC can change the speed of the turn-on process by means of a specific analog input signal at the input side of the IC. Please refer to the Technical Description in AN2014-03 for detailed information. Important steps to successfully operate the 1EDS20I12SV are: signal interfacing of the input side gate current control circuit on the output side. Particularly o definition of the preboost current o design and selection of the current sense resistor o calculation of the controlled current source which is used for turn-on of the IGBT o design and selection of the damping elements calculation of the gate resistor, the PNP transistors for turn-off and the soft turn-off gate resistor design of the two-level turn-off function calculation of external components used in the desaturation detection function All these sections will be discussed in this document, resulting in a reliable design after executing these steps. The basis of the design example in this document is given in Table 1 Table 1 Parameter Module DC link voltage Positive gate voltage Negative gate voltage Target specification for design example maximum switching frequency Preboost current equivalent for turn-on current Turn-off resistor Value FF600R12ME4 600 V +15 V - 8 V 10 khz Level 10 Max. ambient temperature 85 C Max. junction temperature of PMOS during operation 2 x 3 Ω parallel 125 C Application Note AN2015-01 3 <Revision 1.3>, <2018-06-07>
Signal interfacing at the IC s input side 2 Signal interfacing at the IC s input side This section describes the signal interfacing at the IC s input side. 2.1 Calculation and selection Power electronic systems themselves are harsh environments in terms of noise and ground bouncing. It is therefore often necessary to filter input signals in order to obtain the real signal content. The points of time, where current commutation occurs, are naturally these instances, where a high noise level can be observed. A target of the filtering of input signals is to get rid of the signal noise during these periods. The input filter time constant therefore must be considerably longer than the switching times of the driven IGBT. A RC-time constant being more than 3 times higher than the maximum switching time results in good filtering. Figure 1 gives an example of the switching times for a FF600R12ME4 EconoDUAL 3 module. a) b) Figure 1 Datasheet excerpt for a) rise and b) fall time of a FF600R12ME4 Noise filters are usually more efficient, if the capacitive portion is dominant. A good starting point for the series resistance of a RC-filter is 100. The capacitance is therefore for a FF600R12ME4 C = max (t r, t f ) 100 Ω 3 = 0.12 µs 100 Ω 3 = 3.6 nf (1) A standard value for the RC-filter capacitance is C = 3.3 nf. One can give an additional margin to the calculation of the filter time constant, because the values given in the datasheet are typical ones only. 2.2 Component placement and layout It is mandatory for the best filtering effect that the capacitor and the filter resistor are placed as close as possible to the IC s input terminals. The loop of signal track and ground must be minimized and there must not be any area close to the filter for example in an inner PCB layer which is switched between DC + rail and DC- rail. Application Note AN2015-01 4 <Revision 1.3>, <2018-06-07>
Design of the gate current control circuit 3 Design of the gate current control circuit This section describes the design of the gate current control circuit. 3.1 Determining the required preboost current The preboost current is a function of the IGBT s gate charge. The gate charge diagram of the FF600R12ME4 is given in Figure 2. 15 10 V Q G,PRB 5 Q G,rest 0-5 2.05 µc -10 1.22 µc 4.9 µc V GE -15 0 1 2 3 µc 4 5 Q G Figure 2 Gate charge diagram of FF600R12ME4 The preboost current amplitude must be selected in a way that the IGBT does not reach the Miller voltage during preboost. The IGBT tolerances must be considered, such as the dependency of the gate-emitter threshold voltage over temperature and over collector current. A good rule of thumb is to select the voltage after preboost as half the value of the gate-emitter threshold voltage V GE(th). V GE,PRB = V GE(th) 2 The current amplitude which is needed to increase the gate-emitter voltage from the starting voltage to V GE,PRB,end in typically 135 ns is I PB = Q G,PRB 135 ns = 5.6 V 2 = 2.8 V (2) = 2.05 µc - 1. 22 µc 135 ns = 6.08 A (3) 3.2 Selecting the gate current sense resistor value and component The controlled current source requires a shunt resistor. The value of the current sense resistor determines the current level during the turn-on phase of the turn-on sequence. The turn-on current I gg,10 at level 10 equals to the preboost current I PB in this example. This corresponds to a shunt voltage of 1 V. The 11 turn-on current levels are given in the datasheet. Application Note AN2015-01 5 <Revision 1.3>, <2018-06-07>
Design of the gate current control circuit The shunt resistor value is RS = V RS,10 1 V = I gg,10 6.08 A = 0.16 Ω (4) The next smaller value out of the E24 standard series is RS = 0.15. 3.3 Dimensioning the voltage divider at terminal PRB Terminal PRB is referenced to VEE2. The voltage divider can therefore either divide the voltage V GND2 -V VEE2 or V VCC2 -V VEE2 according to Figure 3 VCC2 VCC2 R PRB1 PRB R PRB2 V PRB GND2 R PRB1 GND2 PRB R PRB2 V PRB 1EDS-SRC VEE2 1EDS-SRC VEE2 Figure 3 External circuit for setting of the preboost current, unipolar supply (left), bipolar supply (right) The voltage divider is between terminal GND2 and VEE2 in this example, which is the circuit in the right part of Figure 3. The IC generates the preboost current on basis of equation (5) as described in the datasheet [2]: I PRB = 2 (V PRB V VEE2 ) (5) 3 RS The value of RS = 0.15 and R PRB2 is selected for R PRB2 = 15 k. The related resistance R PRB2 is therefore 2 R PRB1 = 3 V VEE2 I gg,10 RS 2 R I gg,10 RS PRB2 = 3 8 V 6.08 A 0.15 Ω 6.08 A 0.15 Ω 15 kω = 72.76 kω (6) as it is derived in [3]. The selection of R PRB1 is R PRB1 = 75 k. The selection results in a preboost current of I PRB = 5.93 A, hence the voltage which is reached at the end of the preboost phase is V GE,PRB = 2.22 V. This is acceptable, because it gives enough margin to the gate-emitter threshold voltage V GE(th) of the IGBT. The divider is formed by high resistances, so that small sized SMD-footprints such as 0603 or even smaller are suitable. 3.4 Calculating the rms power dissipationof the shunt resistor RS The proposed selection of RS, R PRB1 and R PRB2 results in a marginally lower turn-on current of I gg,10 = I PRB = 5.93 A. The rms current of the resistance can be calculated according to [3] by 2 I RS,rms (I gg, T on ) = I PRB 135ns f P + I 2 gg T on f P (7) The rms value of the shunt current is highest, when the turn-on current is highest. The highest turn-on current is related to level 11. This corresponds to 157% of the preboost current according to the Application Note AN2015-01 6 <Revision 1.3>, <2018-06-07>
Design of the gate current control circuit datasheet of the 1EDS20I12SV. The turn-on time T on is the ratio of the gate charge Q G,rest according to Figure 2 divided by the real preboost current of level 11. 2 2 I RS,rms = I PRB 135ns f P + I gg,11 T on,11 f P (8) = 5.93 2 A 2 135ns 10 khz + (1.57 5.93) 2 A 2 4.9 µc 2.02 µc 1.57 5.93 A 10 khz = 0.56 A Now the rms power dissipation is determined by 2 P RS,rms = I RS,rms RS = (0.56 A) 2 0.15 Ω = 47 mw (9) The extremely low power dissipation allows using geometrically small resistors. Small size resistors also support efficient layouts with short PCB tracks. The peak power stress of the shunt resistor must be also considered for the selection. It is important to consult the resistor s datasheet for the single pulse power capability and its derating over temperature. The pulse power is 2 P RS,pk = I gg,11 RS = (1.57 5.93 A) 2 0.15 Ω = 13 W (10) It is of course always possible to use two or more resistors in parallel for improved power and heat spreading. 3.5 Calculatingthe average power dissipationof the current source p- channel MOSFET It is recommended to use multiple BSD314SPE [4] MOSFETs in parallel. This type fulfills all selection requirements, such as low R DS(on), low V GS(th) and low Q G,tot The number of MOSFETs in parallel depends only on their thermal properties and the dissipated power. The power dissipation of the MOSFET is divided into phases according to [3]. The dissipation in the preboost phase is P d,pmos,avg1 = f P I PRB T PRB (V VCC2 V VEE2 I PRB RS I PB T PRB 2 C ies,prb ) = 10kHz 5.93A 135ns (15V + 8V 5.93A 0.15Ω 5.93A 135ns (2.22V + 8V) ) = 136 mw 2 0.80 µc The worst case average power dissipation during the turn-on phase T on occurs at SPEED level 1, which means I gg = 0.2 I PB. The power dissipation is therefore (11) P d,pmos,avg2 = f P 0.2 I PRB (V VCC2 V GE,PRB 0.2 I PRB RS) Q G,rest 0.2 I PRB = 10 khz (15 V 2.22 V 0.2 5.93 A 0.15 Ω) 2.88 µc = 362.5 mw This equation contains a design margin by assuming that the charging of Q G,rest after preboost is performed at a gate voltage 2.22 V. The total losses under this assumption are P d,pmos, tot = 136 mw + 362.5 mw = 498.5 mw. The thermal resistance junction to ambient R th(j-a) of the BSD314SPE is 250 K/W. The maximum junction temperature should be below 125 C. Therefore the minimum number of MOSFET in parallel is n PMOS = R th(j-a) P d,pmos,tot T j,max T a,max (12) = 250 C W 437 mw = 3.12 (13) 125 C 85 C Application Note AN2015-01 7 <Revision 1.3>, <2018-06-07>
Design of the gate current control circuit Equation (13) results in a number of 3 P-channel MOSFET in parallel for driving the FF600R12ME4 power module with 10 khz and considering the margin which is explained above. The calculation of the maximum junction temperature results in a junction temperature of 126.54 C when using 3 MOSFET. 3.6 Calculating the peak power dissipation of the p-channel MOSFET The peak power dissipation can be derived from equations (11) and (12), if the averaging over a pulse period is not executed. The result for the preboost phase is P d,pmos,pk1 = I PRB (V VCC2 V VEE2 I PRB RS I PB T PRB 2 C ies,prb ) = 5.93A (15V + 8V 5.93A 0.15Ω 5.93A 135ns (2.22V + 8V) ) = 100.7 W 2 0.80 µc (14) And for the turn-on phase at level 11 P d,pmos,pk2 = I gg,11 (V VCC2 V GE,PRB I gg,11 RS) = 1.57 5.93 A (15 V 2.22 V 1.57 5.93 A 0.15 Ω) = 105.9 W (15) It is possible to superpose both portions of the peak power dissipation in order to obtain the resulting temperature increase after the turn-on phase by using the transient thermal impedance of BSD314SPE. This means that the temperature increase caused by the preboost phase and the temperature increase caused by the turn-on phase can simply be added. Figure 4 Thermal impedance of BSD314SPE and extrapolation into nanoseconds range The thermal impedance for the preboost phase is Z th(j-a) (t = 135 ns) 0.2 K/W and for the turn-on phase it is Z th(j-a) (t = 309 ns) 0.3 K/W. The temperature increases are for the preboost phase T PMOS,PRB = P d,pmos,pk1 Z th(j a) (135 ns) = 100.7 W 0.2 K = 20.14 K (16) W And for the turn-on phase it is T PMOS,on = P d,pmos,pk2 Z th(j a) (309 ns) = 105.9 W 0.3 K = 31.78 K (17) W Application Note AN2015-01 8 <Revision 1.3>, <2018-06-07>
Design of the gate current control circuit The total temperature increase results therefore of T PMOS = 20.14 K + 31.78 K = 51.92 K. The junction temperature of the p-channel MOSFET should not exceed the maximum rating of 150 C. The temperature budget is then 150 C 85 C = 65 C. It is easy to see, that the temperature increase T PMOS does not exceed 65 C. A paralleling of MOSFETs due to the pulse power condition is therefore not required. However, the average power dissipation condition of section 3.5 is still valid and has to be considered. 3.7 PCB-Layout considerations The placement of the blocking capacitors C VCC2, the current sense resistors and the PMOS transistors is crucial for a proper operation of the current control loop. Parasitic inductances result in lower performance of the current control, such as overshoots and oscillations. Hence, a dense component placement is important. The evaluation of the power dissipation of the shunt resistor is mandatory, because this is the basis to select the smallest possible footprint for the current sense resistor. The smallest footprint leads to the smallest distance. Paralleling more components can help to select smaller footprints. Figure 5 shows a realization of the component placement and the resulting gate current waveform for a turn-on sequence. This layout is based on a single sided assembly of components. p-ch FET damping C VCC -I G V L,par C PR V GE 6.35mm RS Figure 5 Layout example (left) and waveform results (right, blue: inverted gate current 3.3A/div, purple: gate voltage 5V/div) There is an inductive voltage drop V L,par clearly visible in the instantaneous gate-emitter voltage V GE, when the current changes from its preboost level to the turn-on level. This happens even though the components are placed in close proximity to each other. A much denser realization is possible utilizing double sided assembly of the electrical components. The layout situation for the preboost voltage divider is relatively relaxed compared to the gate current control loop. However, the voltage divider and especially the filter capacitor C PRB are recommended to be placed close to the 1EDS20I12SV. Application Note AN2015-01 9 <Revision 1.3>, <2018-06-07>
Value and component selection for the turn-off section 4 Value and component selection for the turn-off section The approach used here is based on the assumption that the total turn-off gate drive losses are dissipated in either the turn-off resistor or in the turn-off PNP transistor. This is a worst case approach and usually results in a design with considerable margin in terms of power dissipation. Another design approach may be to measure the turn-off current and calculate the resulting rms and single pulse stresses. 4.1 Power dissipation and component selection of the turn-off resistor Typical resistors for this purpose are given in [5]. The power dissipation capability of these resistors is derated to 80%. The power dissipation rating of the turn-off resistor is P d,roff,rms = (V VCC2 V VEE2 ) Q G,tot f P (15 V + 8 V) 4.9 µc 10 khz = = 0.704 W (18) 2 0.8 2 0.8 This power can be handled with one resistor in a 2010 package which has a power dissipation capability of 0.75 W. The pulse power capability is based on the assumption that the two-level turn-off is not activated. The peak power is calculated as an equivalent pulse power value P EPP for two resistors in parallel which matches to various datasheets of resistors. This equation is given for example in [6]: P EPP,ROFF = (V VCC2 V VEE2 ) 2 (15 V + 8 V)2 = = 110.2 W (19) R OFF 0.8 2 3 Ω 0.8 Looking up the the single pulse peak power capability of the turn-off resistor for example in [5] shows that a resistor in size 1206 has a capability of 40 W for pulse periods of 10 µs and shorter. A multiple of resistors is therefore required. The required number is n = 110.2 W / 40 W = 2.76. Three resistors have to be used in parallel. The two-level duration of the 1EDS20I12SV is limited to 5 µs by the watchdog timer which is shorter than 10 µs. Thus, the choice is valid even for considering the twolevel turn-off. 4.2 Component selection of the soft turn-off resistor The soft turn-off gate resistor selection should consider the turn-off propagation delay of the IGBT. A large turn-off resistor will result in longer turn-off propagation delays. A possible range for the soft turn-off resistor is between 10 and 30 times the value of the normal turn-off resistor. The consideration of the pulse power dissipation is mandatory for the soft turn-off resistor, but the rms power dissipation consideration is neglectable, because of the single event nature of the soft turn-off. 4.3 Pulse current capability and component selection of the turn-off PNP transistor A typical transistor for this purpose is ZXTP25040DFH [7]. The calculated maximum average power dissipation capability of this transistor for an ambient temperature of T amb = 85 C according to Table 1 is P d,pnp,avg = P d k T = 730 mw (85 C 25 C) 5.84 mw = 379.6 mw (20) C The maximum rating for pulse currents at an ambient temperature of T amb = 25 C is usually given in the transistors datasheets, such as in [7]. The pulse current capability derates over ambient Application Note AN2015-01 10 <Revision 1.3>, <2018-06-07>
Value and component selection for the turn-off section temperature. It has to fit to the current capability, which is defined by the turn-off gate resistors. The required current capability is therefore: I C,pk = V VCC2 V VEE2 23 V = = 8.52 A (21) R G,ext + R G,int 1.5 Ω + 1.2 Ω The derating factor can be calculated by utilizing the overall power derating. k T = P d,pnp,avg P d,pnp = 379.6 mw = 0.52 (22) 730 mw The required pulse current capability can be calculated now and also the number n of required PNP transistors I C,pk 8.52 A n = = = 1.82 (23) k T I CM 0.52 9 A Therefore, n = 2 transistors are necessary to cover the pulse current capability of the application under an ambient temperature of T amb = 85 C. 4.4 Average power dissipation of the turn-off PNP transistors The average power dissipation contains 2 portions: The collector path disspation, which covers the losses of the IGBT s gate charge and the base path dissipation, which covers the losses of the PNP transistors control. P d,off,avg,c = V CE(sat) Q g f p 1.5 = 0.4 V 4.9 µc 10 khz 1.5 = 29.4 mw P d,off,avg,b = V BE I B D 1.5 = 1.0 V 0.852 A 0.01 1.5 = 12.8 mw Both equations contain a margin of 50%, which is represented by the factor of 1.5. Equations (24) and (25) result in a total dissipation of P d,off,avg,tot = 29.4 mw + 12.8 mw = 42.2 mw. The required number of transistors for the average power dissipation condition when considering again the temperature derating, is The average power dissipation condition would require only 1 PNP transistor, however, the pulse current capability condition requires 2 transistors ond rules here. 4.5 Pulse power dissipation of the turn-off PNP transistor The pulse power dissipation contains as well the collector path and the base path portions similar to the average dissipation calculation. The total pulse power is therefore P d,off,pk = 5.11 W + 1.28 W = 6.39 W. Again, the temperature derating has to be considered, too, with the same factor k T = 0.52, which is given in equation (22). Additionally the copper layer thickness of the used PCB is important and leads to an andditional derating factor (24) (25) n = P d,off,avg 42.2 mw = = 0.11 (26) P d,pnp,tot 379.6 mw P d,off,pk,c = V CE(sat) V VCC2 V VEE2 15 V + 8 V 1.5 = 0.4V 1.5 = 5.11 W R G,ext + R G,int 1.5 Ω + 1.2 Ω P d,off,pk,b = V BE I B 1.5 = 1.0 V 0.852 A 1.5 = 1.28 W (27) (28) k Cu = P d,1oz = 730 mw = 0.584 (29) P d,2oz 1250 mw Application Note AN2015-01 11 <Revision 1.3>, <2018-06-07>
Value and component selection for the turn-off section The pulse width range of the single pulse capability of ZXTP25040DFH ends at 100 µs. A maximum power of approximately 190 W is specified there. This value is derated with respect to the above mentioned derating factors for temperature and the copper thickness of the PCB to P d,pnp,pk = k Cu k T P d,pk = 0.584 0.52 190 W = 57.7 W (30) The allowed maximum peak power dissipation of 57.7 W is much higher than the required 6.39 W. The selected transistor offers therefore a large margin. Application Note AN2015-01 12 <Revision 1.3>, <2018-06-07>
Two-level turn-off design 5 Two-level turn-off design This section describes the dimensioning and selection of components related to the two-level turn-off. 5.1 Dimensioning and selecting the timing capacitor A good target value of the two-level set time T TLSET is between 1 µs and 2 µs. Longer two-level set times may lead to higher turn-off energies E off than specified in the power module datasheet.the twolevel set time capacitance is calculated therefore by C CZ = T TLSET I CZ V TLTO,th 1.5 µs 950 µa = = 560 pf 2.5 V (31) C CZ = 560 pf is a standard value of capacitances and leads to a slightly larger two-level set time of T TLSET = 1.47 µs. I CZ is the two-level set current according to the datasheet. 5.2 Selection of the second turn-off level The second turn-off level should be chosen in order to compromise neither the turn-off switching losses nor the absolute maximum voltage capability of the IGBT. Especially the latter depends on the board layout as well, so that a general recommendation is not possible. However, experience shows that values between 9 V and 13 V result in an acceptable turn-off performance of the IGBT. The 1EDS-SRC family offers three discrete levels at 9.3 V, 10.3 V, and 11.4 V 5.3 Layout recommendations The timing capacitor should be placed as close to the IC as possible. Any kind of parasitic layout capacitance adds to the physically placed component. Such capacitances can be unintentionally created by copper areas, especially in multi-layer PCB boards. Just as a reference: A PCB track of 1mm width and 10mm length has a capacitance of approximately 1.9 pf to a potential GND-plane in the inner layer. Application Note AN2015-01 13 <Revision 1.3>, <2018-06-07>
Hints for the layout of the desaturation detection 6 Hints for the layout of the desaturation detection Setting the desaturation blanking time T DESATBLANK of the 1EDS20I12SV is a critical part of the desaturation detection circuit. The target is to have the complete reaction time of the driver and IGBT for a shut down in case of desaturation shorter than the specified short circuit withstand time t SC of the IGBT. A blanking time of T DESATBLANK = 5µs is selected. Therefore, the blanking capacitance C DESAT is according [3] C DESAT = T DESATBLANK I DESAT V DESAT 5 µs 500 µa = = 277.8 pf (32) 9 V Hence, a capacitance of C DESAT = 270 pf is a suitable selection for achieving a blanking time of approximately 5µs. Parasitic coupling capacitances between terminal DESAT and terminal GND2 may increase the resulting capacitance which is active at terminal DESAT. Injected noise coming from the dv CE /dt of the driven IGBT will be filtered by the series resistor R DESAT between the blanking capacitor C DESAT and the decoupling high voltage diode. A value of 1 k is sufficient to build a RC filter in combination with the blanking capacitor to remain with the rise and fall times according to the datasheet excerpt in Figure 1. A clamping diode between terminal DESAT and GND2 is optional and can be either a schottky or a silicon diode. As depicted in Figure 6 R DESAT and C DESAT must be placed as close to the IC as possible. C DESA R DESA Figure 6 Layout example for the component placement at terminal DESAT Application Note AN2015-01 14 <Revision 1.3>, <2018-06-07>
Hints for the layout of the desaturation detection References [1] Infineon Technologies: FF600R12ME4; datasheet; Infineon Technologies, Neubiberg, Germany. [2] Infineon Technologies: 1EDS20I12SV; datasheet; Infineon Technologies, Neubiberg, Germany. [3] Infineon Technologies: 1EDS20I12SV Technical description; Application Note; Infineon Technologies, Neubiberg, Germany. [4] Infineon Technologies: BSD314SPE; datasheet; Infineon Technologies, Neubiberg, Germany. [5] KOA: Flat chip thick film general purpose RK73B; datasheet Rev 10.Nov.2006; KOA, Japan, 2006. [6] KOA: Handling precautions for flat chip resistors; Application note, Rev. B1_1, KOA, Japan, May 9 th 2007. [7] Diodes: ZXTP25040DFH, datasheet, Diodes, USA. Revision History Major changes since the last revision Page or Reference Description of change Section 4 Adapted calculation of PNP transistor for turn-off all Updated IC parameter data to preliminary status of IC Application Note AN2015-01 15 <Revision 1.3>, <2018-06-07>
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