T553C UHF ASK/FSK Transmitter DATASHEET Features Integrated PLL loop ilter ESD protection also at / (3kV HBM/150V MM; Except pin 2: 3kV HBM/100V MM) High output power (8.0dBm) with low supply current (9.0mA) Modulation scheme ASK/FSK FSK modulation is achieved by connecting an additional capacitor between the load capacitor and the open drain output o the modulating microcontroller Easy to design-in due to excellent isolation o the PLL rom the PA and power supply Single Li-cell or power supply Supply voltage 2.0V to.0v in the temperature range o 0 C to +85 C/125 C Package TSSOP8L Single-ended antenna output with high eicient power ampliier CLK output or clocking the microcontroller One-chip solution with minimum external circuitry 125 C operation or tire pressure systems 510M-RKE-09/15
1. Description The Atmel T553C is a PLL transmitter IC which has been developed or the demands o RF low-cost transmission systems at data rates up to 32kBaud. The transmitting requency range is 310MHz to 350MHz. It can be used in both FSK and ASK systems. Figure 1-1. System Block Diagram 1 Li cell Keys Encoder ATARx9x UHF ASK/FSK Remote control transmitter T553C PLL Antenna Antenna U31B/ U35B/ T53/ T5 UHF ASK/FSK Remote control receiver Demod IF Amp Control 1 to 3 Microcontroller XTO VCO PLL XTO LNA LNA VCO 2
2. Pin Coniguration Figure 2-1. Pinning TSSOP8L CLK PA_ENABLE 1 2 3 T553C 8 6 5 ENABLE GND Table 2-1. Pin Description Pin Symbol Function Coniguration 1 CLK Clock output signal or microcontroller The clock output requency is set by the crystal to / 100Ω 100Ω CLK 2 PA_ENABLE Switches on power ampliier, used or ASK modulation PA_ENABLE 50kΩ U REF = 1.1V 20μA 3 Emitter o antenna output stage Open collector antenna output 3
Table 2-1. Pin Description (Continued) Pin Symbol Function Coniguration 5 Connection or crystal 1.5kΩ 1.2kΩ 182μA 6 Supply voltage See ESD protection circuitry (see Figure -5 on page 8) GND Ground See ESD protection circuitry (see Figure -5 on page 8) 8 ENABLE Enable input ENABLE 200kΩ Figure 2-2. Block Diagram T553C Power up/down CLK 1 8 ENABLE 32 PA_ENABLE 2 PDF GND CP 3 6 LF PA PLL VCO XTO 5
3. General Description This ully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 hence a 9.838MHz crystal is needed or a 315MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs typically < 3 ms until the PLL is locked and the CLK output is stable. There is a wait time o 3ms until the CLK is used or the microcontroller and the PA is switched on. The power ampliier is an open-collector output delivering a current pulse which is nearly independent rom the load impedance. The delivered output power is hence controllable via the connected load impedance. This output coniguration enables a simple matching to any kind o antenna or to 50. A high power eiciency o =P out /(I S,PA V S ) o 0% or the power ampliier results when an optimized load impedance o Z Load = (255 + j192) is used at 3V supply voltage.. Functional Description I ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount o current so that a lithium cell used as power supply can work or several years. With ENABLE = H the XTO, PLL and the CLK driver are switched on. I PA_ENABLE remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO requency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power ampliier are on. With PA_ENABLE the power ampliier can be switched on and o, which is used to perorm the ASK modulation..1 ASK Transmission The Atmel T553C is activated by ENABLE = H. PA_ENABLE must remain L or typically 3 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means o pin PA_ENABLE. Ater transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The Atmel T553C is switched back to standby mode with ENABLE = L..2 FSK Transmission The Atmel T553C is activated by ENABLE = H. PA_ENABLE must remain L or typically 3ms, then the CLK signal can be taken to clock the microcontroller and the power ampliier is switched on with PA_ENABLE = H. The chip is then ready or FSK modulation. The microcontroller starts to switch on and o the capacitor between the load capacitor and GND with an open-drain output port, thus changing the reerence requency o the PLL. I the switch is closed, the output requency is lower than i the switch is open. Ater transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The Atmel T553C is switched back to standby mode with ENABLE = L. The accuracy o the requency deviation with pulling method is about ±25% when the ollowing tolerances are considered. Figure -1. Tolerances o Frequency Modulation V S C Stray1 C M C Stray2 L M C R S C 0 C 5 Crystal equivalent circuit C Switch Using C = 8.2pF ±5%, C 5 = 10pF ±5%, a switch port with C Switch = 3pF ±10%, stray capacitances on each side o the crystal o C Stray1 =C Stray2 = 1pF ±10%, a parallel capacitance o the crystal o C 0 = 3.2pF ±10% and a crystal with C M = 13F ±10%, an FSK deviation o ±21.5kHz typical with worst case tolerances o ±16.25kHz to ±28.01kHz results. 5
.3 CLK Output An output CLK signal is provided or a connected microcontroller, the delivered signal is CMOS compatible i the load capacitance is lower than 10pF..3.1 Clock Pulse Take-over The clock o the crystal oscillator can be used or clocking the microcontroller. Atmel s ATARx9x has the special eature o starting with an integrated RC-oscillator to switch on the Atmel T553C with ENABLE = H, and ater 3 ms to assume the clock signal o the transmission IC, so that the message can be sent with crystal accuracy..3.2 Output Matching and Power Setting The output power is set by the load impedance o the antenna. The maximum output power is achieved with a load impedance o Z Load,opt =(255+j192). There must be a low resistive path to V S to deliver the DC current. The delivered current pulse o the power ampliier is 9 ma and the maximum output power is delivered to a resistive load o 00 i the 1.0pF output capacitance o the power ampliier is compensated by the load impedance. An optimum load impedance o: Z Load = 00 j/(2 1.0pF) = (255 + j192) thus results or the maximum output power o 8dBm. The load impedance is deined as the impedance seen rom the Atmel T553C s, into the matching network. Do not conuse this large signal load impedance with a small signal input impedance delivered as input characteristic o RF ampliiers and measured rom the application into the IC instead o rom the IC into the application or a power ampliier. Less output power is achieved by lowering the real parallel part o 00 where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit o Figure -2. Note that the component values must be changed to compensate the individual board parasitics until the Atmel T553C has the right load impedance Z Load,opt = (255 + j192). Also the damping o the cable used to measure the output power must be calibrated out. Figure -2. Output Power Measurement at = 315MHz V S C 1 1nF L 1 Z Lopt 56nH C 2 3.3pF Z = 50Ω Power meter R in 50Ω Note: For 35MHz C 2 has to be changed to 2.pF. Application Circuit For the blocking o the supply voltage a capacitor value o C 3 = 68nF/XR is recommended (see Figure -3 on page and Figure - on page 8). C 1 and C 2 are used to match the loop antenna to the power ampliier where C 1 typically is 22pF/NP0 and C 2 is 10.8pF/NP0 (18pF + 2pF in series); or C 2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the Z Load,opt by using standard valued capacitors. C 1 orms together with the pins o Atmel T553C and the PCB board wires a series resonance loop that suppresses the 1 st harmonic, hence the position o C 1 on the PCB is important. Normally the best suppression is achieved when C 1 is placed as close as possible to the pins and. The loop antenna should not exceed a width o 1.5 mm, otherwise the Q-actor o the loop antenna is too high. L 1 ([50nH to 100nH) can be printed on PCB. C should be selected that the XTO runs on the load resonance requency o the crystal. Normally, a value o 12pF results or a 15pF load-capacitance crystal. 6
Figure -3. ASK Application Circuit ATARx9x T553C CP Power up/down PDF 32 5 6 1 VDD 20 S 8 3 2 GND ENABLE L1 C1 C C3 Loop Antenna C2 PA_ENABLE OSC1 S1 S2 CLK 1 LF PA VCO PLL XTO
Figure -. FSK Application Circuit S1 S2 ATARx9x 1 VDD S 20 BP2/T2O 18 OSC1 T553C Power up/down CLK ENABLE 1 8 32 PA_ENABLE GND 2 PDF C3 C2 CP 3 6 Loop Antenna C1 LF C5 L1 PA PLL VCO XTO 5 C Figure -5. ESD Protection Circuit CLK PA_ENABLE ENABLE GND 8
5. Absolute Maximum Ratings Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and unctional operation o the device at these or any other conditions beyond those indicated in the operational sections o this speciication is not implied. Exposure to absolute maximum rating conditions or extended periods may aect device reliability. Parameters Symbol Minimum Maximum Unit Supply voltage V S 5 V Power dissipation P tot 100 mw Junction temperature T j 150 C Storage temperature T stg 55 125 C Ambient temperature T amb 55 125 C Input voltage V maxpa_enable 0.3 (V S + 0.3) (1) V Note: 1. I V S + 0.3 is higher than 3.V, the maximum voltage will be reduced to 3.V. 6. Thermal Resistance Parameters Symbol Value Unit Junction ambient R thja 10 K/W. Electrical Characteristics V S = 2.0V to.0v, T amb = 0 C to 125 C unless otherwise speciied. Typical values are given at V S = 3.0V and T amb = 25 C. All parameters are reerred to GND (pin ). Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply current Power down, V ENABLE < 0.25V, 0 C to 85 C V PA-ENABLE < 0.25V, 0 C to +125 C V PA-ENABLE < 0.25V, 25 C (100% correlation tested) I S_O <10 350 na µa na Supply current Supply current Output power Output power variation or the ull temperature range Output power variation or the ull temperature range Power up, PA o, V S = 3V, V ENABLE > 1.V, V PA-ENABLE < 0.25V Power up, V S = 3.0V, V ENABLE > 1.V, V PA-ENABLE >1.V V S =3.0V, T amb =25 C, = 315MHz, Z Load = (255 + j192) T amb = 0 C to +85 C, V S = 3.0V V S = 2.0V T amb = 0 C to +125 C, V S = 3.0V V S = 2.0V, P Out = P Re + P Re I S 3..8 ma I S_Transmit 9 11.6 ma P Re 6.0 8.0 10.5 dbm P Re 1.5 P Re.0 P Re 2.0 P Re.5 Achievable output-power range Selectable by load impedance P Out_typ 0 8.0 dbm Note: 1. I V S is higher than 3.6V, the maximum voltage will be reduced to 3.6V. db db db db 9
. Electrical Characteristics (Continued) V S = 2.0V to.0v, T amb = 0 C to 125 C unless otherwise speciied. Typical values are given at V S = 3.0V and T amb = 25 C. All parameters are reerred to GND (pin ). Parameters Test Conditions Symbol Min. Typ. Max. Unit Spurious emission CLK = 0 /128 Load capacitance at pin CLK = 10pF O ±1 CLK O ± CLK other spurious are lower 55 52 dbc dbc Oscillator requency XTO (= phase comparator requency) XTO = 0 /32 = resonant requency o the, C M 10F, load capacitance selected accordingly T amb = 0 C to +85 C, T amb = 0 C to +125 C XTO 30 0 +30 +0 PLL loop bandwidth 250 khz Phase noise o phase comparator Reerred to PC = XT0, 25kHz distance to carrier 116 110 dbc/hz In loop phase noise PLL 25kHz distance to carrier 86 80 dbc/hz Phase noise VCO at 1MHz at 36MHz 9 125 90 121 ppm ppm dbc/hz dbc/hz Frequency range o VCO VCO 310 350 MHz Clock output requency (CMOS microcontroller compatible) 0 /128 MHz Voltage swing at pin CLK C Load 10pF V 0h V 0l V S 0.8 V S 0.2 1. Series resonance R o the crystal Rs 110 Capacitive load at pin XT0 pf FSK modulation requency rate Duty cycle o the modulation signal = 50% 0 32 khz ASK modulation requency rate Duty cycle o the modulation signal = 50% 0 32 khz Low level input voltage V Il 0.25 V ENABLE input High level input voltage V Ih V Input current high I In 20 µa PA_ENABLE input Low level input voltage High level input voltage Input current high Note: 1. I V S is higher than 3.6V, the maximum voltage will be reduced to 3.6V. V Il V Ih I In 1. 0.25 V S (1) 5 V V V V µa 10
8. Ordering Inormation Extended Type Number Package Remarks T553C-6AQJ-66 TSSOP8L Taped and reeled, Marking: 53C, Pb-ree Note: 1. J = 0 C to +125 C + lead-ree 9. Package Inormation Dimensions in mm +0.05 1-0.15 0.85±0.05 3±0.1 3±0.1 +0.06 0.31-0.0 0.65 nom. 0.1±0.05 3.8±0.3.9±0.1 +0.05 0.15-0.02 3 x 0.65 = 1.95 nom. 8 5 technical drawings according to DIN speciications 1 Package Drawing Contact: packagedrawings@atmel.com TITLE Package: TSSOP 8L 03/15/0 GPC DRAWING NO. REV. 6.53-5083.01-2 11
10. Revision History Please note that the ollowing page numbers reerred to in this section reer to the speciic revision mentioned, not to this document. Revision No. 510M-RKE-09/15 510L-RKE-03/1 510K-RKE-01/13 510J-RKE-12/08 510I-RKE-02/0 510H-RKE-09/05 510G-RKE-02/05 510F-RKE-02/05 History Section 8 Ordering Inormation on page 11 updated T553 in T553C on all pages substituted Section 8 Ordering Inormation on page 11 updated Section Features on page 1 changed Section 8 Ordering Inormation on page 11 updated Put datasheet in the newest template Section.3.1 Clock Pulse Take-over on page 5 updated Put datasheet in the newest template Pb-ree Logo on page 1 deleted Pb-ree Logo on page 1 added Put datasheet in the newest template Section 1 Description on page 1 updated Figure title Figure -2 on page 6 updated Table Electrical Characteristics on pages 9 to 10 updated Table Ordering Inormation on page 11 updated Table Absolute Maximum Ratings (page 8): row Input voltage added Table Absolute Maximum Ratings (page 8): table note 1 added Table Electrical Characteristics (page 10): row PA_ENABLE input updated Table Electrical Characteristics (page 10): table note 1 added Table Ordering Inormation (page 11): Remarks updated 12
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