A 4 GSample/s 8-bit ADC in 0.35 µm CMOS Ken Poulton, Robert Neff, Art Muto, Wei Liu, Andrew Burstein*, Mehrdad Heshami* Agilent Laboratories Palo Alto, California 1
Outline Background Chip Architecture Key Circuits Interleaved Clocks Front-end Track/Hold ADC Digital Circuits Calibration Results Summary 2
Application: Digital Oscilloscopes Probe Preamp ADC Memory System DUT Calibration Sources ADC Designer s scope block diagram System CPU Real time waveform acquisition Maximum sample rate Inputs band-limited to ~ F sample /4 ~ 8 bit resolution External CPU and calibration sources 3
Design Goals Goals: 4 GSample/s, 8 bit conversions 7 effective bits (ENOB) at low frequency > 5 ENOB at F in =1 GHz (F s /4) -1 db bandwidth of 1 GHz. Low enough power for standard packaging Approach: Use time-interleaved ADCs to get high sample rate Minimize the high-speed analog signal path Make all the circuits small for low power Take full advantage of offline calibration 4
ADC Chip Architecture Input Clock V in + - DLL Clock Gen 32 T/H+V/I 32 ADCs 32 RCs 4 muxes Radix Converters 8b +clk, 1GSa/s 32 time-interleaved pipeline ADCs at 125 MSa/s Net sample rate is 4 GSa/s 5
Background: Timing Error and ADC Resolution V in dv dt Fast signal converts a sample timing error (dt) to an apparent voltage error (dv). 6
ADC Effective Bits vs Timing Error Sinewave Effective bits 9 7 5 3 Otherwise Ideal ADC 1 ps rms 4 ps rms 16 ps rms 62.5 125 250 500 F in (MHz) 1000 2000 Rule of thumb: 1 ps / 1 GHz --> 7 effective bits 7
Clock Timing Errors Cycle/Cycle Errors (jitter) Thermal noise induced jitter Substrate and supply noise induced jitter Static Errors Clock and signal path mismatches (time of flight) Device and parasitic mismatches Design Approach Shorten total clock delay to reduce errors. Calibrate remaining static errors. 8
Direct Approach: 31 Stage DLL DLL Input Clock 125 MHz 31 stages, 250 ps/stage, total delay 8 ns... To Track/Hold Circuits Static timing errors: Error ~ total delay Supply noise coupling: Error ~ total delay Thermal jitter: Power ~ (total delay) 2 DLL meeting jitter spec would consume entire ADC power budget!! 9
DLL 500 MHz Clock PD Timing Generator Ring Cntrs /4 /4 /4 /4 /4 /4 /4 /4 Delay Adjusters... 32 Sampling Clocks (125 MHz) Max input edge to sampling edge delay: 2 ns ~ 1 ps jitter < 1 ps static error after cal 10
Simplified Input Track/Hold Clock V in V hold C hold To achieve highest bandwidth and linearity: ONLY 1 NMOS FET in signal path Restrict C hold to only T/H and load parasitics Low common mode input voltage Low-swing differential signal (250 mv peak) Fastest possible full-swing clock edge 2 GHz bandwidth, -50 db HD3 at 1 GHz 11
Interleaved Track/Hold Input Circuits Clk 0 V in... C hold 32 T/H Circuits (125 MSa/s) Clk 31 C hold Requirements 2 GHz input bandwidth to C hold Low parasitics on V in Kickback to V in must be independent of signal 12
Analog Front End Implementation Clk s Clk cc V in + - Clk rst V hold + V hold - V/I I out + I out - W W/2 W/2 Sample Charge Comp. Reset Parasitic-only hold capacitance (140 ff) Only 1 ns pulse width for Clk s Reset phase Transconductor (V/I) current output drives ADC 13
125 MSa/Sec 8-bit Full Nyquist ADC Key Attribute Reason Pipelined Architecture Low power Small area Low input capacitance 1 bit / Stage Highest speed pipeline Open-loop amplifiers Current mode signals (Switched current mirrors) Scale for thermal noise Making it work Fastest settling No explicit capacitors Small Area Smallest area and power Reduce Radix to 1.6 Digital Calibration Achieves Redundancy Corrects amplifier gain and offset errors. 14
Pipeline ADC Block Diagram Corrected Output (8 bits, binary) Radix Conversion Circuit Raw ADC output: 12 bits, Radix 1.6 De-skew latches Input Clock 1-bit quantizer 1 1-bit 1-bit quantizer quantizer 2 12 Input T/H Clock + _ FF DAC + - G Residue G=1.6 15 Only 1 comparator per stage
Current-Mode T/H and Gain I in I out Gain=M W M*W Good Linearity: Current mirrors with cascodes are 8 bit linear. Poor Accuracy: Gain and offset errors 16
Current-Mode ADC Stage Vbias DAC I in Gain=1.6 I out 17
Current-Mode Pipeline ADC State of the art speed/power ratio for an 8-bit ADC 125 MSa/s, full nyquist performance 80 mw total 20 mw V/I buffer 40 mw pipeline 20 mw radix converter Small Area 0.3 mm 2 18
Radix Converter - Principle of Operation Calculate and download bit weights during cal. Bit 11 weight 11 Bit 10 weight 10 Bit 9 weight 9 Σ Binary Output (8 bits) Bit 1 weight 1 Bit 0 weight 0 Output = b 11.w 11 + b 10.w 10 +... + b 1.w 1 + b 0.w 0 Look-up table is an alternative. This ADC uses a hybrid look-up/adder. 19
Supply and Substrate Noise Reduction Fully differential analog path Very low-noise digital logic family (SCL - Source Coupled Logic) Differential Logic Constant Supply Current Generates less noise than the ADC Comparators!! Differential output drivers Chip-level supply and substrate noise simulation for design verification. 20
What Needs To Be Calibrated? Clock 32 ADCs 32 RCs muxes DLL Timing Adjust Clock Gen 32 T/H+V/I Radix Converters Per-slice Gain + Offset DACs RC Bit Weights External Lookup Table Offline Calibration with DC and Pulse sources 21
Offline Calibration DC Linearity Calibration Use a DC ramp input, observe ADC radix bits Analog gain and offset trim per path Use least squares fit on a large record to find optimal bit weights and 3rd harmonic fit. Least squares fit minimizes INL Timing Calibration Apply a pulse train with fast edges Use an FFT to measure phase delay on each T/H Adjust time delays, and iterate Full ADC calibration takes about 3 minutes 22
ADC Chip Layout 16 RCs 16 Pipelines 16 T/H 16 T/H 16 Pipelines 16 RCs 7.1 mm x 4.0 mm 300,000 FETs 4.6 W 23
ADC 256-Ball TBGA Package Copper body Controlled-impedance lines Custom layout, standard ball pattern 24
ADC Code (LSBs) Acquisition Before Calibration 100 80 60 40 20 0-20 -40-60 -80-100 0 0.5 1 1.5 2 2.5 Time (µs) ~ 5 effective bits 25
150 Acquisition With Calibration 100 ADC Code 50 0-50 -100-150 0 5 10 15 20 25 30 35 Equivalent Time (ns) F s =4000 MSa/sec F in =30.27 MHz 7.0 effective bits 26
Error (LSBs) ADC Code 4 2 0-2 -4 100 0-100 Acquisition With Calibration Noise: 0.6 LSB rms 0 5 10 15 20 25 30 35 Equivalent Time (ns) F s =4000 MSa/sec F in =30.27 MHz 7.0 effective bits 27
Error (LSBs) ADC Code Full Calibration, With 1 GHz Input 4 2 0-2 -4 100 0-100 0 0.5 1 Equivalent Time (ns) F s =4000 MSa/s F in =1026.4 MHz 6.35 effective bits 28
Static Linearity INL (LSBs) DNL (LSBs) 1 0.5 0-0.5-1 0.2 0.1 0-0.1 raw INL with Lookup table -0.2-150 -100-50 0 50 100 150 ADC code 29
ADC Effective Bits vs Input Frequency Accuracy (Effective Bits) 7 6 5 4 3 2 4.0 GSample/sec 5.9 GSample/sec 6.2 @1 GHz 1 Input amplitude ~95% of full scale 0 40M 100M 200M 400M 1G 2G 4G Frequency (Hz) 1.2 ps rms clock error 30
Amplitude Response (db) 1 0-1 -2-3 -4 ADC Amplitude Response -5 Measurement -6 Simulation 100M 200M 400M 1G 2G Input Frequency (Hz) -1 db at 1.3 GHz -3 db at 1.6 GHz 31
ADC Chip - Key Specs Measured Units Nominal Sample Rate 4 GSa/s Sample Rate Range 0.1-5.9 GSa/s Resolution 8 bits 3 db Bandwidth 1.6 GHz Accuracy 30 MHz 1 GHz 7.0 6.2 effective bits (ENOB) Noise 0.6 LSB rms INL / DNL ±0.3 / ±0.2 LSB Power 4.6 W at 3.3 V IC Technology 0.35 µm CMOS Chip Size 7.14 x 4.04 mm 2 Transistors 300,000 Package 256 ball TBGA 32
Monolithic ADCs ENOB at F s /4 7 6 5 4 CMOS 8 bit CMOS 6 bit Bipolar 8 bit GaAs HBT 6 bit This work 100M 400M 1G 2G 4G Sample Rate (F s ) (Hz) 33
Features: Results: Summary Interleaving of 32 ADCs Precision timing generator for 32 clock phases Current-mode pipeline provides a superior speed/ power ratio Extensive calibration to achieve accuracy 2x lower power/gsample than any reported GSa/s 8-bit ADC Highest reported clock rate for 6-8 bit CMOS ADCs Highest reported accuracy at 4 GSa/s 34