TVS (transient voltage suppressor) Bi-directional, 18 V (AC), 13 V (DC),.3 pf, 21, RoHS and halogen free compliant Feature list ESD/transient protection of high speed data lines according to: - IEC61-4-2 (ESD): ±15 kv (air/contact discharge) - IEC61-4-4 (EFT): ±2 kv/±4 A (5/5 ns) - IEC61-4-5 (Surge): ±2 A (8/2 μs) Bi-directional working voltage up to: V RWM = ±18 V (AC), ±13 V (DC) Line capacitance: C L =.3 pf (typical) at f = 1 MHz Clamping voltage: V CL = 32 V (typical) at I TLP = 16 A with R DYN =.85 Ω (typical) Very low reverse current: I R < 1 na (typical) Small form factor SMD size 21 and low profile (.58 mm x.28 mm x.15 mm), for further package information please refer to application note AN392 [4] Bi-directional, symmetric I/V characteristic for optimized design and assembly, recommendations for PCB assembly see [2] Potential applications ESD protection of RF signal lines in Near Field Communication (NFC) applications [3] Product validation Qualified for industrial applications according to the relevant tests of JEDEC47/2/22 Device information a ) Pin configuration b ) Schematic diagram Figure 1 Table 1 Pin configuration and schematic diagram Part information Type Package Configuration Marking code WLL-2-1 1 line, bi-directional K 1) 1 The device has no marking on the device backside. The marking code is on pad side. Datasheet Please read the Important Notice and Warnings at the end of this document Revision 1.5 www.infineon.com
Table of contents Table of contents Feature list............................................................................. 1 Potential applications.................................................................. 1 Product validation......................................................................1 Device information..................................................................... 1 Table of contents....................................................................... 2 1 Maximum ratings....................................................................... 3 2 Electrical characteristics................................................................ 4 3 Typical characteristic diagrams......................................................... 6 4 Application information............................................................... 12 5 Package information.................................................................. 13 5.1 WLL-2-1 package....................................................................... 13 6 References............................................................................ 14 Revision history....................................................................... 14 Disclaimer............................................................................ 15 Datasheet 2 Revision 1.5
Maximum ratings 1 Maximum ratings Note: T A = 25 C, unless otherwise specified. Table 2 Maximum ratings Parameter Symbol Values Unit Reverse working voltage V RWM ±18 1) ±13 2) V ESD discharge 3) V ESD (contact) ±15 kv V ESD (air) ±15 Peak pulse power 4) P PK 53 W Peak pulse current 4) I PP ±2 A Operating temperature range T OP -55 to 125 C Storage temperature T stg -65 to 15 C Attention: Stresses above the maximum values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings. Exceeding only one of these values may cause irreversible damage to the component. 1 For RF peak voltage (NFC) 2 For DC voltage 3 V ESD according to IEC61-4-2 (R = 33 Ω, C = 15 pf discharge network) 4 Stress pulse: 8/2 μs current waveform according to IEC61-4-5 Datasheet 3 Revision 1.5
Electrical characteristics 2 Electrical characteristics Note: T A = 25 C, unless otherwise specified. Device is electrically symmetrical. IF I PP VF... Forward voltage IF... Forward current VR... Reverse voltage IR... Reverse current I TLP R DYN ΔV ΔI ΔI ΔV VR V CL V TLP V t1 ΔV V h ΔI V RWM R DYN I R ΔV ΔI I T I R I T I PP I TLP V RWM V h V t1 V CL V TLP VF RDYN... Dynamic resistance VRWM... Reverse working voltage max. Vt1... Trigger voltage Vh... Holding voltage VCL... Clamping voltage VTLP... TLP voltage IR... Reverse leakage current Ipp... Peak pulse current ITLP... TLP current IT... Test current Figure 2 Definitions of electrical characteristics IR Diode_Characteristic_Curve_with_snapback_Bi-directional.svg Datasheet 4 Revision 1.5
Electrical characteristics Table 3 DC characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Trigger voltage 1) V t1 2 22 25 V Holding voltage V h 13 17 21 V I T = 1 ma Reverse current I R <1 3 na V R = 18 V Table 4 AC characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Line capacitance C L.15.3.5 pf V R = V, f = 1 MHz.3 V R = V, f = 1 GHz Table 5 ESD and Surge characteristics Parameter Symbol Values Unit Note or test condition Min. Typ. Max. Clamping voltage 2) V CL 32 V I TLP = 16 A, t p = 1 ns Clamping voltage 3) 18.5 I PP = 1 A, t p = 8/2 µs Dynamic resistance 2) R DYN.85 Ω t p = 1 ns 1 Verified by design 2 Please refer to Application Note AN21 [1], TLP parameters: Z = 5 Ω, t p = 1 ns, t r =.6 ns 3 Stress pulse: 8/2 μs current waveform according to IEC61-4-5 Datasheet 5 Revision 1.5
Typical characteristic diagrams 3 Typical characteristic diagrams Note: T A = 25 C, unless otherwise specified. I R [A] 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-1 1-11 1-12 1-13 1-14 -18-15 -12-9 -6-3 3 6 9 12 15 18 V R [V] Figure 3 Reverse leakage current: I R = f(v R ) 1.9.8.7 C L [pf].6.5.4.3.2.1 1 MHz 1 GHz -18-15 -12-9 -6-3 3 6 9 12 15 18 V R [V] Figure 4 Line capacitance: C L = f(v R ), f = 1 MHz, 1 GHz Datasheet 6 Revision 1.5
Typical characteristic diagrams 14 12 Scope: 6 GHz, 2 GS/s V CL [V] 1 8 6 4 2 V CL-max-peak = 122 V V CL-3ns-peak = 26 V -2-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 5 Clamping voltage (ESD): V CL = f(t), 8 kv positive pulse (according to IEC61-4-2) Scope: 6 GHz, 2 GS/s -25 V CL [V] -5-75 -1-125 V CL-max-peak = -124 V V CL-3ns-peak = -26 V -5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 6 Clamping voltage (ESD): V CL = f(t), 8 kv negative pulse (according to IEC61-4-2) Datasheet 7 Revision 1.5
Typical characteristic diagrams V CL [V] 18 16 14 12 1 8 6 4 2 Scope: 6 GHz, 2 GS/s V CL-max-peak = 157 V V CL-3ns-peak = 46 V -2-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 7 Clamping voltage (ESD): V CL = f(t), 15 kv positive pulse (according to IEC61-4-2) 2 Scope: 6 GHz, 2 GS/s V CL [V] -2-4 -6-8 -1-12 -14-16 V CL-max-peak = -15 V V CL-3ns-peak = -46 V -18-5 5 1 15 2 25 3 35 4 45 t p [ns] Figure 8 Clamping voltage (ESD): V CL = f(t), 15 kv negative pulse (according to IEC61-4-2) Datasheet 8 Revision 1.5
Typical characteristic diagrams 2 R DYN 1 15 R DYN =.85 Ω 7.5 1 5 5 2.5 I TLP [A] Equivalent V IEC [kv] -5-2.5-1 -5-15 R DYN =.85 Ω -7.5-2 -1-4 -35-3 -25-2 -15-1 -5 5 1 15 2 25 3 35 4 V TLP [V] Figure 9 Clamping voltage (TLP): I TLP = f(v TLP ) [1] Datasheet 9 Revision 1.5
Typical characteristic diagrams 2.5 2 1.5 1.5 I PP [A] -.5-1 -1.5-2 -2.5-25 -2-15 -1-5 5 1 15 2 25 V CL [V] Figure 1 Clamping voltage (Surge): I PP = f(v CL ) according to IEC61-4-5 [1] Datasheet 1 Revision 1.5
Typical characteristic diagrams 1 Insertion Loss ( S 21 ) [db] 2 3 4 5 6 7 8 9 1 1-2.1 1 1 Frequency [GHz] Figure 11 Insertion loss versus frequency in a 5 Ω system Datasheet 11 Revision 1.5
Application information 4 Application information Figure 12 Bi-directional ESD/transient protection for NFC front end [3] Datasheet 12 Revision 1.5
Package information 5 Package information 5.1 WLL-2-1 package Note: Dimensions in mm. Top view Bottom view.15±.1.28±.3 2.36 (.16) 1.58 ±.3.26±.2.2 ±.2 SG-WLL-2-1-PO V1 Figure 13 WLL-2-1 package outline.32.27.24.19.19.19.62.57.14.24 Figure 14 WLL-2-1 footprint Copper Solder mask Stencil apertures SG-WLL-2-1-FP V1.23.68 8 2.35.21 SG-WLL-2-1-TP V2 Figure 15 WLL-2-1 packing Figure 16 WLL-2-1 marking example (see Device information) Datasheet 13 Revision 1.5
References 6 References [1] Infineon AG - Application note AN21: Effective ESD protection design at system level using VF-TLP characterization methodology [2] Infineon AG - Recommendation for Printed Circuit Board Assembly of Infineon WLL Packages http://www.infineon.com/packageinformation_wll [3] Infineon AG - Application note AN244: Tailored ESD protection for the NFC frontend [4] Infineon AG - Application note AN392: TVS diodes in ChipScalePackage reduce size and save cost Revision history Revision history: Rev. 1.4. 217-9-28 Page or Item Subjects (major changes since previous revision) Revision 1.5, Table 3 updated Minor editorial changes Datasheet 14 Revision 1.5
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