What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB

Similar documents
Solid State Devices & Circuits. 18. Advanced Techniques

Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits

Design of High-Speed Op-Amps for Signal Processing

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10

Topology Selection: Input

Chapter 12 Opertational Amplifier Circuits

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

EECE488: Analog CMOS Integrated Circuit Design Set 7 Opamp Design

Atypical op amp consists of a differential input stage,

Basic OpAmp Design and Compensation. Chapter 6

Advanced Operational Amplifiers

A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

Basic OpAmp Design and Compensation. Chapter 6

EE 501 Lab 4 Design of two stage op amp with miller compensation

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407

Chapter 13: Introduction to Switched- Capacitor Circuits

Design of Miller Compensated Two-Stage Operational Amplifier for Data Converter Applications

Comparative Analysis of Compensation Techniques for improving PSRR of an OPAMP

University of Michigan, EECS413 Final project. A High Speed Operational Amplifier. 1. A High Speed Operational Amplifier

Design of Low Voltage Low Power CMOS OP-AMP

A Low Power, 8-Bit, 5MS/s Digital to Analog Converter for Successive Approximation ADC

Design of Analog CMOS Integrated Circuits

Design and implementation of two stage operational amplifier

Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

ECEN 5008: Analog IC Design. Final Exam

A new class AB folded-cascode operational amplifier

Class-AB Low-Voltage CMOS Unity-Gain Buffers

Design and Analysis of Low Power Two Stage CMOS Op- Amp with 50nm Technology

Design of Rail-to-Rail Op-Amp in 90nm Technology

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

International Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS)

Design for MOSIS Education Program

High Voltage Operational Amplifiers in SOI Technology

DESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN WITH LATCH NETWORK. Thota Keerthi* 1, Ch. Anil Kumar 2

Chapter 4 Single-stage MOS amplifiers

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852

Analog Integrated Circuit Configurations

A 0.8V, 7A, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18m CMOS

Low Quiescent Power CMOS Op-Amp in 0.5µm Technology

Microelectronics Part 2: Basic analog CMOS circuits

Operational Amplifiers

Revision History. Contents

Design and Layout of Two Stage High Bandwidth Operational Amplifier

AN increasing number of video and communication applications

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

2. Single Stage OpAmps

Rail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation

Op-Amp Design Project EE 5333 Analog Integrated Circuits Prof. Ramesh Harjani Department of ECE University of Minnesota, Twin Cities Report prepared

Operational Amplifier with Two-Stage Gain-Boost

Designing CMOS folded-cascode operational amplifier with flicker noise minimisation

Building Blocks of Integrated-Circuit Amplifiers

Design and Implementation of High Gain, High Bandwidth CMOS Folded cascode Operational Transconductance Amplifier

250 MHz CMOS Rail-to-Rail IO OpAmp: Structural Design Approach. Texas Instruments Inc.- Tucson (former Burr-Brown Inc.)

Low-output-impedance BiCMOS voltage buffer

Design Of Two Stage CMOS Op-Amp With Low Power And High Slew Rate.

A PSEUDO-CLASS-AB TELESCOPIC-CASCODE OPERATIONAL AMPLIFIER

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

@IJMTER-2016, All rights Reserved 333

0.85V. 2. vs. I W / L

Design and Analysis of High Gain CMOS Telescopic OTA in 180nm Technology for Biomedical and RF Applications

Analysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications

A Compact 2.4V Power-efficient Rail-to-rail Operational Amplifier. Strong inversion operation stops a proposed compact 3V power-efficient

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1

Ultra Low Static Power OTA with Slew Rate Enhancement

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Design of High Gain Low Voltage CMOS Comparator

Design and Simulation of Low Voltage Operational Amplifier

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

Reading. Lecture 33: Context. Lecture Outline. Chapter 9, multi-stage amplifiers. Prof. J. S. Smith

DESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)

Analog Integrated Circuit Design Exercise 1

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage

ISSCC 2004 / SESSION 26 / OPTICAL AND FAST I/O / 26.8

Low Voltage Standard CMOS Opamp Design Techniques

Cascode Bulk Driven Operational Amplifier with Improved Gain

A 16Ω Audio Amplifier with 93.8 mw Peak loadpower and 1.43 quiscent power consumption

HIGH GAIN, HIGH BANDWIDTH AND LOW POWER FOLDED CASCODE OTA WITH SELF CASCODE AND DTMOS TECHNIQUE

Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier

Analog Integrated Circuits. Lecture 7: OpampDesign

Current Mirrors. Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 4-1

Design of a low voltage,low drop-out (LDO) voltage cmos regulator

DESIGN OF TWO-STAGE CLASS AB CASCODE OP-AMP WITH IMPROVED GAIN

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching

Low Power Op-Amp Based on Weak Inversion with Miller-Cascoded Frequency Compensation

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT

Design of Low Voltage, Low Power Rail to Rail Operational Transconductance Amplifier with enhanced Gain and Gain Bandwidth Product

Experiment 1: Amplifier Characterization Spring 2019

TWO AND ONE STAGES OTA

F9 Differential and Multistage Amplifiers

EE 501 Lab 11 Common mode feedback (CMFB) circuit

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

ECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)

Transcription:

Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points) Multiple Choice - Choose BEST Answer (a) (b) (c) (d) (e) The difference between opamp output phase and -180 O at unity gain is called? (i) gain margin (ii) unity gain phase difference (iii) phase margin (iv) unity gain crossover frequency Latched comparators are usually very fast because they? (i) have large open loop gain (ii) have positive feedback (iii) have low paracitic resistance (iv) have diode connected transistors What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB For the basic two stage CMOS opamp why do we use a transistor for lead compensation (i) lower power consumption (ii) better matching (iii) less noise (iv) fewer connections Which of the following could be used to improve the accuracy of a basic MOS sample and hold circuit? (v) reduce the sampling capacitor size (vi) use a single ended configuration (vii) increase the sampling transistor size (viii) increase the output buffer input capacitance 2. (20 points) Short Answer (a) In the basic two stage opamp, is it better to have the first stage differential pair implemented with NMOS or PMOS transistors? Why?

(b) Why would you use a single stage folded cascode opamp instead of the basic two stage CMOS opamp you studied? (c) When and Why do we need a common mode feedback circuit? Draw a (transistor level) common mode feedback circuit. (d) Why is usually important to make the sampling clock rise/fall time small in a sample and hold circuit? (e) Why do we use a preamp in a track and latch comparator? Draw a circuit diagram of a simple track and latch comparator and identify the preamp and latch stages.

(f) Why do we use wide swing current mirrors? What is their advantage? Draw a circuit diagram of a simple wide swing current mirror. (g) What is 1/f noise and how can we reduce it in CMOS circuits? (h) Why do we tend not to use minimum channel length transistors in analog circuits? When would you use minimum channel length transistors in analog circuits? (i) What is the purpose of the compensation capacitor CC in the basic two stage opamp? (j) How can we reduce charge injection in clocked comparators?

3. (5 points) Given the following opamp circuit and transistor parameters. Ignoring the body effect, assume ID5 = 100 ua, all transistor lengths are 1.6 m, +/- 5V power supplies and CC = 10 pf. (a) what is the output voltage range of the opamp, (b) estimate the range of the common mode input voltage.

4. (5 points) What is this circuit? Explain the purpose of each component in the circuit. 5. (5 points) For the circuit below. (a) What type of circuit is this? (b) Explain how it can elliminate the input offset voltage of the opamp (c) What effect does the opamp 1/f noise have on this circuit?

6. (5 points) For the circuit shown below, determine the low-frequency small-signal output vo as a function of v1,v2, the MOSFET transconductance gm, R, and the MOSFET drain-source resistance rds. Assume all devices are in saturation. Assume rds is the same for all MOSFETs. Assume gm is the same for all MOSFETs.