EE 330 Lecture 11 Capacitances in Interconnects Back-end Processing
Exam 1 Friday Sept 21 Students may bring 1 page of notes HW assignment for week of Sept 16 due on Wed Sept 19 at beginning of class No 5:00 p.m extension so solutions can be posted Those with special accommodation needs, please send me an email message or contact me so arrangements can be made Review session to be determined
Review from Last Lecture Dual-Damascene Process Patterning of Copper Copper Deposited on Surface CMP Target
Review from Last Lecture Resistance in Interconnects W L R=R [L / W] The Number of Squares approach to resistance determination in thin films 1 2 3 21 N S = 21 L / W=21 R=R N S
Review from Last Lecture Resistance in Interconnects (can be used to build resistors!) Serpentine often used when large resistance required Polysilicon or diffusion often used for resistor creation Effective at managing the aspect ratio of large resistors May include hundreds or even thousands of squares
Review from Last Lecture Resistance in Interconnects (can be used to build resistors!) d 2 2 d 1 Area requirements determined by both minimum width and minimum spacing design rules
Capacitance in Interconnects C=C D A C D is the capacitance density and A is the area of the overlap
Capacitance in Interconnects Metal 2 A 3 Metal 1 A 1 A 5 A 2 A 4 Substrate M 2 M 1 SUB C 12 C 2S C 1S Equivalent Circuit C 12 =CD 12 A 5 C 1S =CD 1S (A 1 +A 2 +A 5 ) C 2S =CD 2S (A 3 +A 4 )
Example Two metal layers, Metal 1 and Metal 2, are shown. Both are above field oxide. Determine the capacitance between Metal 1 and Metal 2. Assume the process has capacitance densities from M 1 to substrate of.05ff/u 2, from M 1 to M 2 of.07ff/u 2 and from M 2 to substrate of.025ff/u 2. 30µ 10µ Metal 1 Metal 2 30µ 30µ 10µ 30µ
Example Solution 30µ 10µ 30µ 30µ 10µ 30µ A C1C2 2 2 20μ 400μ 30µ The capacitance density from M 1 to M 2 is.07ff/u 2 2 2 C12 AC1C2 CD12 400 0.07fF/ 28fF
Capacitance and Resistance in Interconnects See MOSIS WEB site for process parameters that characterize parasitic resistances and capacitances www.mosis.org
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. Assume a 0.18u process. 0.6µ POLY 800µ R =n R POLY SQ SH C P-SUB =A C R SH =? R DPS =? DPS
For 0.18u process R SH =7.7Ω/ C DPS =103 af/µ 2
Example For 0.18u process Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ POLY n SQ 800 06. 1333 800µ A= 0. 6 800 480 2 R =n R =23.5 1333=31.3KΩ POLY SQ SH 2-2 C =A C =480μ 84aFμ =40.3fF P-SUB DPS
Example Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ Metal 1 800µ
For 0.18u process R SH =0.08Ω/ C DPS =39 af/µ 2
Example For 0.18u process Determine the resistance and capacitance of a Poly interconnect that is 0.6u wide and 800u long and compare that with the same interconnect if M 1 were used. 0.6µ Metal 1 n SQ 800 06. 1333 800µ A= 0. 6 800 480 2 R =n R =0.08 1333=107Ω M1 SQ SH 2 2 C =A C =480μ 39aFμ =18.7fF M1-SUB DM1S
IC Fabrication Technology Crystal Preparation Masking Photolithographic Process Deposition Etching Diffusion Ion Implantation Oxidation Epitaxy Polysilicon Contacts, Interconnect and Metalization Planarization
Planarization Planarization used to keep surface planar during subsequent processing steps Important for creating good quality layers in subsequent processing steps Mechanically planarized
Back End Front End Generic Process Flow Wafer Fabrication Mask Fabrication Epitaxy Grow or Apply Photoresist Deposit or Implant Etch Strip Planarization Wafer Probe Wafer Dicing Die Attach Wire Attach (bonding) Package Test Ship
Front End Process Integration for Fabrication of ICs Once for each mask Wafer Fabrication Mask Fabrication Epitaxy Photoresist Deposit or Implant Etch Strip Planarize Back End Processing
Front-End Process Flow Front-end processing steps analogous to a recipe for manufacturing an integrated circuit Recipes vary from one process to the next but the same basic steps are used throughout the industry Details of the recipe are generally considered proprietary
Back-End Process Flow Wafer Probe Wafer Dicing Die Attach Wire Attach (bonding) Package Test Ship
www.renishaw.com Wafer Dicing
Die Attach 1. Eutectic 2. Pre-form 3. Conductive Epoxy
Electrical Connections (Bonding) Wire Bonding Bump Bonding
Wire Bonding Wire gold or aluminum 25 in diameter
Wire Bonding Excellent Annimation showing process at : http://www.kns.com/_flash/cap_bonding_cycle.swf
Wire Bonding Ball Bond Wedge Bond www.kns.com
www.kns.com Ball Bonding Steps
Ball Bonding Tip Approx 25µ
Wire Bonding Ball Bond Termination Bond Ball Bond Photograph
www.secap.org Bump Bonding
Packaging 1. Many variants in packages now available 2. Considerable development ongoing on developing packaging technology 3. Cost can vary from few cents to tens of dollars 4. Must minimize product loss after packaged 5. Choice of package for a product is serious business 6. Designer invariably needs to know packaging plans and package models
www.necel.com Packaging
Packaging www.necel.com
Pin Pitch Varies with Package Technology http://www.electroiq.com/index/display/packaging-article- display/234467/articles/advanced-packaging/volume- 14/issue-8/features/the-back-end-process/materials-andmethods-for-ic-package-assemblies.htm From Wikipedia, Sept 20, 2010 http://en.wikipedia.org/wiki/list_of_chip_carriers
Many standard packages available today: http://www.interfacebus.com/design_pack_types.html
Considerable activity today and for years to come on improving packaging technology Multiple die in a package Three-dimensional chip stacking Multiple levels of interconnect in stacks Through silicon via technology Power and heat management Cost driven and cost constrained
The following few slides come from a John Lau presentation
Back-End Process Flow Wafer Probe Wafer Dicing Die Attach Wire Attach (bonding) Package Test Ship
Testing of Integrated Circuits Bench testing used to qualify parts for production Most integrated circuits are tested twice during production Wafer Probe Testing Quick test for functionality Usually does not include much parametric testing Relatively fast and low cost test Package costs often quite large Critical to avoid packaging defective parts Packaged Part Testing Testing costs for packaged parts can be high Extensive parametric tests done at package level for many parts Data sheet parametrics with Max and Min values are usually tested on all Ics Data sheet parametrics with Typ values are seldom tested Occasionally require testing at two or more temperatures but this is costly Critical to avoid packaging defective parts
Bench Test Environment Photos from www postings and Google image search 62
Bench Test Environment Test LAB Photo courtesy of Texas Instruments 63
Probe Test Probes on section of probe card Photos from www postings and Google image search 64
Probe Test Pad showing probe marks Pad showing bonding wire Die showing wire bonds to package cavity Photos from www postings and Google image search 65
Probe Test Production probe test facility Goal to Identify defective die on wafer Photos from www postings and Google image search 66
Work Station Final Test Typical ATE System (less handler) Main Frame ATE Automated Test Equipment (ATE) Test Head
Device Interface Board - DIB (Load Board) DIB Cavity (for DUT) DIBs Vary Considerably from one ATE Platform to another and are often personalized for a particular DUT Socket (Contactor)
Octal Site DIB Flex Octal (Teradyne) Bottom Top
Final Test Typical ATE Configuration Handler Tester Test Head Atlas (SSI Robotics)
End of Lecture 11