2 3 6 7 8 9 39 32 3 FEATURES High linearity: supports modulations to 2 QAM Rx IF range: 8 MHz to MHz Rx RF range: 8 MHz to MHz Rx power control: 8 db SPI programmable bandpass filters SPI controlled interface -lead, 6 mm 6 mm LFCSP package APPLICATIONS Point to point communications Satellite communications Wireless microwave backhaul systems Intermediate Frequency Receiver, 8 MHz to MHz GENERAL DESCRIPTION The is a highly integrated intermediate frequency (IF) receiver chip that converts radio frequency (RF) input signals ranging from 8 MHz to MHz down to a single-ended intermediate frequency (IF) signal of MHz at its output. The IF receiver chip is housed in a compact 6 mm 6 mm LFCSP package and supports complex modulations up to 2 QAM. The device includes two variable gain amplifiers (VGAs), three power detectors, a programmable automatic gain control (AGC) block, and selected integrated band-pass filters with MHz, 28 MHz, 6 MHz, and 2 MHz bandwidth. The also supports baseband IQ interfaces after the mixer so that the chips can be used in the full outdoor units (ODU) configuration. The supports all standard microwave frequency bands from 6 GHz to 2 GHz. FUNCTIONAL BLOCK DIAGRAM REF_CLK_P RST HMC8 38 SDO 37 SDI 36 SCLK 3 SEN 3 LON 33 LOP IRM_Q_N IRM_Q_P DVDD AMP2_P 2 SPI OTP VDDV 29 IRM_I_N AMP2_N 3 28 IRM_I_P VCC_FILTER FILTER2P VCC_AMP3 6 FILTER MHz 28MHz 6MHz 2MHz 27 VCC_IRM 26 VCC_VGA_BALUN 2 VCC_VGA GND VCC_BB 7 8 AGC 2 FILTERP 23 VCC_AMP GND2 9 22 AMP VGA_EXT_CAP 2 GND RX_OUT VCC_VGA3 AUX_OUT PD3_IN PD3_OUT_RSSI VC_VGA_IF_CAP VC_VGA_RF_CAP VCC_PD PD_OUT RFIN PACKAGE BASE GND 3867- Figure. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 62-96, U.S.A. Tel: 78.329.7 6 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
TABLE OF CONTENTS Features... Applications... General Description... Functional Block Diagram... Revision History... 2 Specifications... 3 Electrical Characteristics: 8 MHz to 8 MHz RF Frequency Range... 3 Electrical Characteristics: 8 MHz to 28 MHz RF Frequency Range... 3 Electrical Characteristics: 28 MHz to MHz RF Frequency Range... Absolute Maximum Ratings... 6 ESD Caution... 6 Pin Configuration and Function Descriptions... 7 Typical Performance Characteristics...9 External AGC Configuration...9 Internal AGC Configuration... 6 Theory of Operation... 8 Register Array Assignments and Serial Interface... 8 Register Descriptions... Register Array Assignments... Applications Information... 2 Schematic/Typical Application Circuit... 2 Evaluation Printed Circuit Board (PCB)... 2 Outline Dimensions... 27 Ordering Guide... 27 REVISION HISTORY /6 v.6 to Rev. A This Hittite Microwave Products data sheet has been reformatted to meet the styles and standards of Analog Devices, Inc. Updated Format... Universal Added Pin Configuration Diagram, Renumbered Sequentially... 7 Added Ordering Guide... 22 /6 v.6: Initial Version Rev. A Page 2 of 27
SPECIFICATIONS TA = 2 C, IF frequency = MHz, local oscillator (LO) input signal level = dbm, RF input signal level = 8 dbm per tone, filter bandwidth = 6 MHz, IF gain limit (decimal) = 7, sideband select = lower sideband, AGC select = external AGC, unless otherwise noted, see the Typical Performance Characteristics section. ELECTRICAL CHARACTERISTICS: 8 MHz TO 8 MHz RF FREQUENCY RANGE Table. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 6 MHz IF Frequency Range 8 MHz RF INPUT INTERFACE Input Impedance Ω Return Loss db IF OUTPUT INTERFACE Input Impedance Ω Return Loss 8 3 db LO INPUT INTERFACE Input Impedance Ω Return Loss 2 9 db DYNAMIC PERFORMANCE Power Conversion Gain 8 86 db RF VGA Dynamic Range 2 db IF VGA Dynamic Range 9 db Image Rejection 36 dbc Noise Figure at PIN (One Tone) 8 db Output Third-Order Intercept (OIP3) 6 dbm Output db Compression Point (OPdB) 7 dbm LO Leakage at the IF Input 8 26 dbm LO Leakage at the RF Input 7 7 dbm RF Leakage at the IF Output 68 6 dbm POWER SUPPLY Supply Voltage VCCX 3.3 V VCC VGA 3.3 V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. ELECTRICAL CHARACTERISTICS: 8 MHz TO 28 MHz RF FREQUENCY RANGE Table 2. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 6 MHz IF Frequency Range 8 MHz RF INPUT INTERFACE Input Impedance Ω Return Loss 2 db Rev. A Page 3 of 27
Parameter Min Typ Max Unit IF OUTPUT INTERFACE Input Impedance Ω Return Loss 8 3 db LO INPUT INTERFACE Input Impedance Ω Return Loss 7 db DYNAMIC PERFORMANCE Power Conversion Gain 77 8 db RF VGA Dynamic Range 7 db IF VGA Dynamic Range 9 db Image Rejection 36 dbc Noise Figure at PIN (One Tone) 7 db Output Third-Order Intercept (OIP3) 8 dbm Output db Compression Point (OPdB) 7 dbm LO Leakage at the IF Input dbm LO Leakage at the RF Input 73 66 dbm RF Leakage at the IF Output 73 6 dbm POWER SUPPLY Supply Voltage VCCX 3.3 V VCC VGA 3.3 V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. ELECTRICAL CHARACTERISTICS: 28 MHz TO MHz RF FREQUENCY RANGE Table 3. Parameter Min Typ Max Unit OPERATING CONDITIONS LO Frequency Range 26 MHz IF Frequency Range 8 MHz RF INPUT INTERFACE Input Impedance Ω Return Loss 3 db IF OUTPUT INTERFACE Input Impedance Ω Return Loss 8 3 db LO INPUT INTERFACE Input Impedance Ω Return Loss 7 db DYNAMIC PERFORMANCE Power Conversion Gain 72 82 db RF VGA Dynamic Range 3 7 db IF VGA Dynamic Range 9 db Image Rejection 38 dbc Noise Figure at PIN (One Tone) 8 db Output Third-Order Intercept (OIP3) 2 22 dbm Rev. A Page of 27
Parameter Min Typ Max Unit Output db Compression Point (OPdB) 7 2 dbm LO Leakage at the IF Input 6 8 dbm LO Leakage at the RF Input 66 62 dbm RF Leakage at the IF Output 72 6 dbm POWER SUPPLY Supply Voltage VCCX 3.3 V VCC VGA 3.3 V Supply Current VCCX 6 ma VCC VGA μa VCC VGA = VC_VGA_IF + VC_VGA_RF can be adjusted from 3.3 V (minimum ATTEN) to V (maximum ATTEN) to control the IF and RF VGA in external AGC mode. Rev. A Page of 27
ABSOLUTE MAXIMUM RATINGS Table. Parameter RF Input LO Input VCCX Maximum Junction Temperature to Maintain Million Hour MTTF Thermal Resistance (RTH), Junction to Ground Paddle Temperature Operating Storage Maximum Peak Reflow Temperature (MSL3) Rating dbm dbm. V to +. V.3 V to +3.6 V C. C/W C to +8 C 6 C to + C 26 C ESD Sensitivity (Human Body Model) V (Class 2) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A Page 6 of 27
2 3 6 7 8 9 39 38 37 36 3 3 33 32 3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS REF_CLK_P RST SDO SDI SCLK SEN LON LOP IRM_Q_N IRM_Q_P DVDD AMP2_P 2 AMP2_N 3 VCC_FILTER FILTER2P VCC_AMP3 6 GND 7 VCC_BB 8 GND2 9 VGA_EXT_CAP HMC8 TOP VIEW (Not to Scale) VDDV 29 IRM_I_N 28 IRM_I_P 27 VCC_IRM 26 VCC_VGA_BALUN 2 VCC_VGA 2 FILTERP 23 VCC_AMP 22 AMP 2 GND Table. Pin Function Descriptions Pin No. Mnemonic Description RX_OUT VCC_VGA3 AUX_OUT PD3_IN PD3_OUT_RSSI VC_VGA_IF_CAP VC_VGA_RF_CAP VCC_PD PD_OUT RFIN NOTES. EXPOSED PAD. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE THERMAL AND ELECTRICAL GROUND PLANE. Figure 2. Pin Configuration DVDD SPI Digital Power Supply. See Figure 2 for the required components. 2 AMPT2_P Second Differential Amplifier Output (Positive). 3 AMP2_N Second Differential Amplifier Output (Negative). VCC_FILTER Power Supply for the Filter. See Figure 2 for the required components. FILTER2P Input of the Third External Filter Amplifier. 6 VCC_AMP3 Power Supply for the Third External Filter Amplifier. See Figure 2 for the required components. 7, 9, 2 GND, GND2, GND3 Ground Connect. 8 VCC_BB Power Supply for the Baseband Blocks. See Figure 2 for the required components. VGA_EXT_CAP External Capacitor for VGA3. See Figure 2 for the required components. RX_OUT Receiver Output. 2 VCC_VGA3 Power Supply for VGA3. See Figure 2 for the required components. 3 AUX_OUT Receiver Auxiliary Output. PD3_IN Receive AGC Loop Input. PD3_OUT/RSSI Third Power Detector Output. 6 VC_VGA_IF/CAP Control Voltage of IFVGA/AGC Integrator Capacitor. See Figure 2 for the required components. 7 VC_VGA_RF/CAP+ Control Voltage of RFVGA/AGC Integrator Capacitor. See Figure 2 for the required components. 8 VCC_PD Power Supply for the First Power Detector. See Figure 2 for the required components. 9 PD_OUT First Power Detector Output. RFIN Radio Frequency Input. This pin is matched to Ω. 22 AMP Single-Ended Output of Amplifier. 23 VCC_AMP Power Supply for AMP. See Figure 2 for the required components. 2 FILTERP RFVGA Input. 2 VCC_VGA Power Supply for the RFVGA. See Figure 2 for the required components. 26 VCC_VGA_BALUN Power Supply for RFVGA Balun. See Figure 2 for the required components. 27 VCC_IRM Power Supply for the Image Reject Mixer. See Figure 2 for the required components. 28 IRM_I_P Positive In-Phase IF Output for the Image Reject Mixer. 29 IRM_I_N Negative In-Phase IF Output for the Image Reject Mixer. VDDV V Supply for Overtemperature (OTP) Burning. See Figure 2 for the required components. 3 IRM_Q_P Positive Quadrature IF Output for the Image Reject Mixer. Rev. A Page 7 of 27 3867-2
32 IRM_Q_N Negative Quadrature IF Output for the Image Reject Mixer. 33 LOP Local Oscillator Input (Positive). This pin is ac-coupled and matched to Ω. 3 LON Local Oscillator Input (Negative). This pin is ac-coupled and matched to Ω. 3 SEN SPI Serial Enable. 36 SCLK SPI Clock Digital Input. 37 SDI SPI Serial Data Input. 38 SDO SPI Serial Data Output. 39 RST SPI Reset. REF_CLK_P Filter Calibration Clock. EPAD Exposed Pad. Connect the exposed pad to a low impedance thermal and electrical ground plane. Rev. A Page 8 of 27
TYPICAL PERFORMANCE CHARACTERISTICS EXTERNAL AGC CONFIGURATION Lower sideband selected, maximum gain. 9 9 8 8 8 7 7 6 MHz 28MHz 6MHz 2MHz EXT 6.8.2.6 2. 2. 2.8 3.2 3.6. 3867-3 8 7 7 6 +8 C +2 C C 6.8.2.6 2. 2. 2.8 3.2 3.6. 3867-6 Figure 3. Conversion Gain vs. RF Frequency over Internal and External Filters Figure 6. Conversion Gain vs. RF Frequency over Temperature, 6 MHz Filter 9 9 8 8 8 7 7 dbm 2dBm 6 dbm +2dBm +dbm 6.8.2.6 2. 2. 2.8 3.2 3.6. 3867-8 7 7 6 3.63V 3.V 2.97V 6.8.2.6 2. 2. 2.8 3.2 3.6. 3867-7 Figure. Conversion Gain vs. RF Frequency at Various Local Oscillator (LO) Powers, 6 MHz Filter Figure 7. Conversion Gain vs. RF Frequency at Various VCCx, 6 MHz Filter 3 +8 C +2 C C 3 +8 C +2 C C 2 2 2 3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_RF (V) 3867-2 3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_RF (V) 3867-8 Figure. Conversion Gain vs. VC_VGA_RF at RF = GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) Figure 8. Conversion Gain vs. VC_VGA_RF at RF = 2 GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) Rev. A Page 9 of 27
Lower sideband selected, maximum gain. 3 +8 C +2 C C 9 8 +8 C +2 C C 2 7 6 2 3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_RF (V) Figure 9. Conversion Gain vs. VC_VGA_RF at RF = GHz, 6 MHz Filter (RF Input Power = dbm, VC_VGA_IF = V) 3867-9 3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_IF (V) Figure 2. Conversion Gain vs. VC_VGA_IF at RF = GHz, 6 MHz Filter (VC_VGA_RF = 3.3 V) 3867-2 9 8 +8 C +2 C C 9 8 +8 C +2 C C 7 6 7 6 3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_IF (V) Figure. Conversion Gain vs. VC_VGA_IF at RF = 2 GHz, 6 MHz Filter (VC_VGA_RF = 3.3 V) 3867-3.3 3. 2.7 2. 2..8..2.9.6.3 VC_VGA_IF (V) Figure 3. Conversion Gain vs. VC_VGA_IF at RF = GHz, 6 MHz Filter, (VC_VGA_RF = 3.3 V) 3867-3 9 8 MHz 28MHz 6MHz 2MHz 9 8 +8 C +2 C C NOISE FIGURE (db) 7 6 3 NOISE FIGURE (db) 7 6 3 2 2.8.2.6 2. 2. 2.8 3.2 3.6. Figure. Noise Figure vs. RF Frequency over Internal Filters 3867-.8.2.6 2. 2. 2.8 3.2 3.6. Figure. Noise Figure vs. RF Frequency over Temperature, 6 MHz Filter 3867- Rev. A Page of 27
Lower sideband selected, maximum gain. NOISE FIGURE (db) 9 8 7 6 3 dbm 2dBm dbm +2dBm +dbm NOISE FIGURE (db) 9 8 7 6 3 3.63V 3.V 2.97V 2 2.8.2.6 2. 2. 2.8 3.2 3.6. Figure. Noise Figure vs. RF Frequency at Various LO Powers, 6 MHz Filter 3867-.8.2.6 2. 2. 2.8 3.2 3.6. Figure 8. Noise Figure vs. RF Frequency at Various VCCx, 6 MHz Filter 3867-8 IMAGE REJECTION (dbc) 3 2 MHz 28MHz 6MHz 2MHz.8.2.6 2. 2. 2.8 3.2 3.6. Figure 6. Image Rejection vs. RF Frequency over Internal Filters 3867-6 IMAGE REJECTION (dbc) 3 2 +8 C +2 C C.8.2.6 2. 2. 2.8 3.2 3.6. Figure 9. Image Rejection vs. RF Frequency over Temperature, 6 MHz Filter 3867-9 IMAGE REJECTION (dbc) 3 2 dbm 2dBm dbm +2dBm +dbm.8.2.6 2. 2. 2.8 3.2 3.6. Figure 7. Image Rejection vs. RF Frequency at Various LO Powers, 6 MHz Filter 3867-7 IMAGE REJECTION (dbc) 3 2 3.63V 3.V 2.97V.8.2.6 2. 2. 2.8 3.2 3.6. Figure. Image vs. RF Frequency at Various VCCx, 6 MHz Filter 3867- Rev. A Page of 27
Lower sideband selected, maximum gain. 32 28 2 MHz 28MHz 6MHz 2MHz 32 28 2 +8 C +2 C C IP3 (dbm) 6 2 IP3 (dbm) 6 2 8 8.8.2.6 2. 2. 2.8 3.2 3.6. Figure 2. Output IP3 vs. RF Frequency over Internal Filters 3867-2.8.2.6 2. 2. 2.8 3.2 3.6. Figure 2. Output IP3 vs. RF Frequency over Temperature, 6 MHz Filter 3867-2 32 28 2 dbm 2dBm dbm +2dBm +dbm 32 28 2 3.63V 3.V 2.97V IP3 (dbm) 6 2 IP3 (dbm) 6 2 8 8.8.2.6 2. 2. 2.8 3.2 3.6. Figure 22. Output IP3 vs. RF Frequency at Various LO Powers, 6 MHz Filter 3867-22.8.2.6 2. 2. 2.8 3.2 3.6. Figure 2. Output IP3 vs. RF Frequency at Various VCCx, 6 MHz Filter 3867-2 +8 C +2 C C +8 C +2 C C RETURN LOSS (db) 2 RETURN LOSS (db) 2 3..8.2.6 2. 2. 2.8 3.2 3.6...8 Figure 23. RF Return Loss vs. RF Frequency over Temperature (Optimize RF Return Loss by Adjusting Capacitor C2, see Figure 2) 3867-23 3..8.2.6 2. 2. 2.8 3.2 3.6...8 LO FREQUENCY (GHz) Figure 26. LO Return Loss vs. LO Frequency over Temperature 3867-26 Rev. A Page 2 of 27
Lower sideband selected, maximum gain. +8 C +2 C C LO TO RF LEAKAGE LO TO IF LEAKAGE RETURN LOSS (db) 2 LEAKAGE (dbm) 6 7 3.....2..3... IF FREQUENCY (GHz) Figure 27. IF Return Loss vs. IF Frequency over Temperature 3867-27 8.8.2.6 2. 2. 2.8 3.2 3.6.. LO FREQUENCY (GHz) Figure. LO Leakage vs. LO Frequency at RF and IF Ports with 6 MHz Filter 3867- RF TO IF LEAKAGE RF TO (AMP2_P + AMP2_N) LEAKAGE LO TO (AMP2_P + AMP2_N) LEAKAGE LEAKAGE (dbm) LEAKAGE (dbm) 6 6 7 7 8.8.2.6 2. 2. 2.8 3.2 3.6. Figure 28. RF Leakage vs. RF Frequency at IF Port with 6 MHz Filter and at (AMP2_P + AMP2_N) Pins 3867-28 8.8.2.6 2. 2. 2.8 3.2 3.6. LO FREQUENCY (GHz) Figure 3. LO Leakage vs. LO Frequency at (AMP2_P + AMP2_N) Pins 3867-3 +8 C +2 C C +8 C +2 C C.....2..3... IF FREQUENCY (GHz) Figure 29. MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) 3867-29.....2..3... IF FREQUENCY (GHz) Figure 32. 28 MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) 3867-32 Rev. A Page 3 of 27
Lower sideband selected, maximum gain. +8 C +2 C C +8 C +2 C C.....2..3... IF FREQUENCY (GHz) Figure 33. 6 MHz Internal Filter Response vs. IF Frequency at RF = GHz (RF Input Power = dbm, Adjusted VC_VGA_IF and VC_VGA_RF to Achieve db of Gain) 3867-33.....2..3... IF FREQUENCY (GHz) Figure 36. 2 MHz Internal Filter Response vs. IF Frequency at RF = GHz 3867-36 PD3 OUTPUT VOLTAGE (V) 2..9.8.7.6...3.2 +8 C +2 C C PD3 OUTPUT VOLTAGE (V) 2..9.8.7.6...3.2 +8 C +2 C C... 3 2 IF OUTPUT POWER (dbm) Figure 3. PD3 Output Voltage vs. IF Power Output at RF = GHz, 6 MHz Filter 3867-3. 3 2 IF OUTPUT POWER (dbm) Figure 37. PD3 Output Voltage vs. IF Power Output at RF = 2 GHz, 6 MHz Filter 3867-37 PD3 OUTPUT VOLTAGE (V) 2..9.8.7.6...3.2. +8 C +2 C C PdB (dbm) 3 2 9 8 7 6 +8 C +2 C C. 3 2 IF OUTPUT POWER (dbm) Figure 3. PD3 Output Voltage vs. IF Power Output at RF = GHz, 6 MHz Filter 3867-3.8.2.6 2. 2. 2.8 3.2 3.6. Figure 38. Output PdB vs. RF Frequency over Temperature, 6 MHz Filter 3867-38 Rev. A Page of 27
Lower sideband selected, maximum gain. 3 2 PdB (dbm) 9 8 7 6 6 7.8.2.6 2. 2. 2.8 3.2 3.6. Figure 39. Output PdB vs. RF Frequency over IF Gain Limit, 6 MHz Filter 3867-39 Rev. A Page of 27
INTERNAL AGC CONFIGURATION POUT = 9 dbm per tone, lower sideband, and 6 MHz filter selected. 8 8 7 7 6 6 IM3 (dbc) IM3 (dbc) +8 C +2 C C +8 C +2 C C 7 6 6 3 2 INPUT POWER (dbm) 3867-7 6 6 3 2 INPUT POWER (dbm) 3867-3 Figure. IM3 vs. Input Power over Temperature, RF = GHz Figure 3. IM3 vs. Input Power over Temperature, RF = 2 GHz 8 7 7 6 +8 C +2 C C IM3 (dbc) 6 NOISE FIGURE (db) +8 C +2 C C 7 6 6 3 2 INPUT POWER (dbm) Figure. IM3 vs. Input Power over Temperature, RF = GHz 3867-9 8 7 6 INPUT POWER (dbm) Figure. Noise Figure vs. Input Power over Temperature, RF = GHz 3867-7 6 +8 C +2 C C 7 6 +8 C +2 C C NOISE FIGURE (db) NOISE FIGURE (db) 9 8 7 6 INPUT POWER (dbm) Figure 2. Noise Figure vs. Input Power over Temperature, RF = 2 GHz 3867-2 9 8 7 6 INPUT POWER (dbm) Figure. Noise Figure vs. Input Power over Temperature, RF = GHz 3867- Rev. A Page 6 of 27
POUT = 9 dbm per tone, lower sideband, and 6 MHz filter selected. 6 +8 C +2 C C 6 +8 C +2 C C OUTPUT POWER (dbm) 8 2 OUTPUT POWER (dbm) 8 2 6 6 8 9 8 7 6 INPUT POWER (dbm) Figure 6. Output Power vs. Input Power over Temperature, RF = GHz 3867-6 8 9 8 7 6 INPUT POWER (dbm) Figure 8. Output Power vs. Input Power over Temperature, RF = 2 GHz 3867-8 6 +8 C +2 C C OUTPUT POWER (dbm) 8 2 6 8 9 8 7 6 INPUT POWER (dbm) Figure 7. Output Power vs. Input Power over Temperature, RF = GHz 3867-7 Rev. A Page 7 of 27
THEORY OF OPERATION The is a highly integrated intermediate frequency (IF) receiver chip that converts radio frequency (RF) to a single-ended IF signal at its output. The internal active gain circuit (AGC) of the is able to actively level the output power at the IF output via SPI control. The gain control of the can be controlled externally as an alternative option via the VC_VGA_RF and VC_VGA_IF pins with voltages ranging from 3.3 V (minimum attenuation) to V (maximum attenuation). The utilizes an input low noise amplifier (LNA) cascaded with a variable gain amplifier (VGA), which can either be controlled by the internal AGC or external voltages, that feeds the RF signals to an image reject mixer. The local oscillator port can either be driven single ended through LON or differentially through the combination of LON and LOP. The radio frequency is then converted to intermediate frequencies, which can either feed off chip via baseband differential outputs or feed on chip into a programmable bandpass filter. It is recommended during IF mode operation that the baseband outputs be unconnected. The programmable band-pass filter on chip has four programmable bandwidths ( MHz, 28 MHz, 6MHz, and 2 MHz). The programmable band-pass filter has the capability to adjust the center frequency. From the factory, a filter calibration is conducted and the center frequency of the filter is set to MHz. This calibration can be recalled via SPI control or the customer can adjust the center frequency, but the calibration value must be stored off chip (see the Register Array Assignments section). An external filter option can be utilized to allow the customer to select other filter bandwidths/responses that are not available on chip. The external filter path coming from the image reject mixer feeds into an amplifier that has differential outputs. The output of the external filter can be fed back into the chip, which is then connected to another amplifier. A VGA follows immediately after the band-pass filter. Control the IF VGA either by the AGC or external voltages. The output of the variable gain amplifier is the output of the device. REGISTER ARRAY ASSIGNMENTS AND SERIAL INTERFACE The register arrays for the are organized into nine registers of 6 bits. Using the serial interface, the arrays are written or read one row at a time, as shown in Figure and Figure. Figure shows the sequence of signals on the enable (SEN), CLK, and data (SDI) lines to write one 6-bit array of data to a single register. The enable line goes low, the first of 2 data bits is placed on the data line, and the data is sampled on the rising edge of the clock. The data line should remain stable for at least 2 ns after the rising edge of CLK. The device supports a serial interface running up to MHz, the interface is 3.3 V CMOS logic. A write operation requires 2 data bits and 2 clock pulses, as shown in Figure. The 2 data bits contain the 3-bit chip address, followed by the -bit register array number, and finally the 6-bit register data. After the 2th clock pulses of the write operation, the enable line returns high to load the register array on the IC. A read operation requires 2 data bits and 8 clock pulses, as shown in Figure. For every register read operation, a write to Register 7 is required first. The data written should contain the 3-bit chip address, followed by the -bit register number for Register 7, and finally the -bit number of the register to be read. The remaining bits should be logic zeroes. When the read operation is initiated, the data is available on the data output (SDO) pin. Read Example If reading Register 2, the following 2 bits should be written to initiate the read operation. ZERO BITS ( BITS) REGISTER 7 ADDRESS ( BITS) REGISTER TO BE READ ( BITS) CHIP ADDRESS (3 BITS) Figure 9. Sample Bits to Initiate Read 3867-9 Rev. A Page 8 of 27
SEN 2 CLOCK CYCLES 2 CLK SDI 2 3 6 7 8 9 2 3 6 7 8 9 2 22 23 MSB WRITE DATA LSB MSB REGISTER ADDRESS LSB CHIP ADDRESS MSB LSB 3867- Figure. Timing Diagram, SPI Register Write SEN 2 CLOCK CYCLES 2 CLOCK CYCLES 2 2 CLK SDI 2 3 6 7 8 9 23678922223 SDO 2 3 6 7 8 9 23 MSB ALL ZEROS LSB MSB READ REGISTER ADDRESS LSB MSB CHIP REG 7 ADDRESS ADDRESS MSB LSB MSB READ DATA LSB 3867- Figure. Timing Diagram, SPI Register Read Rev. A Page 9 of 27
REGISTER DESCRIPTIONS REGISTER ARRAY ASSIGNMENTS In the Access columns (Table 6 through Table ), R means read, W means write, and R/W means read/write. Enable Bits Table 6. Enable Register, (Address x) Bit No. Bit Name Description Reset Access PD2_EN Power Detector 2 enable x R/W = disable = enable Factory diagnostics Logic for normal operation x R/W 3 PD3_AMP_EN Auxiliary output (Pin 3) enable x R/W = disable = enable 2 Reserved Logic for normal operation x R/W AMP_EN LNA enable x R/W = disable = enable RF_VGA_EN RF VGA enable x R/W = disable = enable 9 IRM_EN Image reject mixer enable x R/W = disable = enable 8 FIL2_EN Filter 2 enable x R/W = disable = enable 7 IF_VGA_EN Filter 2 enable x R/W = disable = enable 6 Factory diagnostics Logic for normal operation x R/W PD_EN Power Detector enable x = disable = enable PD3_EN Power Detector 3 enable x R/W = disable = enable 3 AGC_EN Available gain control (AGC) enable x R/W = enable = disable 2 AMP3_PDWN Amplifier 3 power-down x R/W = enable = disable AMP2_PDWN Amplifier 2 power-down x R/W = enable = disable IQ_BUF_EN IQ buffer enable x R/W = disable = enable Rev. A Page of 27
Image Reject and Band-Pass Filter Bits Table 7. Image Reject and Band-Pass Filter Register, (Address x2) Bit No. Bit Name Description Reset Access IRM_IS Image sideband select x R/W = lower sideband = upper sideband [:3] FIL2_SEL Internal band-pass filter select x2 R/W = MHz = 28 MHz = 6 MHz = 2 MHz 2 SEL_EXT_FIL Select external filter x R/W = internal = external Reserved Not used x R/W FIL2_CAL_OVR Override on-chip calibration and use 8-bit word from SPI x R/W = use on-chip calibration word = use FIL2_FREQ_SET word from SPI 9 FIL2_CAL_EN Enable filter center frequency calibration x R/W = disable = enable (transition from to ) 8 Reserved Not used x R/W [7:] FIL2_FREQ_SET Internal band-pass filter center frequency setting x8 R/W Band-Pass Filter Bits: OTP and SPI Table 8. Band-Pass Filter Register, (Address x3) Bit No. Bit Name Description Reset Access [:2] Reserved Logic for normal operation x8 R/W FIL_OPT_MUX_SEL Override SPI FIL2_FRQ_SET and use 8-bit word from OTP x R/W = select OTP setting = select SPI setting [:] Reserved Logic for normal operation x69f R/W AGC Table 9. AGC Register, (Address x) Bit No. Bit Name Description Reset Access [:2] AGC_SELECT Active gain control (AGC) select x3 R/W x3 = internal AGC mode xc = external AGC mode AGC_EXT_CAP_SEL Active gain control external capacitor select x R/W = no external capacitor = external capacitor Rev. A Page 2 of 27
Bit No. Bit Name Description Reset Access [:8] AGC_BW AGC bandwidth x R/W = 7 Hz = 22 Hz = 33 Hz = 67 Hz = 83 Hz = Hz (recommended setting) = 67 Hz = 333 Hz [7:6] VGA3_GAIN VGA 3 attentuation x R/W = db (recommended setting) = db = db = db [:] POUT_CTRL Power output control x R/W x = dbm x = 3 dbm x2 = x3e = +8 dbm x3f = +9 dbm Active Gain Control: IF Gain Limit Bits Table. AGC Register, (Address x) Bit No. Bit Name Description Reset Access [:2] Reserved Not used xa R/W [:9] IF_GAIN_LIMIT IF gain limit x R/W = db = 6 db = 2 db = 8 db = 2 db = db = 36 db = 2 db [8:] Reserved Logic for normal operation x R/W Band-Pass Filter Bits: Calibration and 8-Bit Word Frequency Table. Band-Pass Filter Register, (Address x6) Bit No. Bit Name Description Reset Access [:] Reserved Not used x R 9 FIL2_CAL_OVFL FIL2 calibration overflow signal x R 8 FIL2_VCAL_END FIL2 calibration end signal x R [7:] FL2_FC_CAL FIL2 8-bit word frequency setting, read only x8 R Rev. A Page 22 of 27
AGC: Blocker Power Detector Bits Table 2. AGC Register, (Address x2) Bit No. Bit Name Description Reset Access [:8] Reserved Not used xf R/W 7 Reserved Not used x R/W 6 AGC_BLOCKER_MODE_EN AGC blocker mode enable x R/W = off = on [:3] AGC_BLOCKER_PD2_REF AGC blocker power detector reference level x3 R/W = dbm = 2 dbm = dbm = 2 dbm = dbm = 6 dbm = 8 dbm = dbm [2:] AGC_BLOCKER_PD2_LOOP_BW AGC blocker power detector loop bandwidth control x R/W = 7 Hz = 22 Hz = 33 Hz = 67 Hz = 83 Hz = Hz = 67 Hz = 333 Hz Phase I Bits Table 3. Phase I Register, (Address x) Bit No. Bit Name Description Reset Access [:2] Reserved Not used xf R/W [:9] Reserved Not used x R/W [8:] I_PHASE_ADJ I phase adjust x R/W Phase Q Bits Table. Phase Q Register, (Address x) Bit No. Bit Name Description Reset Access [:2] Reserved Not used xf R/W [:9] Reserved Not used x R/W [8:] Q_PHASE_ADJ Q phase adjust x R/W Rev. A Page 23 of 27
APPLICATIONS INFORMATION During operation at PdB, the IF gain limit of the, as described in the Register Array Assignments and Serial Interface section, needs to be limited by the radio frequency (RF), as listed in Table. There is a recommended IF gain limit setting and maximum allowed IF gain limit setting that is to be used. SCHEMATIC/TYPICAL APPLICATION CIRCUIT Table. Recommended IF Gain Limit Settings by RF Frequency RF Frequency (GHz) Maximum Setting.8 to.8.8 to 2.8 6 2.8 to. 7 6 Recommended Setting Rev. A Page 2 of 27
2 3 6 7 8 9 39 38 37 36 3 3 33 32 3 EVALUATION PRINTED CIRCUIT BOARD (PCB) 2-8MHz : T 3 2 C3 pf VGA_EXT_CAP C9 µf RX_OUT JP RST SDO SDI REF_CLK_P SCLK SEN DVDD C C27 C28 µf nf pf C nf C µf V CC _AMP3 R 6Ω R 6Ω C29 µf 2 SPI OTP 29 V CC _FILTER C6 C33 C32 µf nf pf F MHz R7 9.9Ω C3 pf 3 6 7 8 FILTER MHz 28MHz 6MHz 2MHz AGC 28 27 26 2 2 23 V CC _AMP3 C7 C36 C3 µf nf pf 9 22 2 V CC _BB C7 µf C36 nf C3 pf C3 µf C2 pf C nf C pf R8 7Ω L2 2.2µH C8 µf C38 nf C37 pf R.99Ω C39 nf R kω C9 pf R U2 V+ V + kω R2 kω PD3_OUT R9 kω R3 kω C µf R Ω VC_VGA EXT_23 VC_VGA EXT_ RFIN C pf LON LOP C66 pf L nh C6 nf T2 3 2 C6 nf C68 µf C3 µf V CC _OTP : 2-8MHz C2 pf C nf C µf V CC _IRM C3 µf C3 pf C nf C µf V CC _BALUN C6 pf C nf C6 µf V CC _VGA C7 pf C8 nf C7 µf V CC _AMP C pf C nf C8 µf V CC _AMP C9 pf F2 DC-MHz C9 µf V CC _PD BBOUT_I T3 3 2 : 2-8MHz BBOUT_Q 3867-2 V CC _AGC C µf C2 pf C nf 2 3 C µf C7 nf C8 pf Figure 2. PCB Schematic/Typical Applications Circuit Rev. A Page 2 of 27
3867-3 Figure 3. Evaluation PCB Rev. A Page 26 of 27
OUTLINE DIMENSIONS DETAIL A (JEDEC 9) PIN INDICATOR 6. 6. SQ.9. SQ..2. 3. BSC PIN INDIC ATOR AREA OPTIONS (SEE DETAIL A). BSC EXPOSED PAD.6. SQ..9.9.8 SEATING PLANE TOP VIEW SIDE VIEW...3 2. MAX.2 NOM COPLANARITY.8.3 REF BOTTOM VIEW. MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. PKG- COMPLIANT TOJEDEC STANDARDS MO-2-VJJD-. Figure. -Lead Lead Frame Chip Scale Package [LFCSP] 6 mm 6 mm Body and.9 mm Package Height (CP--22) Dimensions shown in millimeters ORDERING GUIDE Model, 2 Temperature Range MSL Rating 3 Package Description Package Option C to +8 C MSL3 -Lead Lead Frame Chip Scale Package CP--22 EKHMC8LP6J [LFCSP] Evaluation Kit --6-A Package Marking H8 XXXX is a RoHS compliant part. 2 The lead finish is NiPdAu. 3 See the Absolute Maximum Ratings section. XXXX is the -digit lot number. 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D3867--/6(A) Rev. A Page 27 of 27