Recent Developments in Multifunctional Integration Stephan Guttowski, Head of Technology Park»Heterointegration«, Fraunhofer FMD
Founding Participants 2
One-Stop-Shop for developments from wafer technologies to complete systems The FMD combines the expertise and infrastructure of 13 Research Institutes to deliver complete developments out of one hand The FMD will represent a reorganization of more than 2000 scientists and the necessary equipment for technological research and development under a single, virtual roof To prepare the FMD for future developments additional infrastructure investment of 350 Mio. is planned 3
Service FMD One-Stop-Shop Central contact for technology development requests Setup of research and development projects between different institutes Organisation of combined prototype and pilot fabrication Information/Organisation of technology strategies 4 4
Project Research Fab Microelectronics Germany Largest Federal Ministry of Education and Research Project in the area of Microelectronics Targets Setup of a virtual institute for the coordination of the cooperation partners inside the technology parks After handing over the grant approvals issued by the Federal Ministry of Education and Research, April 6, 2017 in Berlin Project volume 348,1 Mio. Eur Fraunhofer Leibniz 279,6 Mio. Eur 68,5 Mio. Eur Duration 4 years (2017-20) Investments in new machinery across the four technology parks: Silicon-based technologies Compound semiconductors Heterointegration Design, testing and reliability 5
Competencies alongside the value chain Design & Design Methods Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Technology Plattforms 6
Competencies alongside the value chain Design & Design Methods Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Design & Design Methods Microwave & Terahertz Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Power Electronics Extended CMOS Optoelectronic Systems Sensor Systems MEMS Actuators 7
General competencies alongside the value chain Design & Design Methods Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Advanced system and component design and adaption to new requirements from the application perspectives Design Methods Specification and requirement engineering Modeling and simulation, Function verification Layout Design System and component design, IP Design under constraints Prototyping Hardware-in-the-loop concepts Emulation, HW/SW co-design Foto: Fraunhofer IIS/EAS / Jürgen Lösel 8
General competencies alongside the value chain Design & Design Methods Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Silicon-based and compound semiconductor based microelectronics and microsystem technology Process Technologies Material Integration CMOS, BiCMOS, FDSOI, MEMS/NEMS III-V Materials combination and processing Devices Technologies High-Frequency, Power electronics Memory Storage, Energy Harvesting Sensors, Actuators Optoelectronic devices SiC 3300V MOSFET Silicon capacities InP based optoelectronics Bulk micromachining mhemt (up to 1 THz) 9
General competencies alongside the value chain Design & Design Methods Materials and processes Devices and components Heterogeneous Integration / SiP Characterization, Test & Reliability Integration of all the different components from various manufacturing processes to systems Memory, CPU, FPGA Packaging MEMS, Sensors, Actors Packaging Optoelectronic/Photonic Packaging Integrated Power Device Packaging Display/RFID/Flex Packaging RF and Analog mixed signal Packaging Advanced Substrate / Interposer 10
General competencies alongside the value chain Design & Design Methods Materials and processes Devices and components Heterogeneous Integration / SiP Characterization, Test & Reliability Powerful methods for metrological characterization of everything, Evaluation of reliability and live time, Holistic consideration of the system function across various levels of abstraction Characterization of materials and devices General, electrical, MEMS, Opto, Power, novel Sensors Measurement and analysis of circuits and systems Analog-mixed signal / digital circuits and systems high-frequency systems characterization of hetero-integrated systems Reliability assessment Complex stress scenarios Thermal, electrical induced effects Reliability risk management Foto: Fraunhofer IZM / Jürgen Lösel 11
Competencies alongside the value chain Design & Design Methods Materials and Processes Devices and Components Heterogeneous Integration / SiP Characterization, Test & Reliability Microwave & Terahertz Power Electronics Extended CMOS Optoelectronic Systems Sensor Systems MEMS Actuators 12
Fraunhofer FHR Fraunhofer FHR Challenges in Heterointegration Integration of components from various manufacturing processes (Wafer, Chip, Passives, MEMS, Panel ) Intergration technologies for: Extreme small sizes Low power loss Large frequency range Maximum reliability Low production costs Buildup adapted to specific product design Novel solutions application-specific and customizable Cross-domain functions (optics, power electronics, signal electronics, sensor technology ) Cost-efficient production: in small batches, scalable to large volumes 3000 km 300 km Radar 14
Scientific contents in Heterointegration Structure size will be adapted to the components Strategies for the realisation of extreme small structure sizes on large production formats (Chip, Wafer, Panel) Scaling of 2D- and 2,5D-Integration schemes for large area substrates and complex 3D-Stacking Extension of processes to non-electronic functionalities (cross-domain capacity, e.g. optoelectronics, optics, sensor technologies) Allocation of integration strategies and processes for smart systems 15
Technological Goals for the Future Integration Short term Further development up to the technological limits (geometrical structures < 750 nm, substrate size 450 x 600 mm) Integration of sensors, MEMS, compound semiconductors Buildup of multiproject platforms to reduce costs using Wafer-, Panel- and Sheet-Level Process development for the integration of power electronic, optoelectronics and RF-components into substrates; with regard to heat dissipation, precision of alignment and structure Long term Development of a smart functionality approach: integration of medium interfaces (optical, fluid, nano electronical) Development of new strategies for structuring: e.g. hybrid technologies by using combined processes (printing, laser direct imaging, stepper, imprint) 16
Fraunhofer FHR Technology Support Example Microwave & Terahertz Radar Applications Space to In-line-AOI Security to Spectroscopy Ultra-high Bandwidth up to 300 GHz Radar Highest achievable level of integration by integrating many components in one single SiGe- Chip Very large applicable temperature range from -40 C up to +85 C. 17
Fraunhofer IZM Technology Support Example Panel Level Packaging Panel Level Packaging up to 18 x 24 Embedding Components into PWB Fan-Out Packaging using Molding Applications Power Electronics Automotive Smart Cameras RF-Module Sensor Packaging LED-Packaging Medical Devices 18
Technology Support Example System-aware Power Packaging (Si, SiC & GaN) Application-Focus on Power Electronics: Power generation & transmission low, medium and high voltage AC/AC, AC/DC & DC/DC-converters Traction avionics, rail & automotive Vertical integrated development: Design & Simulation Material & Manufacturing SiC ( TP2) Device Packaging & Module Integration Test, analytics & forensics Reliability & Lifetime Model ( TP4) 19 Fraunhofer IISB Technology & Market Trends
Fraunhofer IPMS Technology Support Example MEMS Actuators Full Services Offer Device and packaging construction (3D CAD) Material selection (Package, Protection, ) Simulation (thermal, optical, electrical) Methodology evaluation Chip Integration on Foil Sheets Technology Prospects Extreme planar packaging technologies for several millions micro mirrors per chip MEMS Packaging within clean room class ISO4 [US- Kl.10 fully automated assembly 20
Fraunhofer ISIT Technology Support Example MEMS Actuators Full Services Offer Assembly and joining of MEMS, IC and SMD components on diverse substrates Printed Interconnects System Characterization Reliabilty Testing Technology Prospects Passive adjust of optical components on wafer for WLP Sub 0.5 µm precise in-situ laser soldering W2W, C2W Bonding with nanoparticles Hermetic optical capping on wafer level Stacked and hybrid IC/MEMS Integration 21
Fraunhofer EMFT Technology Park 3»Heterogeneous Integration«Technology Support Example Flex Substrate Integration Current Technology State Production of high density redistribution layer on foils in Reel-to-Reel (RzR) Chip Integration on Foil Sheets Technology Improvement Integration of adaptive lithography for inline correction of the Foil Distortions within the Reel-to- Reel-process (RtR) Extremely thin and foldable Chip-Foil-Packages in RtR Module-based integration von multi- functional foil systems Foldable Sensors MEMS-IC Flexible 22
YOUR CONTACT Jörg Amelung Head of (FMD) joerg.amelung@mikroelektronik.fraunhofer.de +49 351 88 23-339 Dr.-Ing. Stephan Guttowski Head of Technology Park»Heterointegration«Forschungsfabrik Mikroelektronik Deutschland FMD Anna-Louisa-Karsch-Str. 2 10178 Berlin stephan.guttowski@mikroelektronik.fraunhofer.de +49 30 46 403 632 GEFÖRDERT VOM www.forschungsfabrik-mikroelektronik.de 23