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Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) description The AHC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive traition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs. A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. SN54AHC574...J OR W PACKAGE SN74AHC574... DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) SN54AHC574... FK PACKAGE (TOP VIEW) OE does not affect internal operatio of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To eure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 3D 4D 5D 6D 7D OE 1D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 2D 1D OE 20 19 18 17 16 15 14 13 12 11 V CC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 3 4 2 1 20 19 18 5 6 7 8 17 16 15 14 9 10 11 12 13 8D GND CLK V CC 8Q 7Q 1Q 2Q 3Q 4Q 5Q 6Q Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Itruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1

TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube SN74AHC574N SN74AHC574N SOIC DW Tube Tape and reel SN74AHC574DW SN74AHC574DWR AHC574 40 C to 85 C SOP NS Tape and reel SN74AHC574NSR AHC574 SSOP DB Tape and reel SN74AHC574DBR HA574 TSSOP PW Tape and reel SN74AHC574PWR HA574 TVSOP DGV Tape and reel SN74AHC574DGVR HA574 CDIP J Tube SNJ54AHC574J SNJ54AHC574J 55 C to 125 C CFP W Tube SNJ54AHC574W SNJ54AHC574W LCCC FK Tube SNJ54AHC574FK SNJ54AHC574FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each flip-flop) INPUTS OUTPUT OE CLK D Q L H H L L L L H or L X Q0 H X X Z logic diagram (positive logic) OE 1 CLK 11 1D 2 1D C1 19 1Q To Seven Other Channels 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0.5 V to 7 V Input voltage range, V I (see Note 1).................................................. 0.5 V to 7 V voltage range, V O (see Note 1)........................................ 0.5 V to V CC + 0.5 V Input clamp current, I IK (V I < 0)........................................................... 20 ma clamp current, I OK (V O < 0 or V O > V CC )............................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±25 ma Continuous current through V CC or GND................................................... ±75 ma Package thermal impedance, θ JA (see Note 2): DB package................................. 70 C/W DGV package................................ 92 C/W DW package................................. 58 C/W N package................................... 69 C/W NS package................................. 60 C/W PW package................................. 83 C/W Storage temperature range, T stg................................................... 65 C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditio (see Note 3) SN54AHC574 SN74AHC574 MIN MAX MIN MAX Supply voltage 2 5.5 2 5.5 V = 2 V 1.5 1.5 VIH High-level input voltage = 3 V 2.1 2.1 V = 5.5 V 3.85 3.85 = 2 V 0.5 0.5 VIL Low-level input voltage = 3 V 0.9 0.9 V = 5.5 V 1.65 1.65 VI Input voltage 0 5.5 0 5.5 V VO voltage 0 0 V = 2 V 50 50 A IOH High-level output current = 3.3 V ± 0.3 V 4 4 = 5 V ± 0.5 V 8 8 ma = 2 V 50 50 A IOL Low-level output current = 3.3 V ± 0.3 V 4 4 t/ v Input traition rise or fall rate = 5 V ± 0.5 V 8 8 = 3.3 V ± 0.3 V 100 100 = 5 V ± 0.5 V 20 20 TA Operating free-air temperature 55 125 40 85 C NOTE 3: All unused inputs of the device must be held at or GND to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. ma /V POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54AHC574 SN74AHC574 MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 2 1.9 1.9 IOH = 50 A 3 V 2.9 3 2.9 2.9 VOH 4.5 V 4.4 4.5 4.4 4.4 V OH IOH = 4 ma 3 V 2.58 2.48 2.48 IOH = 8 ma 4.5 V 3.94 3.8 3.8 2 V 0.1 0.1 0.1 IOL = 50 A 3 V 0.1 0.1 0.1 VOL 4.5 V 0.1 0.1 0.1 V OL IOL = 4 ma 3 V 0.36 0.5 0.44 IOL = 8 ma 4.5 V 0.36 0.5 0.44 II VI = 5.5 V or GND to 5.5 V ±0.1 ±1* ±1 A IOZ VO = or GND 5.5 V ±0.25 ±2.5 ±2.5 A ICC VI = or GND, IO = 0 5.5 V 4 40 40 A Ci VI = or GND 5 V 3 10 10 pf Co VO = or GND 5 V 3 pf * On products compliant to MIL-PRF-38535, this parameter is not production tested at =. timing requirements over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25 C SN54AHC574 SN74AHC574 MIN MAX MIN MAX MIN MAX tw Pulse duration, CLK high or low 5 5 5 tsu Setup time, data before CLK 3.5 3.5 3.5 th Hold time, data after CLK 1.5 1.5 1.5 timing requirements over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25 C SN54AHC574 SN74AHC574 MIN MAX MIN MAX MIN MAX tw Pulse duration, CLK high or low 5 5 5 tsu Setup time, data before CLK 3 3 3 th Hold time, data after CLK 1.5 1.5 1.5 4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax FROM TO LOAD TA = 25 C SN54AHC574 SN74AHC574 (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CLK Q CL = 15 pf OE Q CL = 15 pf OE Q CL = 15 pf CLK Q CL = 50 pf OE Q CL = 50 pf OE Q CL = 50 pf CL = 15 pf 80* 125* 65* 65 CL = 50 pf 50 75 45 45 8.5* 13.2* 1* 15.5* 1 15.5 8.5* 13.2* 1* 15.5* 1 15.5 8.2* 12.8* 1* 15* 1 15 8.2* 12.8* 1* 15* 1 15 8.5* 13* 1* 15* 1 15 8.5* 13* 1* 15* 1 15 11 16.7 1 19 1 19 11 16.7 1 19 1 19 10.7 16.3 1 18.5 1 18.5 10.7 16.3 1 18.5 1 18.5 11 15 1 17 1 17 11 15 1 17 1 17 tsk(o) CL = 50 pf 1.5** 1.5 On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax FROM TO LOAD TA = 25 C SN54AHC574 SN74AHC574 (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX CLK Q CL = 15 pf OE Q CL = 15 pf OE Q CL = 15 pf CLK Q CL = 50 pf OE Q CL = 50 pf OE Q CL = 50 pf CL = 15 pf 130* 180* 110* 110 CL = 50 pf 85 115 75 75 5.6* 8.6* 1* 10* 1 10 5.6* 8.6* 1* 10* 1 10 5.9* 9* 1* 10.5* 1 10.5 5.9* 9* 1* 10.5* 1 10.5 5.5* 9* 1* 10.5* 1 10.5 5.5* 9* 1* 10.5* 1 10.5 7.1 10.6 1 12 1 12 7.1 10.6 1 12 1 12 7.4 11 1 12.5 1 12.5 7.4 11 1 12.5 1 12.5 7.1 10.1 1 11.5 1 11.5 7.1 10.1 1 11.5 1 11.5 tsk(o) CL = 50 pf 1** 1 On products compliant to MIL-PRF-38535, this parameter is not production tested. On products compliant to MIL-PRF-38535, this parameter does not apply. MHz MHz POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5

noise characteristics, V CC = 5 V, C L = 50 pf, T A = 25 C (see Note 4) PARAMETER SN74AHC574 VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.2 V VIH(D) High-level dynamic input voltage 3.5 V VIL(D) Low-level dynamic input voltage 1.5 V NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, V CC = 5 V, T A = 25 C MIN MAX PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance No load, f = 1 MHz 28 pf 6 POST OFFICE BOX 655303 DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION From Under Test CL (see Note A) Test Point From Under Test CL (see Note A) RL = 1 kω S1 Open GND TEST / / / Open Drain S1 Open GND LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input 50% tw 50% Timing Input Data Input tsu 50% th 50% 50% VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input In-Phase Out-of-Phase 50% 50% 50% 50% VOH 50% VOL VOH 50% VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Control Waveform 1 S1 at (see Note B) Waveform 2 S1 at GND (see Note B) 50% 50% 50% 50% VOL + 0.3 V VOL VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH VOH 0.3 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7

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