s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process and ircuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 305 D54AT74...F PAKAGE D74AT74...E OR M PAKAGE (TOP VIEW) LR D LK PRE Q Q GND 2 3 4 5 6 7 4 3 2 0 9 8 V 2LR 2D 2LK 2PRE 2Q 2Q description/ordering information The AT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP E Tube D74AT74E D74AT74E Tube D74AT74M 55 to25 SOI M AT74M Tape and reel D74AT74M96 DIP F Tube D54AT74F3A D54AT74F3A Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at www.ti.com/sc/package. FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or LR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
logic diagram, each flip-flop (positive logic) PRE LK TG Q D TG TG TG Q LR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V.......................................................... 0.5 V to 6 V clamp current, I IK (V I < 0 or V I > V ) (see Note )..................................... ±20 ma clamp current, I OK (V O < 0 or V O > V ) (see Note )................................ ±50 ma ontinuous output current, I O (V O = 0 to V ).............................................. ±50 ma ontinuous current through V or GND.................................................. ±00 ma Package thermal impedance, θ JA (see Note 2): E package................................... 80 /W M package.................................. 86 /W Storage temperature range, T stg................................................... 65 to 50 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions (see Note 3) TA = 25 55 to 25 40 to 85 UNIT MIN MAX MIN MAX MIN MAX V Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI voltage V VO voltage V IOH High-level output current 24 24 24 ma IOL Low-level output current 24 24 24 ma t/ v transition rise or fall rate 0 0 0 ns/v NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS s, literature number SBA004. 2
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V VOH VOL VI =VIH or VIL VI =VIH or VIL TA = 25 55 to 25 40 to 85 UNIT MIN MAX MIN MAX MIN MAX IOH = 50 µa 4.5 V 4.4 4.4 4.4 IOH = 24 ma 4.5 V 3.94 3.7 3.8 IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V 3.85 IOL = 50 µa 4.5 V 0. 0. 0. IOL = 24 ma 4.5 V 0.36 0.5 0.44 IOL = 50 ma 5.5 V.65 IOL = 75 ma 5.5 V.65 II VI = V or GND 5.5 V ±0. ± ± µa I VI = V or GND, IO = 0 5.5 V 4 80 40 µa I V I = V 2. V 4.5 V to 5.5 V 2.4 3 2.8 ma i 0 0 0 pf Test one output at a time, not exceeding -second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85 and 75-Ω transmission-line drive capability at 25. Additional quiescent supply current per input pin, TTL inputs high, unit load V V AT INPUT LOAD TABLE INPUT UNIT LOAD Data 0.53 PRE or LR 0.58 LK Unit load is I limit specified in electrical characteristics table (e.g., 2.4 ma at 25 ). timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) 55 to 25 40 to 85 UNIT MIN MAX MIN MAX fclock lock frequency 85 97 MHz tw Pulse duration PRE or LR low 5 4.4 LK 5.7 5 ns tsu Setup time Data 4 3.5 ns PRE or LR inactive ns th Hold time Data after LK 0 0 ns trec Recovery time, before LK LR or PRE 2.7 2.4 ns 3
switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to 25 40 to 85 UNIT MIN MAX MIN MAX fmax 85 97 MHz tplh tphl tplh tphl LK Q or Q PRE or LR QorQ Q 2.4 9.5 2.5 8.6 2.4 9.5 2.5 8.6 2.9.5 3 0.5 3. 2.5 3.2.4 ns ns operating characteristics, V = 5 V, T A = 25 PARAMETER TYP UNIT pd Power dissipation capacitance 55 pf 4
PARAMETER MEASUREMENT INFORMATION From Under Test L = 50 pf (see Note A) R = 500 Ω R2 = 500 Ω S 2 V GND Open TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 2 V GND tw LOAD IRUIT.5 V.5 V PULSE DURATION LR.5 V Reference tsu.5 V th LK.5 V trec Data.5 V 0% 90% 90% tr.5 V 0% tf In-Phase Out-of-Phase REOVERY TIME.5 V.5 V tplh 50% 0% tphl 90% 90% 90% VOH 50% V 0% VOL tf PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tphl 50% V 50% 0% 0% tf tplh VOH 90% VOL tr SETUP AND HOLD AND INPUT RISE AND FALL TIMES ontrol Waveform S at 2 V (see Note B) Waveform 2 S at GND (see Note B) tpzl tpzh.5 V.5 V tplz V 20% V 20% V VOL 80% V tphz OUTPUT ENABLE AND DISABLE TIMES VOH 80% V NOTES: A. L includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tplh and tphl are the same as tpd. G. tpzl and tpzh are the same as ten. H. tplz and tphz are the same as tdis. Figure. Load ircuit and Voltage Waveforms 5
MPDI002 JANUARY 995 REVISED DEEMBER 20002 N (R-PDIP-T**) 6 PINS SHOWN PLASTI DUAL-IN-LINE PAKAGE DIM PINS ** 4 6 8 20 A A MAX 0.775 (9,69) 0.775 (9,69) 0.920 (23,37).060 (26,92) 6 9 A MIN 0.745 (8,92) 0.745 (8,92) 0.850 (2,59) 0.940 (23,88) 0.260 (6,60) 0.240 (6,0) MS-00 VARIATION AA BB A AD 0.070 (,78) 0.045 (,4) D 8 0.045 (,4) 0.030 (0,76) D 0.020 (0,5) MIN 0.325 (8,26) 0.300 (7,62) 0.05 (0,38) 0.200 (5,08) MAX Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M 0.430 (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D 4040049/E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Falls within JEDE MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
MEHANIAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTI SMALL-OUTLINE PAKAGE 8 PINS SHOWN 0.050 (,27) 0.020 (0,5) 0.04 (0,35) 0.00 (0,25) 8 5 0.244 (6,20) 0.228 (5,80) 0.008 (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A 0 8 0.00 (0,25) 0.044 (,2) 0.06 (0,40) Seating Plane 0.069 (,75) MAX 0.00 (0,25) 0.004 (0,0) 0.004 (0,0) DIM PINS ** 8 4 6 A MAX 0.97 (5,00) 0.344 (8,75) 0.394 (0,00) A MIN 0.89 0.337 (4,80) (8,55) 0.386 (9,80) 4040047/E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,5). D. Falls within JEDE MS-02
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