ACPL-339J Isolated Gate Driver Evaluation Board User s Manual Quick-Start Visual inspection is needed to ensure that the evaluation board is received in good condition. The default connections of the evaluation board are as follows: 1. A 15 V Zener diode at D1 is provided to allow for a single DC power supply of 21. V ~ 30 V to be applied across V cc2 and V ee. A virtual ground V e (at COM pin of CON2) will be generated, and it acts as the reference point at the emitter of each IGBT. V cc2 will then stay at 15 V above the virtual ground V e. R11 is needed to provide the bias current across D1. 2. Actual IGBT can be mounted at either Q5 (for TO-220 package) or Q (for TO-247 package) or connected to the driver board through short wire connections from the holes provided at Q5 or Q. 3. S2 jumper is shorted by default to allow for the driver board to be tested without actual IGBT connection at Q5 or Q. Note: Once IGBT is connected at either the Q5 or Q location, this S2 jumper must be removed to allow for IGBT Desat protection to be activated. 4. J1 is shorted by default, assuming that a Desat detection voltage of 8 V is needed. To reduce the Desat detection voltage by another 1 V, this jumper can be replaced by another piece of D3 diode (BYM2E). To further reduce the Desat detection voltage, higher VF voltage diodes can be selected to replace both D3 and J1, plus the use of higher resistance for R4. 5. S1 is shorted by default to ground the IN1 signal. This short can be removed if IN1 cannot be grounded. Once inspection is done, the evaluation board can be powered up in five simple steps (see Figure 1), to test either one of the top and bottom half bridge inverter arms in simulation mode without the need of actual IGBT (or Power MOSFET). Testing Either Arm of The Half Bridge Inverter Driver (without IGBT) 1. Solder a 10 nf capacitor across gate and emitter terminals of Q5 (to simulate actual gate capacitance of IGBT/power MOSFET). 2. Connect a +5 V DC supply (DC supply 1) across +5 V and GND terminals of CON1. 3. Connect another DC supply (DC Supply 2 with voltage range from 21. V ~ 30 V) across V cc2 (+15V) and V ee (-. V ~ -15 V) terminals of CON2. This can be non-isolated for testing purpose. 4. Supply a 10 khz 5 V DC pulse (at 50% duty) from a signal generator across IN1+ & IN1 pins of CON1 to simulate microcontroller output to drive either arm of the half bridge Inverter. 5. Use a multi-channel digital oscilloscope to capture the waveforms at the following points: a. LED signal at IN1+ pin with reference to (w.r.t.) GND. b. Fault output for any fault signal appearing at pin w.r.t. GND. c. V outn for the negative output voltage of ACPL-339J at U1 pin 11 w.r.t. V e (COM pin). d. V outp for the positive output voltage of ACPL-339J at U1 pin 12 w.r.t. V e. e. V gmos for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. V e. f. V desat for the DESAT voltage of Q5/Q Collector w.r.t. V e. g. VgIGBT for the gate driving voltage of Q5/Q Gate w.r.t. V e. Note: A DESAT fault can be simulated by removing the S2 Jumper.
GND DC Supply 1 5f 5g 5a 2 IN1+ Signal Input 4 IN1 5b 5d 5c 10 nf 1 5e 3 21. V ~ 30 V DC Supply 2 Figure 1. Simple Simulation Test Setup of Evaluation Board Schematics Figure 2 shows the schematics of the Evaluation Board. IN1+ IN1- GND CON1 Vcc1 C1 220p R1 270 R2 270 S1 C2 220p Vcc1 C3 GND 330n R3 10k C4 1n 1 2 3 4 5 7 8 NC CATHODE ANODE CATHODE V GND1 V CC1 V GND1 IC1 ACPL-339J 1 V E 15 DESAT 14 V GMOS 13 V CC2 12 V OUTP 11 V OUTN 10 V LED 9 V EE Vcc2 C5 + + C VEE 1µ Tant 20V C7 + 10µ Tant 35V D2 1µ Tant 20V C8 DFLS220L 100p R4 100 Si745DP R5 15 (½W) Q1 R 15 (½W) Si7848BDP Q2 J1 BYM2E D3 470 R9 S2 R7//R7a 10R (½W) 10R (½W) 10R (½W) R10 10R (½W) 330 R8 //R8a Q3 15V BZG03C15TR3 Caution: Please remove S2 jumpers if IGBT/Power Mosfet is connected to Q5 (or Q) Si2318 1k (½W) R11 D1 VE 21.V~30V G VE VEE NM VCC2 VEE VE C Q5 G CON2 NM E C Q E IGBT (or Power Mosfet) (TO-220 & TO-247) Figure 2. Schematics of ACPL-339J Evaluation Board 2
Practical Connections of the Evaluation Board Using IGBT/Power MOSFET for Actual Inverter Test 1. Solder actual IGBTs/Power MOSFETs at Q5 (or Q) for the top and bottom arms of the Half Bridge Inverter Isolated Drivers. 2. Connect a +5 V DC isolated supply 1 across +5 V and GND terminals of CON1 for both arms of the Isolated Drivers. 3. Connect another isolated DC supply 2 (voltage range from 21. V ~ 30 V) across V cc2 and V ee terminals of CON2 for top arm. 4. Connect another isolated DC supply 3 (voltage range from 21. V ~ 30 V) across V cc2 and V ee terminals of CON2 for bottom arm. 5. Connect the signal output (meant to drive the top arm of half-bridge Inverter) from the microcontroller to Signal Input 1 across pin IN1+ and IN1 of CON1 w.r.t. GND of Top Inverter Arm Isolated Driver.. Connect the signal output (meant to drive the bottom arm of half-bridge Inverter) from the microcontroller to Signal Input 2 across pin IN1+ and IN1 of CON1 w.r.t. GND of Bottom Inverter Arm Isolated Driver. 7. Use a multi-channel Digital Oscilloscope to capture the waveforms at these points: a. LED signal at IN1+ pin with reference to (w.r.t.) GND for Top Arm b. LED signal at IN1+ pin w.r.t. GND for Bottom Arm c. Fault output for any fault signal appearing at 1 w.r.t. GND d. Fault output for any fault signal appearing at 2 w.r.t. GND e. V gmos for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. V e of Top Inverter Arm (differential probe needed) f. V gmos for the gmos output voltage of ACPL-339J at U1 pin 14 w.r.t. V e of Bottom Inverter Arm (differential probe needed) g. V desat for the DESAT voltage of Q5 (or Q) w.r.t. V e of Top Inverter Arm (differential probe needed) h. V desat for the DESAT voltage of Q5 (or Q) w.r.t. V e of Bottom Inverter Arm (differential probe needed) i. V gigbt for the gate driving voltage of Q5/Q w.r.t. V e of Top Inverter Arm (differential probe needed) j. V gigbt for the gate driving voltage of Q5/Q w.r.t. V e of Bottom Inverter Arm (differential probe needed) 8. Connect the high voltage cable from Top Arm IGBT Emitter pin to the Bottom Arm IGBT Collector pin and then to the Inverter load. 9. Connect the high voltage cables from Top Arm IGBT Collector to HVDC+ and from Bottom Arm IGBT Emitter to HVDC respectively as shown. Note: To protect the Inverter and its driver circuitries, it is recommended that you enable the current limiting function of the HV supply supplying the High Voltage DC Bus during this test. 3
HVDC+ 7c 5 IN1+ IN1 1 GND DC Supply 1 2 Signal Input 1 Top Inverter Arm Isolated Driver 1 IGBT mounted at Q5 (or Q) 9 Note: S2 jumper must be removed before this connection Top Arm of Half-Bridge Inverter Circuit Microcontroller V e 3 21. V ~ 30 V DC Supply 2 8 To Load Bottom Inverter Arm Isolated Driver IN1+ IN1 7d 2 Signal Input2 1 IGBT mounted at Q5 (or Q) Bottom Arm of Half- Bridge Inverter Circuit Figure 3. Connection of Evaluation Board in Actual Applications V e 4 21. V ~ 30 V DC Supply 3 Note: S2 jumper must be removed before this connection 9 HVDC 4
Application Circuit Description The ACPL-339J is an advanced isolated gate driver that provides 1.0 A output current, suitable for IGBT and power MOSFET. It is also designed to drive different sizes of MOSFET buffer stage that will make the class of IGBT scalable. ACPL- 339J provides a single isolation solution suitable for both low and high power ratings of motor control and inverter applications. The input LED is optically coupled to an integrated circuit with two power output stages under nonoverlapping timing protection to prevent cross conduction at external MOSFET buffers at Q1 and Q2. Each of the ACPL-339J evaluation boards (see Figure 4) accommodates an ACPL-339J IC. Two boards are needed to drive top and bottom arms of the Half-bridge Inverter. It allows the designer to easily test the performance of gate driver in an actual application under real-life operating conditions. Figure 2 shows the typical de-saturation protected gate drive circuit that is implemented on the evaluation board. Operation of the evaluation board merely requires the inclusion of a common 5V DC isolated supply on the input side and two isolated DC supplies (range from 21. V ~ 30 V): one for top arm and one for the bottom arm across V cc2 and V ee. The V cc2 voltage will then be fixed at +15 V by a Zener diode at D1, while the balance of the supplied voltage (21. V ~ 30 V minus 15 V) will be built across the 1 kω resistor (R11) to set the negative V ee voltage, all with reference to V e at each arm. Note: As can be seen on the board, the isolation circuitry (at the far left) is easily contained within a small area while maintaining adequate spacing for good voltage isolation and easy assembly. Figure 4. Top and Bottom Views of ACPL-339J Evaluation Board 5
a) Operations of various outputs The outputs (V OUTP, V OUTN, V GMOS and ) of each ACPL-339J are governed by the combination of I F (the LED current), UVLO and DESAT conditions. Once the UVLOP+ and UVLON signals are not active (V CC2 - V E > V UVLOP+, V E - V EE > V UVLON+ ), V OUTP is allowed to go low and V OUTN is allowed to go high. Thereafter, the DESAT (pin 15) detection feature of the ACPL-339J will be the primary source of IGBT/Power MOSFET protection. DESAT will remain functional until V CC2 - V E is decreased below V UVLOP- or V E - V EE is decreased below V UVLON-. Therefore, the DESAT detection and UVLO features of the ACPL-339J work alternatively to ensure constant IGBT/MOSFET protection. Table 1 shows the possible output combinations for Fault, V outp, V outn and V gmos under the influence of different UVLO and DESAT operating conditions, whether they are active or not. Table 1 I F UVLOP and UVLON DESAT Function Pin 7 () Output V OUTP V OUTN V GMOS X Active Not Active High High Low V E ON Not Active Active (with DESAT fault) High High Low V E ON Not Active Active (no DESAT fault) Low Low High V EE OFF Not Active Not Active Low High Low V EE Note: Normal operating condition is highlighted in blue in the table; X denotes Don t Care; Logic output of V GMOS will be changed from V EE to V E when UVLON is active. This will ensure that MN3 is turned on to shut down the IGBT/SiC FET when insufficient power supply V E -V EE is applied. b) Soft-shutdowns from DESAT and UVLO faults The DESAT pin of each device monitors its IGBT V ce voltage. The internal DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT blanking capacitor (C8, at 100 pf). The nominal blanking time is calculated in terms of external capacitance (C BLANK ), threshold voltage (V DESAT ), and DESAT charge current (I CHG ) as T BLANK = C BLANK V DESAT / I CHG. The nominal blanking time with the recommended 100 pf capacitor is 100 pf * 8 V / 250 µa = 3.2 µsec. This nominal blanking time also represents the longest time it will take for each ACPL-339J to respond to a DESAT fault condition. After T BLANK time, both V OUTP and V OUTN outputs will turn off the respective external Q1 and Q2 MOSFETs and V GMOS switches from Low to High, turning on an external Q3 pull-down MOSFET, to softly turn off the IGBT. Also activated is an internal feedback channel that brings the isolated output from Low to High to notify the microcontroller of the fault condition. Once fault is detected, the output will be muted for T MUTE time. All input LED signals will be ignored during the mute period to allow the driver to completely do a soft shutdown of the IGBT. The fault is auto-reset upon the 1 ms (typical) mute time (T MUTE ) timeout or upon the change in IN1 status from High to Low transition, whichever is later. In this way there is a minimum timeout, yet there is still flexibility of lengthening the timeout. When a DESAT fault is detected, its device s V GMOS output switches from Low to High, turning on the external Q3 MOSFET pull-down device. Q3 slowly discharges the IGBT gate voltage at a decay rate corresponding to the RC constant of RS and C IN (the IGBT input capacitance). Based on a RS of 330 Ω (as in R10) and C IN of 10 nf(from the external connected capacitor at Q5 or Q), the entire soft shut down will decay in 4.8 * 330 Ω * 10 nf = 15.8 µs. Soft shutdown prevents fast changes of the collector current that could cause damaging voltage spikes due to lead and wire inductance. Similarly, when under voltage operation occurs during normal operation, its device s V GMOS output switches from Low to High, turning on the external Q3 MOSFET pull-down device. Q3 slowly discharges the IGBT gate voltage at a decay rate corresponding to the RC constant of RS and C IN (the IGBT input capacitance). The entire soft shutdown will decay in 15.8 µs to prevent fast changes in the collector current.
Using the Board It is easy to prepare the evaluation board for use. Only minor preparations (just by soldering cables for DC supplies, proper cables for HVDC+/HVDC high voltage bus, and load connections) are required. The evaluation board has a default setup (as shown in Table 2) when it is shipped to the customer. The customer is free to select different settings for J1, S1 and S2 for his different needs. Table 2 Recommended PWM frequency V cc1 V cc2 w.r.t. Vee J1 S1 S2 Default Setup 1 khz to 50 khz (0 ~ 5 V) dc 21. V ~ 30 V Shorted Shorted Shorted J1 is provided to let customer to adjust the DESAT fault detection voltage to 7 V by replacing it with another BYM2E. S1 jumper is shorted to ground the IN1-. This can be open if differential signal is used across IN1+ & IN1 to drive the LED. S2 jumper can be shorted when IGBT/Power MOSFET are not connected to Q5 (or Q) to stop the DESAT fault from occurring. It has to be open, however, when IGBT/Power MOSFET are connected to activate the DESAT fault protection. Output Measurement Figure 5 and Figure show a sample of Input LED and various output waveforms that have been captured. The soft shutdown waveform are shown clearly in V gigbt waveform. LED ON I F 8 V LED OFF V DESAT V GMOS Soft Shutdown V G(IGBT) V OUTN Ext NMOS OFF Ext NMOS ON V OUTP Ext PMOS ON Ext PMOS OFF Figure 5. Input LED (t ON < t MUTE ) and various output voltage waveforms 7
LED ON I F 8 V LED OFF V DESAT V GMOS Soft Shutdown V G(IGBT) V OUTN Ext NMOS OFF Ext NMOS ON V OUTP Ext PMOS ON Ext PMOS OFF Figure. Input LED (t ON > t MUTE ) and various output voltage waveforms Figure 5 and Figure also show that, once DESAT fault is detected, the output (V gigbt ) will be muted for T MUTE time where input LED signals will be ignored during the mute period to allow for the driver to completely perform a soft shutdown of the IGBT. The fault is auto-reset upon the 1 ms (typical) mute time (T MUTE ) timeout or upon LED Input High to Low transition, whichever is later. In this way there is a minimum timeout, yet there is still flexibility of lengthening the timeout, as in Figure. Performing OR on the Fault Circuits During normal operation of the circuit under no fault condition, LED2 of U1 (IC1) are activated and normally On, to pull their respective pin 7 Low. To improve on the operating efficiencies, and at the same time to allow for easy bootstrapping, the LEDs are made to operate at 50% duty cycle at a frequency of 5 MHz through internal oscillator circuits. This, however, causes the open collector Fault output at pin 7 of U1 to toggle at undesirable High and Low levels if only pull-up resistors are connected. To filter away the unwanted oscillating outputs and to keep it at a Low level, an RC network each is connected (see Figure 7) for both ICs (IC1 and IC2) in the Top and Bottom Arms of the Half- Bridge Inverter Drivers. Corner frequencies of both networks are set at around 15 ~ 1 khz to have effective filtering. During an actual fault condition, however, pin 7 will be pulled High. Due to this positive (or High ) logic, the Fault pins cannot be tied together to achieve a common Fault level if one and only one of the Inverter Arms experiences a fault. Tying the Fault pins together causes the voltage level of both Fault pins to stay Low when only one of the ICs experiences a fault this is undesirable. To overcome such a problem and to allow the circuit to correctly report a common Fault level to the microcontroller, a circuit that performs the OR function consists of an NPN transistor and a base resistor can each be connected to the Fault pin of their respective IC. As shown in Figure 7, the collector outputs can then be tied (perform an OR) together before a pull-up resistor and the point on which the OR is performed represents a common Fault signal, albeit in a reversed logic. 8
47k IC1 47k R 10k V CC1 7 LED2 2N3904 C 1 nf GND1 5,8 SHIELD ACPL-339J IC2 47k R 10k V CC1 7 LED2 2N3904 C 1 nf GND1 5,8 SHIELD ACPL-339J Figure 7. Performing an OR on the Fault Outputs Of IC1 (Top Arm) and IC2 (Bottom Arm) For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2005-2014 Avago Technologies. All rights reserved. AV02-3957EN - July 24, 2014