PD-97574A RADIATION HARDENED LOGIC LEVEL POWER MOSFET SURFACE MOUNT (LCC-6) 6V, DUAL P-CHANNEL R 7 TECHNOLOGY Product Summary Part Number Radiation Level RDS(on) I D krads(si).6 -.65A IRHLUC793Z4 3 krads(si).6 -.65A LCC-6 Description IR HiRel R7 Logic Level Power MOSFETs provide simple solution to interfacing CMOS and TTL control circuits to power devices in space and other radiation environments. The threshold voltage remains within acceptable operating limits over the full operating temperature and post radiation. This is achieved while maintaining single event gate rupture and single event burnout immunity. The device is ideal when used to interface directly with most logic gates, linear IC s, micro-controllers, and other device types that operate from a 3.3-5V source. It may also be used to increase the output current of a PWM, voltage comparator or an operational amplifier where the logic level drive signal is available. Features 5V CMOS and TTL Compatible Low R DS(on) Fast Switching Single Event Effect (SEE) Hardened Low Total Gate Charge Simple Drive Requirements Hermetically Sealed Light Weight Complimentary N-Channel Available - IRHLUC77Z4 Absolute Maximum Ratings Symbol Parameter Value Units I D @ V GS = -4.5V, T C = 25 C Continuous Drain Current -.65 I D2 @ V GS = -4.5V, T C = C Continuous Drain Current -.4 I DM @ T C = 25 C Pulsed Drain Current -2.6 P D @T C = 25 C Maximum Power Dissipation. W Linear Derating Factor. W/ C V GS Gate-to-Source Voltage ± V E AS Single Pulse Avalanche Energy 34 mj I AR Avalanche Current -.65 A E AR Repetitive Avalanche Energy. mj dv/dt Peak Diode Recovery dv/dt -5.6 V/ns T J T STG Operating Junction and -55 to + 5 Storage Temperature Range C Package Mounting Surface Temp 3 (for 5s) Weight.2 (Typical) g A For Footnotes, refer to the page 2. International Rectifier HiRel Products, Inc.
Electrical Characteristics for each P-Channel Die @ Tj = 25 C (Unless Otherwise Specified) Symbol Parameter Min. Typ. Max. Units Test Conditions BV DSS Drain-to-Source Breakdown Voltage -6 V V GS = V, I D = -25µA BV DSS / T J Breakdown Voltage Temp. Coefficient -.6 V/ C Reference to 25 C, I D = -.ma R DS(on) Static Drain-to-Source On-Resistance.6 VGS = -4.5V, I D2 = -.4A V GS(th) Gate Threshold Voltage -. -2. V V GS(th) / T J Gate Threshold Voltage Coefficient 3.6 mv/ C V DS = V GS, I D = -25µA gfs Forward Transconductance.6 S V DS = -5V, I D2 = -.4A I DSS -. V DS = -48V, V GS = V Zero Gate Voltage Drain Current µa - V DS = -48V,V GS = V,T J =25 C I GSS Gate-to-Source Leakage Forward - V GS = -V na Gate-to-Source Leakage Reverse V GS = V Q G Total Gate Charge 3.6 I D = -.65A Q GS Gate-to-Source Charge.5 nc V DS = -3V Q GD Gate-to-Drain ( Miller ) Charge.8 V GS = -4.5V t d(on) Turn-On Delay Time 23 V DD = -3V t r Rise Time 22 I D = -.65A ns t d(off) Turn-Off Delay Time 32 R G = 24 t f Fall Time 26 V GS = -5.V Ls +L D Total Inductance 33 nh Source-Drain Diode Ratings and Characteristics (Per P Channel Die) Symbol Parameter Min. Typ. Max. Units Test Conditions I S Continuous Source Current (Body Diode) -.65 I SM Pulsed Source Current (Body Diode) -2.6 V SD Diode Forward Voltage -5. V T J =25 C, I S = -.65A, V GS =V t rr Reverse Recovery Time 35 ns T J =25 C, I F = -.65A,V DD -25V Q rr Reverse Recovery Charge 9.8 nc di/dt = -A/µs t on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by L S +L D ) A Measured from the center of drain pad to center of source pad C iss Input Capacitance 47 V GS = V C oss Output Capacitance 46 pf V DS = -25V C rss Reverse Transfer Capacitance 8. ƒ =.MHz R G Gate Resistance 52 ƒ =.MHz, open drain Thermal Resistance (Per P Channel Die) Symbol Parameter Min. Typ. Max. Units R JA Junction-to-Ambient 25 C/W Test Conditions Typical socket mount Footnotes: Repetitive Rating; Pulse width limited by maximum junction temperature. V DD = -25V, starting T J = 25 C, L = 6mH, Peak I L = -.65A, V GS = -V I SD -.65A, di/dt -5A/µs, V DD -6V, T J 5 C Pulse width 3 µs; Duty Cycle 2% Total Dose Irradiation with V GS Bias. - volt V GS applied and V DS = during irradiation per MIL-STD-75, Method 9, condition A. Total Dose Irradiation with V DS Bias. 48 volt V DS applied and V GS = during irradiation per MlL-STD-75, Method 9, condition A. 2 International Rectifier HiRel Products, Inc.
Radiation Characteristics IR HiRel radiation hardened MOSFETs are tested to verify their radiation hardness capability. The hardness assurance program at IR Hirel is comprised of two radiation environments. Every manufacturing lot is tested for total ionizing dose (per notes 5 and 6) using the TO-39 package. Both pre- and post-irradiation performance are tested and specified using the same drive circuitry and test conditions in order to provide a direct comparison. Table. Electrical Characteristics For P Channel @ Tj = 25 C, Post Total Dose Irradiation Symbol Parameter Up to 3 krads (Si) Units Test Conditions BV DSS Drain-to-Source Breakdown Voltage -6 V V GS = V, I D = -25µA Min. V GS(th) Gate Threshold Voltage -. -2. V V DS = V GS, I D = -25µA I GSS Gate-to-Source Leakage Forward - na V GS = -V I GSS Gate-to-Source Leakage Reverse na V GS = V I DSS Zero Gate Voltage Drain Current -. µa V DS = -48V, V GS = V R DS(on) R DS(on) Static Drain-to-Source On-State Resistance (TO-39) Static Drain-to-Source On-State Resistance (LCC -6) Max..4 V GS = -4.5V, I D2 = -.4A.6 V GS = -4.5V, I D2 = -.4A V SD Diode Forward Voltage -5. V V GS = V, I S = -.65A. Part numbers and IRHLUC793Z4 IR HiRel radiation hardened MOSFETs have been characterized in heavy ion environment for Single Event Effects (SEE). Single Event Effects characterization is illustrated in Fig. a and Table 2. Table 2. Typical Single Event Effect Safe Operating Area LET (MeV/(mg/cm 2 )) Energy (MeV) Range (µm) V 2V VDS (V) 4V 5V 6V 7V 38 ± 5% 3 ± 7.5% 38 ± 7.5% -6-6 -6-6 -6-5 62 ± 5% 355 ± 7.5% 33 ± 7.5% -6-6 -6-6 -6 85 ± 5% 38 ± 7.5% 29 ± 7.5% -6-6 -6-6 Bias VDS (V) -7-6 -5-4 -3-2 - 2 3 4 5 6 7 Bias VGS (V) LET=38 ± 5% LET=62 ± 5% LET=85 ± 5% Fig a. Typical Single Event Effect, Safe Operating Area For Footnotes, refer to the page 2. 3 International Rectifier HiRel Products, Inc.
-I D, Drain-to-Source Current (A) -I D, Drain-to-Source Current ( ) R DS (on), Drain-to -Source On Resistance ( ) R DS(on), Drain-to-Source On Resistance (Normalized) -I D, Drain-to-Source Current (A) VGS TOP -V -5.V -4.V -3.5V -3.V -2.5V -2.25V BOTTOM -2..V VGS TOP -V -5.V -4.V -3.5V -3.V -2.5V -2.25V BOTTOM -2..V. -2.V -2.V 6 s PULSE WIDTH Tj = 25 C.. -V DS, Drain-to-Source Voltage (V) Fig. Typical Output Characteristics 6 s PULSE WIDTH Tj = 5 C.. -V DS, Drain-to-Source Voltage (V) Fig 2. Typical Output Characteristics 2. I D = -.65A T J = 25 C.5 T J = 5 C.. V DS = -25V 6 s PULSE WIDTH 2 2.5 3 3.5 4 4.5 -V GS, Gate-to-Source Voltage (V).5 V GS = -4.5V -6-4 -2 2 4 6 8 2 4 6 T J, Junction Temperature ( C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature R DS(on), Drain-to -Source On Resistance ( ) 4 3.2 3.5 3 I D = -.65A 2.8 2.5 2 T J = 5 C 2.4 2. T J = 5 C.5.5 T J = 25 C 2 3 4 5 6 7 8 9 2.6.2.8 T J = 25 C Vgs = -4.5V.5..5 2. 2.5 3. -V GS, Gate -to -Source Voltage (V) -I D, Drain Current (A) Fig 5. Typical On-Resistance Vs Gate Voltage Fig 6. Typical On-Resistance Vs Drain Current 4 International Rectifier HiRel Products, Inc.
-V (BR)DSS, Drain-to-Source Breakdown Voltage (V) -I SD, Reverse Drain Current (A) -I D, Drain Current (A) C, Capacitance (pf) -V GS, Gate-to-Source Voltage (V) -V GS(th) Gate threshold Voltage (V) 8 2.5 I D = -.ma 2. 7.5 6 5-6 -4-2 2 4 6 8 2 4 6 T J, Temperature ( C ). I D = -5µA I.5 D = -25µA I D = -.ma I D = -5mA. -6-4 -2 2 4 6 8 2 4 6 T J, Temperature ( C ) Fig 7. Typical Drain-to-Source Breakdown Voltage Vs Temperature Fig 8. Typical Threshold Voltage Vs Temperature 24 2 V GS = V, f = MHz C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd 2 I D = -.65A V DS = -48V V DS = -3V V DS = -2V 6 C iss 8 2 6 C oss 8 4 4 C rss -V DS, Drain-to-Source Voltage (V) 2 FOR TEST CIRCUIT SEE FIGURE 7 7.5.5 2 2.5 3 3.5 4 4.5 Q G, Total Gate Charge (nc) Fig 9. Typical Capacitance Vs. Drain-to-Source Voltage Fig. Typical Gate Charge Vs. Gate-to-Source Voltage.7.6 T J = 5 C.5.4 T J = 25 C.3..2. V GS = V.5.5 2 2.5 3 3.5 4 4.5 5. -V SD, Source-to-Drain Voltage (V). 25 5 75 25 5 T C, Case Temperature ( C) Fig. Typical Source-Drain Diode Forward Voltage Fig 2. Maximum Drain Current Vs.Case Temperature 5 International Rectifier HiRel Products, Inc.
-I D, Drain-to-Source Current (A) E AS, Single Pulse Avalanche Energy (mj) OPERATION IN THIS AREA LIMITED BY R DS (on) 8 7 6 5 TOP BOTTOM I D -.29A -.4A -.65A ms 4.. Tc = 25 C Tj = 5 C Single Pulse ms DC -V DS, Drain-to-Source Voltage (V) 3 2 25 5 75 25 5 Starting T J, Junction Temperature ( C) Fig 3. Maximum Safe Operating Area Fig 4. Maximum Avalanche Energy Vs. Drain Current Thermal Response ( Z thja ) D =.5.2..5 SINGLE PULSE.2 ( THERMAL RESPONSE ).. Notes:. Duty Factor D = t/t2 2. Peak Tj = P dm x Zthjc + Tc. E-5.... t, Rectangular Pulse Duration (sec) Fig 5. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient 6 International Rectifier HiRel Products, Inc.
Fig 6a. Unclamped Inductive Test Circuit Fig 6b. Unclamped Inductive Waveforms Fig 7a. Gate Charge Waveform Fig 7b. Gate Charge Test Circuit Fig 8a. Switching Time Test Circuit Fig 8b. Switching Time Waveforms 7 International Rectifier HiRel Products, Inc.
Case Outline and Dimensions LCC-6.245 ±..8.65.9 Max. ±.8.7 ±..5 Pin. 5 6 4.25 Pin 3 2 Notes:. Outline conforms to MIL PRF 95/255L 2. All dimensions are shown in inches 3. Controlling dimension: Inch Die 2 (P Ch) Pin # Pin Name 5 Gate 4 Drain 3 Source Die (P Ch) Pin # Pin Name 6 Source Drain 2 Gate www.infineon.com/irhirel Infineon Technologies Service Center: USA Tel: + (866) 95-959 and International Tel: +49 89 234 65555 Leominster, Massachusetts 453, USA Tel: + (978) 534-5776 San Jose, California 9534, USA Tel: + (48) 434-5 8 International Rectifier HiRel Products, Inc.
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