Logic level four-quadrant triac. Passivated sensitive gate 4-Q triac in a SOT223 surface-mountable plastic package

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Rev. 4 6 September 21 Product data sheet 1. Product profile 1.1 General description Passivated sensitive gate 4-Q triac in a SOT223 surface-mountable plastic package 1.2 Features and benefits Direct interfacing to logic level ICs Direct interfacing to low power gate drive circuits High blocking voltage of 6V Sensitive gate in four quadrants Surface-mountable package 1.3 Applications General purpose low power motor control Home appliances Industrial process control Low power AC Fan controllers 1.4 Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V DRM repetitive peak off-state - - 6 V voltage I T(RMS) RMS on-state current half sine wave; T sp 89 C; see Figure 2; see Figure 1 - - 1 A Static characteristics I GT gate trigger current V D =12V; I T =.1 A; T2+ G+; - - 3 ma T j = 25 C; see Figure 8 V D =12V; I T =.1 A; T2+ G-; - - 3 ma T j = 25 C; see Figure 8 V D =12V; I T =.1 A; T2- G-; - - 3 ma T j = 25 C; see Figure 8 V D =12V; I T =.1 A; T2- G+; T j = 25 C; see Figure 8 - - 5 ma

2. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 T1 main terminal 1 2 T2 main terminal 2 4 T2 3 G gate 4 T2 main terminal 2 1 2 3 SOT223 (SC-73) sym51 T1 G 3. Ordering information Table 3. Type number Ordering information Package Name Description Version SC-73 plastic surface-mounted package with increased heatsink; SOT223 4 leads 4. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 6134). Symbol Parameter Conditions Min Max Unit V DRM repetitive peak off-state voltage - 6 V I T(RMS) RMS on-state current half sine wave; T sp 89 C; see Figure 2; see Figure 1-1 A I TSM non-repetitive peak on-state full sine wave; T j(init) =25 C; t p = 16.7 ms - 8.5 A current full sine wave; T j(init) =25 C; t p = 2 ms; - 8 A see Figure 3; see Figure 4 I 2 t I2t for fusing t p = 1 ms; sine-wave pulse -.32 A 2 s di T /dt rate of rise of on-state current I T =1A; I G =2mA; di G /dt = 1 ma/µs; - 5 A/µs T2+ G- I T =1A; I G =2mA; di G /dt = 1 ma/µs; - 5 A/µs T2+ G+ I T =1A; I G =2mA; di G /dt = 1 ma/µs; - 2 A/µs T2- G+ I T =1A; I G =2mA; di G /dt = 1 ma/µs; - 5 A/µs T2- G- I GM peak gate current - 1 A P GM peak gate power - 2 W P G(AV) average gate power over any 2 ms period -.1 W T stg storage temperature -4 15 C T j junction temperature - 125 C All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 2 of 15

1.2 3aad391 I T(RMS) (A).8.4 5 5 1 15 T sp ( C) Fig 1. Maximum permissible RMS on-state current as a function of solder point temperature; typical values. P tot (W) 2. 1.6 1.2 conduction angle (degrees) 3 6 9 12 18 form factor a 4 2.8 2.2 1.9 1.57 α α = 18 12 9 3aac259.8 6 3.4..2.4.6.8 1 1.2 I T(RMS) (A) Fig 2. Total power dissipation as a function of RMS on-state current; maximum values All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 3 of 15

1 3aad318 I TSM (A) 8 6 4 I T I TSM 2 1 1 1 2 1 3 number of cycles 1/f T j(init) = 25 C max t Fig 3. Non-repetitive peak on-state current as a function of the number of sinusoidal current cycles; maximum values I TSM (A) 1 3 I T 3aad319 I TSM t 1 2 (1) t p T j(init) = 25 C max 1 (2) 1 1 5 1 4 1 3 1 2 t p (s) 1 1 Fig 4. Non-repetitive peak on-state current as a function of pulse width; maximum values All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 4 of 15

5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R th(j-sp) thermal resistance from see Figure 7 - - 25 K/W junction to solder point R th(j-a) thermal resistance from junction to ambient minimum footprint; printed-circuit board mounted; in free air; see Figure 5 pad area; printed-circuit board mounted; in free air; see Figure 6-156 - K/W - 7 - K/W 3.8 min 36 1.5 min 18 1.5 min (3 ) 2.3 6.3 6 9 1 4.6 4.5 1.5 min 4.6 All dimensions are in mm 1aab58 7 15 5 1aab59 All dimensions are in mm Printed-circuit board: FR4 epoxy glass (1.6 mm thick), copper laminate (35 um thick), Fig 5. Minimum footprint SOT223 Fig 6. Printed-circuit board pad area SOT223 All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 5 of 15

1 2 3aad39 Z th(j-sp) (K/W) 1 1 P 1 1 t p t 1 2 1 5 1 4 1 3 1 2 1 1 t p (s) 1 1 Fig 7. Transient thermal impedance from junction to solder point as a function of pulse duration All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 6 of 15

6. Characteristics Table 6. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics I GT gate trigger current V D =12V; I T =.1 A; T2+ G+; T j =25 C; - - 3 ma see Figure 8 V D =12V; I T =.1 A; T2+ G-; T j =25 C; - - 3 ma see Figure 8 V D =12V; I T =.1 A; T2- G-; T j =25 C; - - 3 ma see Figure 8 V D =12V; I T =.1 A; T2- G+; T j =25 C; - - 5 ma see Figure 8 I L latching current V D =12V; I G =.1 A; T2+ G+; T j =25 C; - - 7 ma see Figure 9 V D =12V; I G =.1 A; T2+ G-; T j =25 C; - - 15 ma see Figure 9 V D =12V; I G =.1 A; T2- G+; T j =25 C; - - 7 ma see Figure 9 V D =12V; I G =.1 A; T2- G-; T j =25 C; - - 7 ma see Figure 9 I H holding current V D =12V; T j =25 C; see Figure 13 - - 7 ma V T on-state voltage I T = 1 A; see Figure 1-1.3 1.6 V V GT gate trigger voltage V D =12V; I T =.1 A; T j =25 C; - - 1.3 V see Figure 11 V D =6V; I T =.1 A; T j = 125 C.2 - - V I D off-state current V D =6V; T j = 125 C - -.5 ma Dynamic characteristics dv D /dt rate of rise of off-state voltage V DM =42V; T j = 11 C; gate open circuit; see Figure 12 1 - - V/µs dv com /dt rate of change of commutating voltage V D =4V; T j =11 C; di com /dt =.44 A/ms; gate open circuit.5 - - V/µs All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 7 of 15

4 3aaa25 3 3aaa23 I GT I L I GT(25 C) I L(25 C) 3 2 (1) (2) (3) (4) 2 1 1 5 5 1 15 T j ( C) 5 5 1 15 T j ( C) (1) T2- G+ (2) T2- G- (3) T2+ G- (4) T2+ G+ Fig 8. Normalized gate trigger current as a function of junction temperature Fig 9. Normalized latching current as a function of junction temperature 2 3aac258 1.6 3aaa29 I T (A) 1.6 V GT V GT(25 C) 1.2 1.2.8.8 (1) (2) (3).4.4.4.8 1.2 1.6 2 V T (V) V o = 1. V R s =.21 Ω (1) T j = 125 C; typical values (2) T j = 125 C; maximum values (3) T j = 25 C; maximum values Fig 1. On-state current as a function of on-state voltage 5 5 1 15 T j ( C) Fig 11. Normalized gate trigger voltage as a function of junction temperature All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 8 of 15

1.6 3aaa28 A 1.2.8.4 5 1 15 T j ( C) Fig 12. Normalized critical rate of rise of off-state voltage as a function of junction temperature; typical values 3 3aaa24 I H I H(25 C) 2 1 5 5 1 15 T j ( C) Fig 13. Normalized holding current as a function of junction temperature All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 9 of 15

7. Package outline Plastic surface-mounted package with increased heatsink; 4 leads SOT223 D B E A X c y H E v M A b 1 4 Q A A 1 1 2 3 L p e 1 b p w M B detail X e 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A 1 b p b 1 c D E e e 1 H E L p Q v w y mm 1.8 1.5.1.1.8.6 3.1 2.9.32.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1.7.95.85.2.1.1 OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT223 SC-73 4-11-1 6-3-16 Fig 14. Package outline SOT223 (SC-73) All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 1 of 15

8. Soldering 7 3.85 3.6 3.5.3 1.3 (4 ) 1.2 (4 ) 4 solder lands solder resist 3.9 6.1 7.65 solder paste 1 2 3 occupied area Dimensions in mm 2.3 2.3 1.2 (3 ) 1.3 (3 ) 6.15 sot223_fr Fig 15. Reflow soldering footprint for SOT223 (SC-73) 8.9 6.7 1.9 4 solder lands 6.2 8.7 solder resist occupied area 1 2 3 1.9 (3 ) Dimensions in mm preferred transport direction during soldering 2.7 2.7 1.1 1.9 (2 ) sot223_fw Fig 16. Wave soldering footprint for SOT223 (SC-73) All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 11 of 15

9. Revision history Table 7. Revision history Document ID Release date Data sheet status Change notice Supersedes v.4 2196 Product data sheet - v.3 Modifications: Various changes to content. v.3 2985 Product data sheet - Z13_7_9_SERIES v.2 All information provided in this document is subject to legal disclaimers. NXP B.V. 21. All rights reserved. Product data sheet Rev. 4 6 September 21 12 of 15

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12. Contents 1 Product profile...........................1 1.1 General description......................1 1.2 Features and benefits.....................1 1.3 Applications............................1 1.4 Quick reference data.....................1 2 Pinning information.......................2 3 Ordering information......................2 4 Limiting values...........................2 5 Thermal characteristics...................5 6 Characteristics...........................7 7 Package outline.........................1 8 Soldering.............................. 11 9 Revision history.........................12 1 Legal information........................13 1.1 Data sheet status.......................13 1.2 Definitions.............................13 1.3 Disclaimers............................13 1.4 Trademarks............................14 11 Contact information......................14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 21. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 September 21 Document identifier: