Using the Wafer Scale Packaged Detector in 2 to 6 GHz Applications Application Note 5525 Introduction The is a broadband directional coupler with integrated temperature compensated detector designed for 2 to 6 GHz applications. The detector provides a DC output proportional to RF power input, providing a means of measuring amplifier power output. The is a three-terminal device with the through 5 Ω transmission line connecting directly between the RF input and RF output ports. A DC bias is fed to the RF input port and the rectified DC is available at the RF output port. Using the With only three terminals available, the DC bias and detected voltage are internally DC coupled to the input and output terminals respectively. The key to successful operation of the is the use of low loss bias decoupling networks connected to both the RF input port and the RF output port. A simple circuit is shown in Figure 1. The bias decoupling networks can take the form of a series inductor-resistor combination shown as L1-R1 and L2-R2 in Figure 1. DC blocking capacitors are used at C1 and C2. Both networks provide a low loss AC coupled RF path to the device and a means of DC biasing the device on the input and a means of extracting the detected voltage on the output of the device. The internal load resistor for the detector is approximately 2 kω. If desired, resistor R3 can be used as an external load resistor for the detector. Although C4 provides additional decoupling, any shunt capacitance at C4 will reduce the video bandwidth of the detector and therefore may not be desirable. The -3 db video bandwidth of the detector itself is approximately 3 MHz. Any additional bypassing external to the device at the output terminal will decrease the bandwidth. More detailed information will follow in a later section of this application note. The suggested bias voltage at the RF input port is 1.5 V. At this nominal bias, the bias current is typically.16 ma. With no RF input power a nominal 6 mv Voffset voltage appears at the detected output port. A plot of DC output versus RF input for the is shown in Figure 2. 1 C1 RF Input L1 L2 R1 R2 C3 R3 C4 Vb Vdet Figure 1. Biasing the detector module C2 RF Output Output DC Voltage (V) 1.1.1-1 5 1 15 2 25 3 35 Pin (dbm) Figure 2. Output DC voltage vs. RF input power for the 2 GHz 3 GHz 4 GHz 5 GHz 6 GHz
PCB Pattern Implementing the bias networks is usually done in microstrip. The recommended printed circuit board via pattern is shown in Figure 3. This is a non-solder mask defined footprint (NSMD). The outline of the solder mask that borders the device is shown by the area indicated in green. The recommended footprint does not require any plated through holes under the device. Modeling and tests indicate that placing vias adjacent to (within.3 ) and on either side of the device, as shown in Figure 3, provides good grounding for the VMMK-3XXX devices when mounted on.1 thick RO435 printed circuit board material. Additional information covering the assembly, cleaning and handling of VMMK products is covered in Avago Application Note AN378. 1.2 (.48).4 (.16).1 (.4).1 (.4).5 (.2).5 (.2) Part of Input Circuit.76 max (.3) 2 pl - see discussion.381 (.15) 2 pl.2 (.8).2 (.8) Figure 3. Recommended PCB layout for VMMK devices Part of Output Circuit.254 dia PTH (.1) 4 pl Solder Mask.4 dia (.16) 4 pl.7 (.28) Demonstrating Performance Demonstrating performance with a demonstration board requires mounting the on a 5 Ω microstrip line with connectors. Rogers 435 printed circuit board material with a 1 mil thickness is used as a low loss substrate for launching in and out of the. The 5 Ω line width is.2. The printed circuit board stack is a multilayer stack which provides rigidity during testing. The total thickness is.6. A Johnson SMA connector, part number 142-761-861, is used to provide a smooth transition to the microstrip line. Bias decoupling networks have been included on the demonstration board to inject a voltage at the input port and as a means to measure the detected voltage at the output port. Measuring the loss of any low loss component over a wide range of frequencies when it is embedded within a circuit board is difficult. To demonstrate the loss of the by itself requires de-embedding all of the printed circuit board losses, including the 5 Ω microstrip line, the bias decoupling lines and the connectors. The loss of these additional components is much greater than the loss of the by itself. A completed demonstration board for the is shown in Figure 4. An additional reference demonstration board with all the biasing components minus the was also built for reference. The difference in the loss between the two boards represents the loss of the by itself. A schematic diagram and parts list are shown in Figures 5 and 6. The demonstration board was designed for use with 42 SMD components. Biasing the at the input port is accomplished with a 2 kω resistor substituted for L1 and a Ω resistor for R1. Using a single resistor instead of a series LC provides greater bandwidth. Based on requiring a Vb of 1.5 V at the input port of the, the required bias voltage for the demonstration board is 4.5 V. The nominal current draw is.15 ma. Figure 4. demonstration board Figure 5. Schematic of the 2 to 7 GHz demonstration board circuit for the 2
Component C1 C2 C3 C4 D1 L1 L2 R1 R2 R3 Description 3.3 pf Murata GRM1555C1H3R3CA1 3.3 pf Murata GRM1555C1H3R3CA1 1 pf 1 pf Murata GRM1555C1H1RCA1 2 Ω 15 nh Murata LQW15AN15NH Ω 1 Ω Not used Figure 6. demonstration board parts list for 2 to 7 GHz application db(s(4,3)) db(s(2,1)) -1-2 -3-4 1 2 3 4 5 6 7 8 9 1 Figure 7. Insertion loss vs. frequency response of demonstration board (blue) vs. reference demonstration board (red). The difference in the curves is the loss of the. A 15 nh inductor was chosen for the output inductor, and although the manufacturer only provides S-parameters to 6 GHz, the inductor provides a high impedance through approximately 8 GHz, even though the inductor is passing through its parallel resonance. A 1 pf capacitor for C4 provides minimal bypassing while still allowing narrow pulses to be detected by the. Figures 7, 8 and 9 show the insertion loss and input and output return loss of the demonstration board and the through reference board. The apparent loss of the can be determined by taking the difference between the red and blue curves shown in Figure 7. The plot suggests less than.4 db loss for the from 2 to 6 GHz. Input and output return loss is typically greater than 1 db from 2.5 to 6 GHz. The low end of the frequency range is limited by the components used on the demonstration board. At the expense of increased loss at 6 GHz, replacing L2 with a 22 nh inductor will help flatten out the response at the low end. Another factor that can influence the performance of the is the inductance provided by the printed circuit board vias. In general, the lowest inductance will provide the lowest insertion loss and best return loss performance of the. The effect of the printed circuit board vias is best evaluated using a linear simulator such as Agilent s Advanced Design System and the published data sheet S-parameters for the. Using the recommended PCB layout, as shown in Figure 3, should minimize the inductance associated with the vias. db(s(3,3)) db(s(1,1)) -1-15 -2-25 -3 1 2 3 4 5 6 7 8 9 1 Figure 8. Input return loss S11 of the demonstration board (blue) vs. the reference demonstration board (red) db(s(4,4)) db(s(2,2)) -1-15 -2-25 -3 1 2 3 4 5 6 7 8 9 1 Figure 9. Output return loss S11 of the demonstration board (blue) vs. the reference demonstration board (red) 3
S-parameter Measurements The device S-parameters are measured on a.16 thick RO43 printed circuit test board, using 3-µm pitch G-S-G (ground-signal-ground) probes. A coplanar waveguide is used to provide a smooth transition from the probes to the device under test. The presence of the ground plane on top of the test board results in excellent grounding at the device under test. A combination of SOLT (Short Open Load Thru) and TRL (Thru - Reflect - Line) calibration techniques are used to correct for the effects of the test board, resulting in accurate device S-parameters. Other circuit approaches The data sheet discusses a coplanar waveguide (CPW) approach (Figure 1) that may integrate into a user application better than microstrip line. Although a CPW approach can provide a lower inductance path for grounding the common lead of the, other circuit elements such as couplers and bias networks may be more difficult to model. The CPW approach is built on.16 thick RO43. The 5 Ω transmission line is.2 in width, and this matches up well with the input pad of the. A.5 gap between the transmission line and the top side CPW ground plane provides optimum dimensions for a 5 Ω transmission line. Biasing the device on the CPW board is accomplished by using a small 42 resistor in place of the quarter wave bias decoupling lines used in the microstrip line approach. A 22 kω resistor can be used to bias the from a 5 V power supply. With the nominal.16 ma of device current required by the, the bias voltage at the device will be a nominal 1.5 V. Finding the lowest parasitic and lowest loss resistor may require some empirical bench testing where various component losses are measured by shunting each component across the 5 Ω CPW line and measuring its effect on the loss of the CPW transmission line. The resistor can be bypassed with a small 1 pf capacitor in parallel with a 1 pf capacitor. Figure 1. CPW approach for demonstration board In a similar fashion, a single resistor can be used on the output to extract the detected voltage, Vdet from the output port. A smaller 1 kω value resistor may be more appropriate as any additional capacitive bypassing after the 1 kω resistor will further decrease the video bandwidth of the detector. Video Bandwidth The -3 db video bandwidth of the by itself is approximately 3 MHz and is based on the expression: f u (3 db) =.25 / t w to.35 / t w t w = the pulse width The by itself will pass pulses as narrow as 1 ns. Since the detected voltage at the output port is resident at the same terminal as the RF output, anything attached to either the Vdet port or the RF output port of the demonstration board will restrict video bandwidth. The easiest solution on the Vdet port is to not use any bypass capacitance at C4 and keep R2 as low a value as possible. Using a scope probe with any appreciable capacitance will also adversely effect video bandwidth and pulse rise time. If possible use a high impedance low capacitance operational amplifier as a load for the Vdet port. In a normal application of the, the RF output is an antenna which presents a DC open circuit to the device. When testing the in a demonstration board, the normal load that a piece of test equipment would present to the device would be a nominal resistive 5 Ω load. In the case of the demonstration board, the external 5 Ω RF port termination is AC coupled with a 3.9 pf blocking capacitor, shown as C2. The series load of 3.9 pf and 5 Ω is in shunt with the Vdet voltage and will severely limit the ability of the to demodulate narrow pulses. The demonstration board was designed to evaluate the loss performance of the and to provide a DC voltage proportional to a continuous wave signal present at the RF input. In order to evaluate the pulse handling capability of the similar to its end use, a suggestion would be to use two coaxial to waveguide transitions back to back in series with the RF output 5 Ω termination. The back-to-back transitions will provide a low loss, high pass filter which will minimize the effect of the 5 Ω termination on pulse handling capability. Another option is to use a simple quarter wave capacitive coupled filter at the RF output of the demonstration board. Minimize the cable length between the RF output of the demonstration board and the load because a 5 Ω coaxial line will add a load of approximately 3 pf/ft. 4
In systems where the is followed by something other than an antenna or waveguide probe which is normally a DC open, it may be beneficial to use quarter wavelength parallel coupled microstrip lines to AC couple to the following stage. The quarter wave parallel coupled lines will provide a low loss DC block at the design center frequency with less series capacitance than a typical capacitor. Depending on what follows the DC block, its effect of loading the Vdet port may be less than if a capacitor was used. Coupler Directivity The directivity of a coupler describes its ability to differentiate between the power sent in one direction down a transmission line versus power sent in the opposite direction. The couplers used in laboratory test equipment are usually in the vicinity of 4 db, which are considered very good. The requirements on couplers used to measure forward and reverse power as a check on system operability are normally not as stringent. The has a typical directivity of 13 db at 2 GHz, decreasing to 1 db at 6 GHz. Directivity is measured by inserting the between a well matched 5 Ω signal source and a well match 5 Ω termination. Incident power is set for a convenient Vdet level. As an example, it could be set for 2 mv. The is then reversed and the incident power increased until the same 2 mv is achieved. The difference in the incident power levels is the directivity of the at that particular frequency. Coupler directivity can be correlated to an error coefficient that can affect the magnitude of the power detected by the coupler. Since we are only making scalar measurements without any phase information, we can only calculate a plus and minus window that our measured coupled power could be found. This can happen with two loads with the same return loss but with different phase angles, which can cause two different levels of power being coupled to the detector. The greater the reflection from the load, the greater the error could be. The potential error ρ relates to coupler directivity by the following equation: ρ = A + A ρ L 2 The reflection coefficient of the output load is ρ L and A = log 1-1 (directivity (db)/-2). The following equation relates ρ to mismatch loss by: Mismatch loss (db) = -1 log 1 (1-ρ 2 ) Mismatch in db suggests a plus and minus window over which the detected power could vary based on the reflection coefficient of the load attached to the coupler. Table 1 shows a few scenarios describing the mismatch loss versus several different return loss loads and 1 db and 13 db coupler directivity. Table 1. Uncertainty vs. directivity of the Directivity (db) RL (db) ρl ρ ML ± (db) 1-18.126.321 ±.47-12.251.336 ±.52-6.51.395 ±.74 13-18.126.227 ±.23-12.251.237 ±.25-6.51.279 ±.35 The data shows that for greater than a 12 db return loss load, the maximum uncertainty in measured power for a 13 db directivity coupler is plus or minus.25 db. The uncertainty increases to plus or minus.52 db for a 1 db directivity coupler. For narrow band applications the uncertainty window can be reduced by providing a better match at the load. Summary The provides an integrated directional coupler and temperature compensated detector that provides a compact approach for monitoring amplifier power output. Its useful frequency range is from 2 to 6 GHz. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 25-211 Avago Technologies. All rights reserved. AV2-347EN - August 23, 211