Journal of Research in Engineering and Applied Sciences CAPACITOR VOLTAGE BALANCING IN SINGLE PHASE SEVEN-LEVEL PWM INVERTER Midhun G, 2Aleena T Mathew Assistant Professor, Department of EEE, PG Student (Power Control & Drives) Department of EEE {midhun.g@mbcet.ac.in, anu.midhun99@gmail.com, 2 aleenatmathew9@gmail.com} 2 Abstract Multilevel inverter has emerged recently as a very important altrernative in the area of high voltage and high power applications. A multilevel inverter can synthesize stepped output voltages similar to sinisoidal wave. The main limitations of conventional topologies are high THD, large number of components, complex PWM control and voltage balancing problems. So to overcome these limitations, a single-phase seven-level PWM inverter with less number of carrier signals and components is introduced. It consist of a single dc voltage source with a series of capacitors, diodes, switches and an H-bridge cell. Simulation of proposed single-phase seven-level PWM inverter is done in MATLAB simulink software and voltage balancing issue in series connected capacitors is eliminated using modified PWM scheme. Key Words : Multilevel inverter, THD ( Total Harmonic Distortion).. Introduction modulation ability without the need of any transformer. Despite its complexities, multilevel inverter is preferred due to its superior harmonics profile and its ability to produce a high voltage without any transformer [5]. The concept of multilevel inverter was introduced in 975. The term multilevel began with three level inverter. A multilevel inverter is a power electronic system that can synthesize stepped output voltages similar to sinusoidal wave. Using multilevel technique, the amplitude of the voltage is increased, stress in the switching devices is reduced and overall harmonics profile is improved. As the number of levels increases, the obtained output waveform approaches the sinusoidal wave with less distortion, less switching frequency, higher efficiency etc. Plenty of multilevel inverter topologies have been investigated, but only several of them are practical for industrial applications. Among existing multilevel inverters, diodeclamped and cascaded H-bridge (CHB) multilevel inverters are most widely used. It exhibits several attractive features such as simple circuit layout, less component counts, modular in structure and avoid unbalance capacitor voltage problem. However as the number of output level increases, the circuit becomes bulky due to the increase in the number of power device [-3]. The demand for renewable energy has increased significantly over the years because of shortage of fossil fuels and greenhouse effect. Among various types of renewable energy sources, solar energy and wind energy have become very popular and demanding due to advancement in power electronics techniques. Using multilevel inverters renewable energy sources can be easily interfaced to the grid. Improving the output waveform of the inverter reduces its respective harmonic content [6-8]. When the output voltage levels increases, the number of power semiconductor switches, sources and the number of the gate driver circuit required increases which would make the overall system more expensive and complex. So to overcome these limitations, a single phase seven-level PWM inverter is introduced in the proposed work. And also a new concept is put forward to reduce voltage unbalancing in series connected capacitors [-]. When dc voltages are scaled in power of three, it can maximize the number of output voltage levels. However, it increases independent dc voltage sources to generate higher output voltage levels. To solve this problem, a multilevel inverter employing a cascaded transformer is used. However, the cascaded transformer makes the system bulky because it operates in a low frequency [4]. To eliminate this drawback transformer less circuit topologies were modified from the CHB multilevel inverter. Multilevel inverters have found potential application in high power systems due to there over 2. Single Phase Seven-level PWM Inverter Most of the conventional multilevel topologies uses series connected capacitors and independent DC sources. Series connected capacitors makes voltage unbalancing problems and it will affect the performance of multilevel inverter. The proposed multilevel inverter is a useful way to minimize the number of independent DC voltage sources and also it is an effective configuration of a multilevel inverter that can increase the number of output 83 JREAS, Vol. 2, Issue 2, April 27
voltage levels with a reduced number of switches. Fig. shows the block diagram of the proposed seven-level PWM inverter. It consists of a single dc voltage source, level and polarity generation part and load. The level generation part is helps to generate the required levels. The other part is called polarity generation part and is responsible for generating the polarity of the output voltage. respectively. These command signals produces the gating signal for each switches. The switching modes for the seven-level PWM inverter are shown in Table.. There are seven switching patterns to control the inverter. The sequence of switches (-3), (4-7), (4-5) and (-4) are used for levels up to Vdc and (-4), (3-7), (3-6) and (2-3) are used for levels up to Vdc. Here Vdc is the input voltage. The output voltage will be the sum of voltage sources which are included in the current path. Fig. : Block Diagram of Seven-Level PWM Inverter A detailed circuit diagram of the proposed seven-level PWM inverter is shown in Fig.2. It includes single dc voltage source, which is separated by three capacitors connected in series. Each capacitor voltage is considered to Vdc/3. Then output voltage wave having seven levels, i.e., Vdc, 2Vdc/3, Vdc/3,, - Vdc, - 2Vdc/3, -Vdc. Vdc (or - Vdc) is determined by the switches S~ S4. Other voltage levels are produced by S5, S6 and S7. Fig. 3 : Switching scheme for proposed topology Table Output Voltage Levels With Switching States SWITCHING STATES 3. Fig. 2 : Circuit Diagram of Seven-level PWM Inverter OUTPUT VOLTAGE E S S2 S3 S4 S5 S6 S7-2Vdc /3 -Vdc /3 Vdc /3 2Vdc /3 Vdc -Vdc Capacitors Voltage Unbalance The seven-level PWM inverter consists of three capacitors, i.e., C, C2 and C3 respectively. These capacitors have the major role in generating the exact output levels. If there is any voltage unbalance in series connected capacitor, that causes variation in output levels. Therefore, the voltage balancing of seriesconnected capacitors is very important factor for the working of the inverter. From Fig.4 IC(avg), IC2(avg) and IC3(avg) are current through the capacitors C, C2 and C3 respectively. Switching scheme for controlling the seven-level inverter is shown in Fig.3. Phase Disposition (PD-PWM) is adopted to control the inverter. The Vcar, Vcar2 and Vcar3 are the three carrier waves and Vref is the reference wave used for modulation. The reference and carrier waves have the same frequency but different offset voltages. By comparing the reference and each carrier wave, it produces the command signals, i.e., Ca, Cb and Cc 84 JREAS, Vol. 2, Issue 2, April 27
wave (Vcar2), which is compared with the reference (Vref). Fig. 5 : Variation of Cb according to the amplitude of Vcar2 Fig.4 : Equivalent Circuit with average currents 5. Simulation of proposed seven-level PWM inverter are done in MATLAB as shown in Fig.6. Phase Disposition (PD-PWM) is used here. There are three carrier signals are given by three repeating sequence block and these are compared with a reference sine wave. Then produces three command signals and is given to the switching subsystem and corresponding switching signals are produced. Then, it given to each switches. Output is viewed from the scope block. A voltage of 5V DC is applied to get an output voltage of 5V with resistance and inductance as load (R=ohm, L=25mH) as shown in Fig.7. The output voltage levels have seven steps maximum upto 5V. Due to the voltage unbalancing of series connected capacitors, causes the variation in output voltage level. Waveform of unbalanced capacitor voltages are shown in Fig.8. Ideally the three capacitors voltage will be divided equally as 5V but from simulation result there will be variations in each capacitor voltage. IC(avg)< IC2(avg)< IC3(avg) for <a <a2 < a3 where a, a2, a3 are load angles respectively. It means that more charges flow from lower capacitor C3 than upper capacitors C and C2. This is the main reason for the voltage unbalancing in the series-connected capacitors of the proposed circuit topology. Hence, each capacitor voltage should be regulated to feed the appropriate amount of average current by satisfying the below condition IC(avg)= IC2(avg)= IC3(avg) The capacitor voltage unbalancing occurs depending on just the switching angles of a, a2 and a3 regardless of the load conditions. In other words, the difference between the charging and discharging of the series connected capacitors is determined by the switching angles. It means that the different periods for each voltage level are the cause of the capacitor voltage unbalancing problem. 4. Simulation Modified Switching Scheme To solve the capacitor voltage unbalancing, a modified switching pattern is adopted for the proposed seven-level PWM inverter. The main idea of the proposed control strategy is to regulate the charging and discharging current rate of capacitor? C2. It ensures the voltage regulation of C2 and the voltage balance of the upper and lower capacitors. Because capacitor C2 locates between C and C3 and the charging and discharging current of C and C3 should flow through C2. Thus, the voltage regulation of C2 is directly related to the voltage regulation across C and C3. In order to regulate the charging and discharging current rate of C2, it is possible by controlling the amplitude of the second carrier (Vcar2). Fig.5 shows the modified control method for regulating the C2 voltage. It controls the amplitude of the carrier Fig. 6 : Simulink model of proposed seven-level PWM inverter 85 JREAS, Vol. 2, Issue 2, April27
Fig. 7 : Seven-level PWM output voltage with RL load (Vin=5V; x axis=.sec/div; y axis= 5V/div) Fig. 9 : Simulink model of seven-level inverter for RL load with capacitor voltage balancing Fig. : Output voltage of seven-level inverter with balanced capacitor voltage (x axis: Time.s/div; y axis: Voltage 5V/div) Fig. 8 : Waveform of unbalanced capacitor voltage (x axis: Time.s/div; y axis: Voltage V/div) The charging and discharging time of capacitor C2 regulates voltage balancing of other two capacitors. This idea is adopted in the modified switching scheme. The simulink model of a single phase seven level inverter with modified switching scheme for RL-load is shown in Fig.9. 5V is applied as the input DC-voltage. The triggering pulses are generated by using the Phase Disposition pulse width modulation (PD-PWM) technique. The modified switching arrangement is done by taking voltage across the capacitor C2 from the output and it is given as input through a PI controller. This feedback of voltage helps to vary the amplitude of second carrier in between other two carriers. Then the second carrier will control the charging and discharging of C2 and eliminate the voltage unbalancing problem. Then the three carrier signals are given by three repeating sequence block and these are compared with a reference sine wave. The three command signals is then given to the switching subsystem and corresponding switching signals are produced. Then, given to each switches and Output is viewed from the scope block. Fig. : Waveform of balanced capacitor voltage (x axis: Time.s/div; y axis: Voltage V/div) The balanced output voltage of seven-level PWM inverter with modified switching scheme is shown in Fig.. with load (R=ohm, L=25mH). Waveform of balanced capacitor voltage is shown in Fig.. Voltages of all three capacitor are balanced at 5V. It is clear from the simulation result the voltage unbalancing in series connected capacitors is rectified. So that the proposed PWM scheme will be an effective remedy for voltage balancing issues in seven-level PWM inverter. 86 JREAS, Vol. 2, Issue 2, April 27
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