DESIGN AND ANALYSIS OF NAND GATE USING BODY BIASING TECHNIQUE

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DESIGN AND ANALYSIS OF NAND GATE USING BODY BIASING TECHNIQUE Mr.Om Prakash 1, Dr.B.S.Rai 2, Dr.Arun Kumar 3 1 Assistant Professor, Deptt.Electronics & Comm. IIMT IETMeerut, U.P. (India). 2 HOD & Professor Deptt.Electronics & Comm. M.M.M.Engg.College, Gorakhpur, U.P. (India). 3 Professors and Dean of Students Deptt.Electronics & Comm. IFTM University Moradabad, U.P. (India) ABSTRACT Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage over static CMOS logic circuits. Dynamic CMOS Circuits, featuring a high speed operation are used in high performance VLSI designs. The main drawbacks of dynamic logic are a lack of design automation, a decreased tolerance to noise and increased power Consumption. In this work, domino gate is designed with various body biasing and high performance circuit was specified. Keywords: CMOS, Conventional Body Bias, Domino Logic, Dynamic Power, Substrate Biasing. I INTRODUCTION VLSI designers have different options to reduce the power dissipation in the various design stages. It is important to introduce low-power design techniques and to reduce the package size during the circuit normal mode of operation. More power consumption also reduces the battery life of the devices. Therefore reducing power dissipation during operation has become a critical objective in today s VLSI circuit designs. So special cooling equipment is necessary to remove excessive heat produced during circuit operation. Power consumption in CMOS circuits can be dynamic or static. Dynamic power dissipation takes place due to switching activities because of short circuits current and charging and discharging of load capacitances. Static power consumption is another type of power dissipation in CMOS circuits. Leakage currents with sub-threshold source-to-drain leakage, reverse bias junction band-to-band tunneling, gate oxide tunneling, and other current drawn continuously from the power supply cause static power dissipation [7]. To reduce dynamic power dissipation it is necessary to reduce the supply voltage of the circuit, reduction of supply voltage after a certain limit affects the performance of the circuit, to maintain circuit performance of the circuit it is necessary to decrease the threshold voltage as well, but it leads to leakage power dissipation. Leakage power can be reduced by increasing the threshold voltage [5] IN this paper to reduce the voltage applying to the load CIRCUIT; we suggest the use of AVL (Adaptive Voltage Level) circuit technique. II AVL TECHNIQUE AVL circuit contained one p-mosfet and two series connected n-mosfets, which will reduce the voltage applying to the load circuit. AVL circuit is controlled by sleep (slp) control signal [1]. When sleep signal is low, the p-mosfet is on, while

series connected n-mosfets are off. During this operation, we get the full voltage out of the AVL circuit. When sleep signal make transition from low to high, this will turn-on series connected n-mosfets, and turn-off p-mosfet, Thus, the drain-tosource voltage (Vdsn), of the off n-mos in load circuit (domino NAND gate) can be expressed as Vdsn =VDD 2v Where v is a voltage drop of the series connected single n-mosfet and Vdsn can be changed by changing the number of series connected n-mosfets. If Vdsn decreases this will increase the barrier height of the off n-mos [6], therefore it will decrease the drain induced- barrier-lowering (DIBL) effect and, consequently, increase Vthn. This result in a decrease in the sub threshold current of the n-mos, therefore the leakage current through the gate decreases. AVL circuit is controlled by sleep control signal. The advantage of using AVL circuit is that the load circuits can operate quickly when they are in active mode due to the increase in drain-source current as the AVL circuit supplies the maximum drain-source voltage Vds to the on-mosfets through on-switches. On the other hand, during standby mode, it supplies a slightly lower voltage through the weakly-on switches [2]. Hence the sub-threshold leakage current of the off-mos transistors decrease and the standby power gets reduced. It also produces high noise immunity. When we applied voltage to the substrate of a MOSFET it affects the threshold voltage of a MOSFET as well. The voltage difference between the source and the substrate, VBS also affects the width of the depletion layer and due to changes in the charge in depletion layer voltage across the oxide also get changed. Therefore the expression for the threshold voltage is given by: The threshold difference due to an applied source-substrate voltage can therefore be expressed by: Where is the body effect parameter given by? Substrate biasing provides an effective circuit-level technique for varying threshold voltage and to enhance the performance of the circuit. This paper gives emphasis on low power design as well as improved noise margin for domino NAND gate technique. Among different dynamic logic circuit techniques, domino logic technique is mostly used because it provides less delay and its area consideration, but it has less tolerance to noise and its static power consumption is high. So in this paper we have applied AVL circuit technique and body bias technique to overcome both of these problems

III STANDARD DOMINO NAND GATE A standard domino NAND gate is as shown in Figure 1. A standard Domino NAND gate consists of one p-type transistor and an n-type dynamic logic block. During pre-charge phase the output node of the dynamic CMOS stage is pre-charged to high logic level [4]. During evaluation phase, the output node of the dynamic CMOS stage is either discharged to a low level or it remains high, means that, the output node may be selectively discharged through the n-type logic block depending upon whether there is a path exist to the GND or not. It depends upon the inputs of the NMOS logic block. If a path to ground is not formed during the evaluation phase, means there is no conducting path exist to the ground, we get the high logic level at the output. If inputs to the n-type logic blocks are such that it makes a conducting path to the ground, output will be low. IV BODY BIAS NAND GATE Figure 1.Domino NAND Gate Domino logic gates are frequently employed in high performance circuits for high speed and area efficiency. As supply voltage is reduced, delay increases, unless threshold voltage Vth is also decreased. Substrate biasing provides an effective circuit-level technique for varying threshold voltage. Here substrate of NMOS is connected to the clock and PMOS is connected to Vdd, which increases the threshold voltage that in turn reduces the leakage current Figure 2 Body Bias NAND Gate

4.1 Parameters Observation Observation parameters of domino AND Gate and Body Bias NAND Gate Technique Dynamic power dissipation In mili wtts Leakage Power in pico watts Evaluation Delay in Pico sec Noise margin in volts (NMH) Noise margin In volts (NML) Domino NAND gate 0.087 140.73 25.99 1 0.5 Body Bias NAND gate 0.081 176.95 25.81 1.2 0.85 200 180 160 140 120 Dynamic power dissipation In mili wtts Leakage Power in pico watts 100 80 Evaluation Delay in Pico sec 60 40 20 Noise margin in volts (NMH) 0 Domino NAND gate Body Bias NAND gate Figure 3.Comparison of power consumption, delay and noise margin V SIMULATION RESULTS Figure 4.Output of Domino NAND GATE

Figure 5.Output of Body bias NAND GATE VI CONCLUSION In this paper we have designed Domino NAND gate and body bias NAND gate Simulation results shows that our proposed circuit technique consumes less dynamic as well as static power than other techniques. The other benefit of proposed technique is its high noise immunity as compare to other technique. In this paper we can say that our proposed NAND gate consumes less power and gives high noise margin. REFERENCES [1]. H. Mangalam and K. Gunavathi, Domino Logic Circuit with Reduced Leakage and Improved Noise Margin, International Journal of Applied Engineering Research ISSN 0973-4562 Volume 2, Number 4 (2007), pp. 585 593. [2]. Suman Nehra, K.G.Sharma, Tripti Sharma and Prof.B.P.Singh, High Performance VLSI Design Using Body Biasing in Domino Logic Circuits -International Journal of Technology And Engineering System(IJTES):Jan March 2011- Vol.2.No.2. [3]. Sreenivasa Rao.Ijjada, Ayyanna.G, G.Sekhar Reddy, Dr.V.Malleswara Performance of different cmos logic styles for low power and high speed, International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.2, June 2011. [4]. Kang, S. and Y. Leblebici. CMOS Digital Integrated Circuits: Analysis and Design. The McGraw-Hill Companies, Inc.: New York. 1996, pp 383-384. [5]. Gholamreza Karimi1, Adel Alimoradi2 Multi-Purpose Technique to Decrease Leakage Power in VLSI Circuits Canadian Journal on Electrical and Electronics Engineering Vol. 2, No. 3, March 2011. [6]. Tadayoshi Enomoto, Yoshinori Oka, Hiroaki Shikano, and Tomochika Harada Chuo University, Faculty of Science and Engineering, Tokyo, Japan enomoto@ise.chuo-u.ac.jp A Self-Controllable-Voltage-Level (SVL) Circuit for Low-Power, High-Speed CMOS Circuits, ESSCIRC 2002,pp 412-414.

[7]. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, and Zainalabedin Navabi, Electrical and Computer Engineering Department Faculty of Tehran, Iran Simultaneous Reduction of Dynamic and Static Power in Scan Structures. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE 05)- 2005. [8]. Pushpa Raikwal, V. Neema &S. Katiyal Low power with improved noise margin for domino CMOS NAND gate International Journal Of Computational Engineering Research / ISSN: 2250 3005.

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