A Lossless Clamp Circuit for Tapped-Inductor Buck Converters*

A Lossless Clamp Circuit for Tapped-Inductor Buck nverters* Kaiwei Yao, Jia Wei and Fred C. Lee Center for Power Electronics Systems The Bradley Department of Electrical and mputer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 4061 USA Abstract Tapped-inductor buck converters allow great improvements in the performance of 1V-input voltage regulator modules (VRMs). However, the converters inductor leakage energy problem limits their applications. This paper proposes a simple clamp circuit, which can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Simulation and experimental results prove the significant improvement afforded by the proposed clamp circuit. I. INTRODUCTION Semiconductor integration technology is developing so fast that present microprocessors can run at clock frequency greater than 1GHz. Moore s Law predicts that this trend will continue in the next decade. However, this development depends on a clean low-voltage, high-current power supply. Because of this requirement, a special DC-DC power supply, the voltage regulator module (VRM), is needed for good voltage regulation. Since the required power continues to increase, 1V proves to be a better level than 5V for the VRM s input voltage [1]. The conduction loss in the input bus can be significantly reduced since the input current is much smaller. Also, the input filter capacitance can be reduced because the same capacitance can store much more energy at higher voltage levels. All of these factors mean that a 1V-input VRM can achieve high efficiency, small size and low cost. If there is no requirement for isolation, the buck converter is the simplest circuit for realizing step-down DC-DC conversion. As a result, this topology is widely used for both 5V- and 1V-input VRMs. In order to handle large output current and achieve the current ripple cancellation effect, multi-phase interleaving technology is used. Fig. 1 shows this state-of-the-art topology for VRM applications. 5V 1V Q1 1 Q1 m Q 1 Q m L 1 L m Fig. 1. Multi-phase interleaving buck converter. Processor Load * This work was supported primarily by the VRM consortium. Also, this work made use of ERC shared facilities supported by the National Science Foundation under Award Number EEC-9731677. However, since the output voltage is low (from 1.1V to 1.85V for the VRM 9.0 standard), the step-down ratio is very large for 1V input voltage. The duty cycle is D=/, (1) which is so small that the turn-on period of the top switch will be extremely short, especially when the switching frequency is high. As a result, gate driving for the top switches would be problematic. Another problem for the 1V-input buck converter is the asymmetric transient response that occurs because of the great difference between the rising and falling speeds of the inductor current []. During the turn-on period of the top switch, the inductor current rising speed is: di/dt rise =(-)/L. () The inductor current falling speed during the freewheeling period is: di/dt fall =/L. (3) Since the inductor current falling speed is the slowest, it will limit the transient response of the VRM. Finally, the most serious problem for the 1V-input buck converter is its low efficiency, especially for high-frequency applications. Since the top switch turn-off current equals the output peak current, the turn-off loss is significant. Also, the bottom switch body diode reverse-recovery problem is a major contributor to the poor efficiency at high frequency. As a result, some other topologies are proposed in order to improve the performance of the 1V-input VRM [-5]. Of these, the tapped-inductor (TI) buck converter is very attractive for its simple structure. It involves only a slight modification of the original buck converter. Section II describes both the advantages and disadvantages of this converter s use in VRM applications. Section III introduces a lossless clamp circuit with the modified TI buck converter in order to solve the existing problems. The design of multiphase interleaving TI buck VRM is discussed in Section IV, and the simulation and experimental results in Section V verify the significant performance improvement. II. TAPPED-INDUCTOR BUCK CONVERTER Fig. shows a TI buck converter, in which a tapped inductor takes place the output filter inductor in the conventional buck converter. This allows different inductances between the charging and discharging periods. Inductance of winding w1 and w is effective during the charging period, while inductance of only winding w1 is effective during the discharging period. In another word, the

TI buck converter adds a second coupled winding w in the conventional buck converter. The turns ratio is defined as: n=(w1+w)/w1. (4) This modification introduces an extra degree of freedom, in that the tapped inductor turns ratio n may be selected for the most benefit to the VRM applications. For the TI buck converter in Fig. 1, n should always be greater than one. 1V Q1 w Q n:1 w1 Fig.. A TI-Buck converter..1. The advantages of the TI buck converter From the voltage-second balance on the inductor, the switching duty cycle of the TI buck converter can be derived. n D =. (5) + ( n 1) If n=1, (5) shows the same result as (1), which is the duty cycle of the conventional buck converter. When n>1, the duty cycle increases with the increase of n. Fig. 3 shows the trend clearly with 1.5V output voltage. For example, the duty cycle is almost doubled when n=. As a result, the TI buck converter can extend the duty cycle with the same input and output voltage. The problem in the conventional buck converter about the small duty cycle can be solved. Duty Cycle 0.6 0.5 0.4 0.3 0. Buck nverter 0.1 (=1V, =1.5V) 0 1 3 4 5 6 7 8 (n) Turns Ratio Fig. 3. D-n relationship in the TI buck converter. Since the charging and discharging inductances are different in the TI buck converter, it is possible to achieve the same inductor current rising and falling speeds by choosing a suitable turns ratio. When the top switch is turned on, the inductor current rising speed is: di/dt rise =(-)/(n L w1 ). (6) When the top switch is turned off, the inductor current falling speed is: di/dt fall =/L w1. (7) In both (6) and (7), L w1 represents the inductance of winding w1. Fig. 4 shows the inductor current rising and falling speeds (the current slew rate) as related to the turns ratio with 1.5V output voltage and normalized inductance over winding w1. When n is about.5, the inductor current rising and falling speeds are the same, which means symmetric transient response can be achieved. The most significant improvement of the TI buck converter is that it can have less switching losses. First, the switching current of the top switch is much smaller compared with that in the conventional buck converter. If the inductance is large and the current ripple is relatively small (and can therefore be ignored), the top switch switching current is: Io i off =. (8) n ( n 1) D The increased turns ratio allows the switching current to be greatly reduced. For example, the switching current can be reduced by about half when n=. Current Slew Rate (A/s) 1 10 8 6 4 Curre nt Rising Speed (=1V, =1.5V) Curre nt Falling Speed 0 1 3 4 5 6 7 8 (n) Turns Ratio Fig. 4. Relationship between inductor current slew rate and turns ratio. Another way the loss can be reduced is that the bottom switch body diode reverse-recovery problem is greatly relieved by the leakage inductance of the tapped inductor. When the top switch is turned on, the di/dt of the diode reverse-recovery current is limited by the leakage inductance. However, in the conventional buck converter, the only limitation for this di/dt is the very small parasitic inductance. Smaller di/dt means smaller reverse-recovery peak current and less reverse-recovery loss... The existing problems in the TI buck converter Although the TI buck converter has many benefits, including extended duty cycle, symmetric transient response and less switching loss, there are two problems limiting its wide applications in practice. First, there is the gate-driving problem. Fig. raises the question of how to drive the top switch. A transformerisolated gate driver will degrade the simplicity of the original power converter besides the fact that this driving method is not good in very high-frequency applications. The simple bootstrap gate driver can still be used. However, the source voltage of the top switch becomes negative when the top switch is turned off. The driving voltage level for the top switch will be: Vg top =Vcc+(n-1), (9) where Vcc is the control voltage level, which is normally equal to. If the n is too large, the driving voltage may be too high for the applications. The most serious problem for the TI buck converter is the leakage energy. It is impossible for the tapped inductor to achieve a perfect coupling effect so that leakage inductor exists in the circuit. When the top switch is turned off, the

current in the leakage inductor of winding w cannot be reflected to winding w1, so it continuously goes through the drain-to-source capacitor of the top switch. All of the energy stored in the leakage inductor will be transferred to this small capacitance, causing a huge voltage spike across the top switch. This voltage spike not only increases the switching loss, but also can destroy the top switch. Some methods have been proposed to solve these problems, especially the leakage energy problem [3,6]. Although all the proposed methods feature the lossless characteristic (which is better than the conventional RLC clamp circuit), they employ a coupled third winding, which increases the circuit complexity. A simple clamp circuit, which solves all the problems in the TI buck converter, is proposed in the next section. III. A NOVEL LOSSLESS CLAMP CIRCUIT The gate-driving problem is easy to solve by simply rearranging the connections of the tapped inductor and power devices. Fig. 5 shows this circuitry change. The tapped inductor looks more like two coupled inductors. With this change, the source of the top switch is connected with the drain of the bottom switch, so that the bootstrap gate driver can be used without any limitation from the turns ratio. n:1 1V w Q1 Bootstrap Gate Driver Q w1 Fig. 5. Modified structure of the TI buck converter. Based on this modified circuit structure, a simple lossless clamp circuit with two diodes and a capacitor is proposed, as shown in Fig. 6. Fig. 7 shows the key operation waveforms. The operation principle is as follows. Ds1 w Cs - + i Cs Ds Clamp Circuit Q1 Bootstrap Gate Driver Q w1 i L Fig. 6. Lossless clamp circuit for the TI buck converter. During top switch Q1 s turn-on period, the steady-state voltage across the clamp capacitor Cs is: V Cs0 =(-)/n+. (10) Here, the diode forward voltage drop is ignored. When top switch Q1 is turned off, the current in the leakage inductor will go through Cs and Ds1 so that the leakage inductor energy will be stored in clamp capacitor Cs. If Cs is large enough, the increased voltage across Cs is relatively small and the value is about: V Cs = Lleak ioff Cs VCs0. (11) As a result, the turn-off voltage stress across top switch Q1 is effectively clamped as: Vds peak =+V Cs0 + V Cs. (1) When turns ratio n is greater than, this voltage stress across the top switch is less than 3V, so the 30V power MOSFETs can still be used. Vg Q1 i Cs V Cs V Cs0 0V V Cs Vds peak Fig. 7. Key operation waveforms for the lossless clamp circuit. When top switch Q1 is turned on, the extra energy stored in the clamp capacitor will be discharged to the output through Ds and winding w1. The voltage across Cs will go back to V Cs0, the steady-state value. Therefore, all the leakage energy is totally recovered to the output. The voltage stress across the bottom switch Q is: Vds peak = V Cs0 + V Cs. (13) This value is less than. Low-voltage power MOSFETs (less than 30V) with much smaller Rds on can be used to reduce conduction losses. The currents through Ds1 and Ds are very narrow pulse currents related to the leakage energy, so Ds1 and Ds can be small. If the tapped inductor is designed to have small leakage inductance, a 1 to microfarad capacitance is large enough for the clamping function. The Cs package can be extremely small. Briefly put, this clamp circuit features simple structure, small size and low cost. However, there is a limitation for the application of this lossless clamp circuit with some turns ratio design. For an ideal TI buck converter without leakage inductance and clamp circuit, when top switch Q1 is turned off, the voltage across winding w is: V L_w =(n-1). (14) This voltage must be smaller than the V Cs0 in (10) to maintain correct operation. Otherwise, instead of the intended small pulse current, a large current will continue charging and discharging Cs. From (10) and (14), the limitation for this clamp circuit application is: n +1. (15) For 1V-input VRM applications, the -to- ratio is normally larger than 6, and n should be less than 3 for symmetric transient response. So the limitation is not a problem for this circuit s use in VRM design. Fig. 8 shows the simulation results for this clamp circuit using a uf clamp capacitor. The tapped inductor is designed

with n=, 300nH for the inductance of winding w1, and 0.95 coupling coefficient. The output is 1.5V with 1.5A DC current. The switching frequency is 300KHz. The simulation results prove the operation of this clamp circuit. All the results are in agreement with the previous analysis. The small errors are due to the diode forward conduction drop in the simulation circuit. Vg Q1 i Cs V Cs V w because this is the simplest structure for a tapped inductor. Another reason for the small turn ratio is the moving zero in the right half plane (RHP) [8,9]. This RHP zero reduces the system feedback loop phase margin and can impact the transient response. Ro [ n + D (1 n)] Z RHP = (16) Le ( n 1) D n Lw 1 (17) Le = [ D + n (1 D)] Here, Ro is the output load. The RHP zero moves with the output load; full load is the worst case. Fig. 9 shows the relationship between the RHP zero and the turns ratio at full load condition. A large turns ratio moves the RHP zero to the low frequency range. Also, larger L w1 means lower RHP zero frequency. Since a higher-frequency RHP zero has less influence on the system feedback, the turns ratio is designed to be :1 instead of 3:1. 1. 10 6 Vds Q 7V RHP Ze ro (Hz) 1. 10 5 1. 10 4 L w1 =300nH L w1 =600nH Fig. 8. Simulation results for the lossless clamp circuit. IV. VRM DESIGN WITH THE TI BUCK CONVERTER A 1V-input and 1.5V/50A-output VRM is designed incorporating the TI buck converter. A four-phase interleaving structure is used for the large output current and current ripple cancellation. For multi-phase current sharing, the lossless method is used [7]. The 30V power MOSFETs Si4884DY and Si4874DY are selected as the top and bottom switches respectively. Here, device selection is not optimal since 1V power MOSFETs with lower Rds on could be used as the bottom switch. Switching frequency is 300KHz for best device operation. The most important aspect is the tapped-inductor design, which is related to the efficiency, transient response and VRM size. Planar core structure is selected for the low profile, high power density design. The inductor winding can be realized with the PCB copper trace in order to both simplify assembly and reduce cost. Also, the solder point resistance can be eliminated, which is very helpful for large winding current. Fig. 4 shows that the best turns ratio for the tapped inductor is about.5 for a symmetric transient response. Since large currents go through winding w1 during the freewheeling period, w1 should be one-turn winding to reduce the conduction loss. As a result, one-turn or two-turn windings can be used for w in order to achieve almost symmetric transient response. One-turn design is selected for 1. 10 3 3 4 5 6 7 8 (n) Turns Ratio Fig. 9. The influence of turns ratio on RHP zero. The inductance of winding w1 is designed to be 300nH as a trade-off between the transient response and efficiency. A small inductance can increase the current slew rate (6 and 7) but will also increase the RMS current and switching current through the power MOSFETs. Fig. 9 shows that a smaller inductance can relieve the influence of the RHP zero. Magnetic integration technology [10] is adapted for twophase tapped inductors in order to shrink the inductor size. To achieve flux cancellation in the center leg of an EI core, the phase difference should be 180 degrees. Fig. 10 shows the integrated inductor structure with PCB as windings. Here, Phillips EI-18-3F3 core is selected. There is no air gap in the central leg, so these two inductors are totally decoupled. W1 for L1 Gap PC Board W for L1 re W1 for L W for L Fig. 10. The integrated magnetic structure. For the four-phase interleaving TI buck VRM, each phase has a clamp circuit. Schottky diodes with low current ratings are used for diodes Ds1 and Ds since they can reduce the conduction loss and overall size. A.uF 106 package ceramic capacitor is selected as clamp Cs. The clamp circuit is so small that it has little influence on the whole VRM size.

V. SIMULATION AND EXPERIMENTAL RESULTS A four-channel interleaving buck converter was also built for comparison with the four-channel TI buck converter. Both have the same power rating, power devices and components except for the inductor design. Since the discharging period is the worst case of transient response for both the buck and the TI buck converters, it can be derived from (3 and 7) that the same discharging inductance can achieve the same transient response []. Also, the same crossover frequencies for the feedback loops are required. Fig. 11 shows the simulation comparison of switching currents between the buck and TI buck converters. The total conduction losses of the top and bottom switches are almost the same since the RMS current of the top switch is slightly reduced but the RMS current of the bottom switch is slightly increased. However, the turn-off current of the top switch in TI buck converter is reduced significantly, which can help to reduce the switching loss. It is obvious that the duty cycle is almost doubled in the TI buck converter. i S1 0.3A 10.51A Buck (i rms =4.88A) TI Buck (i rms =3.58A) 7V i Q1 Vg Q Vds Q (a) Vg Q1 Vg Q i Q1 Vds Q 19V i S Buck (i rms =1.3A) TI Buck (i rms =1.85) (b) Fig. 1. The TI buck converter: (a) without clamp and (b) with clamp. Fig. 11. The switching current comparison between buck and TI buck. Fig. 1 shows the experimental result comparison for the TI buck converter with and without the clamp circuit at fullload condition. Without the clamp circuit, there is a huge voltage spike across the top switch when it is turned off. The energy in the leakage inductor has no way to go except into the drain-to-source capacitor of the top switch. In the test at full-load condition, the voltage spike is so high that the top switch is destroyed. However, with the clamp circuit, this leakage energy can be stored in the clamp capacitor and recovered to the output. The voltage stress across the top switch is perfectly clamped below 0V. Fig. 13 shows the current-sharing tests in the four-phase input currents at both zero-load and full-load conditions. Since the PCB winding is used, the inductor parasitic resistance of these four inductors can be closely matched, which is the key factor in perfect current sharing [7]. During the test, the four phases input currents are almost the same for the whole load range. Fig. 14 shows the test efficiency comparison between the four-phase buck VRM and the four-phase TI buck VRM. The superiority of the TI buck converter with clamp circuit is significant. Curve only goes to 40A output because without the clamp circuit, the top device is destroyed at higher output current. Phase 3 Phase 4 Phase 3 Phase 1 (a) Phase 4 Phase 1 Phase Phase (b) Fig. 13. Current sharing in the four-channel TI buck VRM: (a) Io=0A and (b) Io=50A.

Efficiency (%) 90 85 80 75 70 65 60 1 3 1. TI Buck with Clamp. TI Buck w/o Clamp 3. Buck nverter 0 10 0 30 40 50 Load Current (A) Fig. 14. The efficiency comparison. Fig. 1 shows that the voltage stress of the bottom switch is only about 7V. As a result, 1V power MOSFETs can be used to further reduce the Rds on. For example, the 1V trench MOSFET Si4838DY (with the same package as the 30V Si4874DY) can reduce the Rds on from 7mΩ to 3mΩ and the gate driving voltage level drops from 10V to 4.5V. The whole VRM efficiency will be improved by about 3% with this new device. VI. CONCLUSION The TI buck converter is introduced in this paper, and a novel lossless clamp circuit is proposed to solve the converter s leakage energy problem. With the help of the simple clamp circuit, which features small size, low cost, perfect switch voltage stress clamping, and full energy recovery, the TI buck converter proves to be an excellent candidate for 1V-input VRM applications. ACKNOWLEDGEMENTS The authors would like to thank Siliconix for supplying free device samples. REFERENCES [1] William Hemena and Randhir Malik, A distributed power architecture for PC industry, HFPC 000, pp. 1-3. [] Jia Wei, Peng Xu, Ho-Pu Wu, Fred C. Lee, Kaiwei Yao and Mao Ye, mparison of three topology candidates for 1V VRM, IEEE APEC 001. [3] A non-isolated high input voltage VRM topology improved center tapped inductor technology, VRM Quarterly Review Report, Section, July 1998, VPEC, Virginia Tech, pp. 9-35. [4] Ron Lenk, Introduction to the tapped buck converter, HFPC 000 proceedings, pp.155-166. [5] Peng Xu, Jia Wei and Fred C. Lee, The active-clamp couple-buck converter-a novel high efficiency voltage regulator module, IEEE APEC 001. [6] R. Patrice Lethellier, Buck converter with inductive turn ratio optimization, US Patent Number 6094038, July 5, 000. [7] Xunwei Zhou, Xu Peng and F.C. Lee, A high power density, high efficiency and fast transient voltage regulator module with a novel current sensing and current sharing technique, APEC 99, l. 1, pp. 89-94. [8] M. Rico, J. Uceda, J. Sebastian and F. Aldana, Static and dynamics modeling of tapped-inductor DC-to-DC converters, IEEE PESC 87, pp. 81-88. [9] D. Edry, M. Hadar, O. Mor and S.A Ben-Yaakov, SPICE compatible model of tapped-inductor PWM converters, IEEE APEC 94, l., pp.101-107. [10] Wei Chen, F. C. Lee, Xunwei Zhou and Peng Xu, Integrated planar inductor scheme for multi-mode interleaved quasi-square-wave DC/DC converter, VPEC 1999, pp. 01-06.