High Common-Mode Voltage, Single-Supply Difference Amplifier FEATURES FUTIONAL BLOCK DIAGRAM High common-mode voltage range V to + V at a V supply voltage Operating temperature range: C to + C Supply voltage range: 3. V to V Low-pass filter (-pole or -pole) EXCELLENT AC AND DC PERFORMAE ± mv voltage offset ± ppm/ C typ gain drift db CMRR min dc to khz PLATFORMS Transmission control Diesel injection control Engine management Adaptive suspension control Vehicle dynamics control kω kω A 7 3 CLAMP DIODE A kω G = G = Figure. SOIC (R) Package Die Form INDUCTIVE LOAD kω kω 9- PUT GENERAL DESCRIPTION The is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. The input CMV range extends from V to + V at a typical supply voltage of V. BATTERY V -TERM SHUNT POWER DEVICE A The is offered in die and packaged form. Both package options are specified over a wide temperature range of C to + C, making the well-suited for use in many automotive platforms. COMMON Figure. High-Line Current Sensor 9- Automotive platforms demand precision components for better system control. The provides excellent ac and dc performance, which keeps errors to a minimum in the user s system. Typical offset and gain drift in the SOIC package are.3 µv/ C and ppm/ C, respectively. Typical offset and gain drift in the MSOP package are µv/ C and ppm/ C, respectively. The device also delivers a minimum CMRR of db from dc to khz. BATTERY V -TERM SHUNT POWER DEVICE A PUT The features an externally accessible kω resistor at the output of the preamp A, which can be used for low-pass filter applications and for establishing gains other than. CLAMP DIODE COMMON INDUCTIVE LOAD 9-3 Figure 3. Low-Line Current Sensor Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7.39.7 www.analog.com Fax: 7.3.73 Analog Devices, Inc. All rights reserved.
TABLE OF CONTENTS Specifications Single Supply... 3 Absolute Maximum Ratings... ESD Caution... Pin Configuration and Function Descriptions... Typical Performance Characteristics... 7 Theory of Operation... Applications... 3 Gain Trim... Low-Pass Filtering... High-Line Current Sensing with LPF and Gain Adjustment... Driving Charge Redistribution ADCs... Outline Dimensions... Ordering Guide... Current Sensing... 3 Gain Adjustment... 3 REVISION HISTORY / Rev. B to Rev. C Changes to Table... 3 Changes to Figure... Changes to Figure... 9 / Rev. A to Rev. B Changes to the General Description... Changes to Specifications... 3 Added Figure to Figure 33... Changes to Figure 3... Changes to Figure and Figure... Changes to Ordering Guide... / Rev. to Rev. A Changes to the Features... Changes to the General Description... Changes to Specifications (Table )... 3 Changes to Absolute Maximum Ratings (Table )... Changes to Pin Function Descriptions (Table 3)... Changes to Figure... Changes to Figure 9 and Figure... Updated Outline Dimensions... Changes to the Ordering Guide... 7/ Revision : Initial Version Rev. C Page of
SPECIFICATIONS SINGLE SUPPLY TA = operating temperature range, VS = V, unless otherwise noted. Table. SOIC MSOP Die Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit SYSTEM GAIN Initial V/V Error. V.3 +.3.3 +.3 %. V dc @ C vs. Temperature 3 ppm/ C VOLTAGE OFFSET Input Offset (RTI) VCM =. V; C + + + mv vs. Temperature C to + C +.3 + + + +.3 + µv/ C C to + C + + µv/ C INPUT Input Impedance Differential 3 39 3 39 3 39 kω Common-Mode 3 7 3 7 3 7 kω CMV Continuous + + + V Common-Mode Rejection VCM = V to + V f = dc db f = khz db f = khz db PREAMPLIFIER Gain V/V Gain Error.3 +.3.3 +.3.3 +.3 % Output Voltage Range...... V Output Resistance 97 3 97 3 97 3 kω PUT BUFFER Gain V/V Gain Error. V. V dc.3 +.3.3 +.3.3 +.3 % Output Voltage Range...... V Input Bias Current na Output Resistance Ω DYNAMIC RESPONSE System Bandwidth VIN =. V p-p; 3 3 3 khz V =. V p-p Slew Rate VIN =. V dc;... V/µs V = V step NOISE. Hz to Hz µv p-p Spectral Density, khz (RTI) 7 7 7 nv/ Hz POWER SUPPLY Operating Range 3. 3. 3. V Quiescent Current vs. VO =. V dc...... ma Temperature PSRR VS = 3. V to V 7 3 7 3 7 3 db TEMPERATURE RANGE For Specified Performance + + + C See notes on next page. Rev. C Page 3 of
Source imbalance < Ω. The preamplifier exceeds db CMRR at khz. However, because the signal is available only by way of a kω resistor, even the small amount of pin-topin capacitance between Pins, and 3, might couple an input common-mode signal larger than the greatly attenuated preamplifier output. The effect of pin-topin coupling can be neglected in all applications by using filter capacitors at Node 3. Rev. C Page of
ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage. V Transient Input Voltage ( ms) V Continuous Input Voltage (Common Mode) 3 V Reversed Supply Voltage Protection.3 V Operating Temperature Range Die C to + C SOIC C to + C MSOP C to + C Storage Temperature C to + C Output Short-Circuit Duration Indefinite Lead Temperature Range (Soldering, sec) 3 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C Page of
PIN CONFIGURATION AND FUTION DESCRIPTIONS A 3 TOP VIEW (Not to Scale) 7 9-3µm Figure. -Lead SOIC Table 3. -Lead SOIC Pin Function Descriptions Pin No. Mnemonic X Y IN 9... 3. 3 A +9. 3. +. 3. +. +7. +Vs +. +7. 7 NA NA 9. +. µm A 9- Figure. Metallization Photograph Rev. C Page of
TYPICAL PERFORMAE CHARACTERISTICS TA = C, VS = V, VCM = V, RL = kω, unless otherwise noted. 9 PSRR (db) 7 3 COMMON-MODE VOLTAGE (V) C C + C + C k k k 9-3 + C 3 3 7 9 3 9-9 FREQUEY (Hz) POWER SUPPLY (V) Figure. Power Supply Rejection Ratio vs. Frequency Valid for CM Range V to + V Figure 9. Negative Common-Mode Voltage vs. Voltage Supply 3 PUT (db) k k k M FREQUEY (Hz) 9-7 COMMON-MODE VOLTAGE (V) 3 3 C C + C + C + C 3 7 9 POWER SUPPLY (V) 9-3 Figure 7. Bandwidth Figure. Positive Common-Mode Voltage vs. Voltage Supply.. 9. CMRR (db) 9 PUT SWING (V) 3. 3.... 7 7 k k k 9-.. k k 9- FREQUEY (Hz) LOAD RESISTAE (Ω) Figure. Common-Mode Rejection Ratio vs. Frequency Valid for CM Range V to + V Figure. Output Swing vs. Load Resistance Rev. C Page 7 of
PUT MINUS SUPPLY (mv) 3 NO LOAD k LOAD 3 V SUPPLY = TEMPERATURE RANGE = C TO C 7 3 7 9 SUPPLY VOLTAGE (V) 9-3. 9.. 7.... 3..... 3.... 7.. V OS DRIFT (µv/ C) 9.. 9-7 Figure. Output Minus Supply vs. Supply Voltage Figure. Offset Drift Distribution, SOIC PUT 3 TEMPERATURE = C 3 INPUT CH mvω CH mvω M µs.ms/s NS/PT A CH.73V 9-3 3 9 7 3 3 7 9 3 V OS (µv) 9- Figure 3. Pulse Response Figure. VOS Distribution, SOIC V SUPPLY = TEMPERATURE RANGE = C TO + C 3 3 TEMPERATURE = C. 9.. 7.... 3..... V OS DRIFT (µv/ C) 3... Figure. Offset Drift Distribution, SOIC. 7.. 9.. 9-3 9 7 3 3 7 9 3 V OS (µv) Figure 7. VOS Distribution, SOIC 9-9 Rev. C Page of
3 TEMPERATURE = C TEMPERATURE = C 3 3 3 9 7 3 3 7 9 3 V OS (µv) Figure. VOS Distribution, SOIC 9-3...3....7..9....3....7..9....3....7..9.3 ERROR (%) Figure. SOIC Gain Accuracy 9-33 3 TEMPERATURE = C 7 V SUPPLY = TEMPERATURE RANGE = C TO + C 3 3...3....7..9....3....7..9....3....7..9.3 9-3 9-3 ERROR (%) V OS DRIFT (µv/ C) Figure 9. SOIC Gain Accuracy Figure. Offset Drift Distribution, MSOP 3 TEMPERATURE = C V SUPPLY = TEMPERATURE RANGE = C TO C 3...3....7..9....3....7..9....3....7..9.3 9-3 9-3 ERROR (%) V OS DRIFT (µv/ C) Figure. SOIC Gain Accuracy Figure 3. Offset Drift Distribution, MSOP Rev. C Page 9 of
TEMPERATURE = C TEMPERATURE = C 9-37 9- V OS (µv)..3..9.7..3...3..7.9..3..7.9..3..7.9 ERROR (%) Figure. VOS Distribution, MSOP Figure 7. MSOP Gain Accuracy 9 TEMPERATURE = C TEMPERATURE = C 7 3 V OS (µv) 9-3..3..9.7..3...3..7.9..3..7.9..3..7.9 ERROR (%) 9- Figure. VOS Distribution, MSOP Figure. MSOP Gain Accuracy 9 TEMPERATURE = C TEMPERATURE = C 7 3 V OS (µv) Figure. VOS Distribution, MSOP 9-39..3..9.7..3...3..7.9..3..7.9..3..7.9 ERROR (%) Figure 9. MSOP Gain Accuracy 9- Rev. C Page of
TEMPERATURE = C V OS (µv) + C + C C 7 3 3 CMRR (µv/v) 3 3 7 Figure 3. CMRR Distribution, V to + V Common Mode 9-3 + C 3 COMMON-MODE VOLTAGE (V) Figure 3. VOS vs. Common-Mode Voltage 9- Rev. C Page of
THEORY OF OPERATION The consists of a preamp and buffer arranged as shown in Figure 3. Like-named resistors have equal values. The preamp uses a dynamic bridge (subtractor) circuit. Identical networks (within the shaded areas), consisting of RA, RB, RC, and RG, attenuate input signals applied to Pins and. When equal amplitude signals are asserted at inputs and, and the output of A is equal to the common potential (that is, ), the two attenuators form a balanced-bridge network. When the bridge is balanced, the differential input voltage at A, and thus its output, is. Any common-mode voltage applied to both inputs keeps the bridge balanced and the A output at zero. Because the resistor networks are carefully matched, the common-mode signal rejection approaches this ideal state. However, if the signals applied to the inputs differ, the result is a difference at the input to A. A responds by adjusting its output to drive RB, by way of RG, to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. By attenuating voltages at Pins and, the amplifier inputs are held within the power supply range, even if Pin and Pin input levels exceed the supply or fall below common (ground). The input network also attenuates normal (differential) mode voltages. RC and RG form an attenuator that scales A feedback, forcing large output signals to balance relatively small differential inputs. The resistor ratios establish the preamp gain at. Because the differential input signal is attenuated and then amplified to yield an overall gain of, Amplifier A operates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to Pins and. To minimize these errors while extending the common-mode range, a dedicated feedback loop is employed to reduce the range of common-mode voltage applied to A for a given overall range at the inputs. By offsetting the voltage range applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. Amplifier A3 detects the common-mode signal applied to A and adjusts the voltage on the matched RCM resistors to reduce the common-mode voltage range at the A inputs. By adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. The output of the dynamic bridge taken from A is connected to Pin 3 by way of a kω series resistor, provided for lowpass filtering and gain adjustment. The resistors in the input networks of the preamp and the buffer feedback resistors are ratio trimmed for high accuracy. The output of the preamp drives a gain-of- buffer amplifier,, implemented with carefully matched feedback resistors, RF. The -stage system architecture of the enables the user to incorporate a low-pass filter prior to the output buffer. By separating the gain into two stages, a full-scale, rail-to-rail signal from the preamp can be filtered at Pin 3, and a half-scale signal, resulting from filtering, can be restored to full scale by the output buffer amp. The source resistance seen by the inverting input of is approximately kω to minimize the effects of s input bias current. However, this current is quite small and errors resulting from applications that mismatch the resistance are correspondingly small. R A R A R CM R kω A 3 CM (TRIMMED) R F R G R B R C R B R C R G A3 R F COM 9- Figure 3. Simplified Schematic Rev. C Page of
APPLICATIONS The difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. The differential input resistance is nominally 3 kω, and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. The open-collector output stage sources current to within mv of ground and to within mv of VS. V CM A kω kω R EXT GAIN = R EXT + kω kω R EXT = kω GAIN GAIN CURRENT SENSING High-Line, High Current Sensing Basic automotive applications using the large common-mode range are shown in Figure and Figure 3. The capability of the device to operate as an amplifier in primary battery-supply circuits is shown in Figure ; Figure 3 illustrates the ability of the device to withstand voltages below system ground. Low Current Sensing The can also be used in low current sensing applications, such as the to ma current loop shown in Figure 33. In such applications, the relatively large shunt resistor can degrade the common-mode rejection. Adding a resistor of equal value on the low impedance side of the input corrects for this error. + Ω % Ω % A PUT R EXT Figure 3. Adjusting for Gains Less than The overall bandwidth is unaffected by changes in gain by using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. In many cases this can be ignored, but if desired, it can be nulled by inserting a resistor equal to kω minus the parallel sum of REXT and kω, in series with Pin. For example, with REXT = kω (yielding a composite gain of ), the optional offset nulling resistor is kω. Gains Greater than Connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in Figure 3, increases the gain. The gain is multiplied by the factor REXT/(REXT kω); for example, it is doubled for REXT = kω. Overall gains as high as are achievable in this way. The accuracy of the gain becomes critically dependent on the resistor value at high gains. Also, the effective input offset voltage at Pin and Pin (about six times the actual offset of A) limits the part s use in high gain, dc-coupled applications. 9- GAIN ADJUSTMENT Figure 33. to ma Current Loop Receiver The default gain of the preamplifier and buffer are and, respectively, resulting in a composite gain of. With the addition of external resistor(s) or trimmer(s), the gain may be lowered, raised, or finely calibrated. Gains Less than Because the preamplifier has an output resistance of kω, an external resistor connected from Pins 3 and to decreases the gain by a factor REXT/( kω + REXT) as shown in Figure 3. 9- V CM A kω kω R EXT GAIN = R EXT kω R EXT kω R EXT = kω GAIN GAIN Figure 3. Adjusting for Gains Greater than 9-7 Rev. C Page 3 of
GAIN TRIM Figure 3 shows a method for incremental gain trimming by using a trim potentiometer and external resistor, REXT. The following approximation is useful for small gain ranges: ΔG ( MΩ REXT)% Thus, the adjustment range is ±% for REXT = MΩ; ±% for REXT = MΩ, and so on. Low-pass filters can be implemented in several ways by using the. In the simplest case, a single-pole filter ( db/decade) is formed when the output of A is connected to the input of via the internal kω resistor by tying Pin 3 and Pin and adding a capacitor from this node to ground, as shown in Figure 37. If a resistor is added across the capacitor to lower the gain, the corner frequency increases; it should be calculated using the parallel sum of the resistor and kω. PUT V CM A R EXT GAIN TRIM kω MIN V CM A f C = πc C IN FARADS C 9-9-9 Figure 3. Incremental Gain Trim Internal Signal Overload Considerations When configuring gain for values other than, the maximum input voltage with respect to the supply voltage and ground must be considered, because either the preamplifier or the output buffer reaches its full-scale output (approximately VS. V) with large differential input voltages. The input of the is limited to (VS.) for overall gains, because the preamplifier, with its fixed gain of, reaches its full-scale output before the output buffer. For gains greater than, the swing at the buffer output reaches its full scale first and limits the input to (VS.) G, where G is the overall gain. LOW-PASS FILTERING In many transducer applications, it is necessary to filter the signal to remove spurious high frequency components including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (PAR) greater than unity. For example, a full-wave rectified sinusoid has a PAR of.7, a raised cosine has a PAR of, and a half-wave sinusoid has a PAR of 3.. Signals having large spikes may have PARs of or more. When implementing a filter, the PAR should be considered so that the output of the preamplifier (A) does not clip before, because this nonlinearity would be averaged and appear as an error at the output. To avoid this error, both amplifiers should clip at the same time. This condition is achieved when the PAR is no greater than the gain of the second amplifier ( for the default configuration). For example, if a PAR of is expected, the gain of should be increased to. Figure 37. Single-Pole, Low-Pass Filter Using the Internal kω Resistor If the gain is raised using a resistor, as shown in Figure 3, the corner frequency is lowered by the same factor as the gain is raised. Thus, using a resistor of kω (for which the gain would be doubled), the corner frequency is now.79 Hz/µF (.39 µf for a Hz corner frequency.) V CM A C kω Figure 3. -Pole, Low-Pass Filter C f C (Hz) = /C(µF) A -pole filter (with a roll-off of db/decade) can be implemented using the connections shown in Figure 3. This is a Sallen-Key form based on a amplifier. It is useful to remember that a -pole filter with a corner frequency f and a -pole filter with a corner at f have the same attenuation at the frequency (f /f). The attenuation at that frequency is log (f/f), which is illustrated in Figure 39. Using the standard resistor value shown and equal capacitors (Figure 3), the corner frequency is conveniently scaled at Hz/µF (. µf for a Hz corner). A maximally flat response occurs when the resistor is lowered to 9 kω and the scaling is then. Hz/µF. The output offset is raised by approximately mv (equivalent to µv at the input pins). 9- Rev. C Page of
ATTENUATION FREQUEY db/decade db/decade low-pass filter, set here with a corner frequency of 3. Hz, which provides about 3 db of attenuation at Hz. A higher rate of attenuation can be obtained using a -pole filter with fc = Hz, as shown in Figure. Although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the -pole filter. LOG (f /f ) A -POLE FILTER, CORNER f, AND A -POLE FILTER, CORNER f, HAVE THE SAME ATTENUATION LOG (f /f ) AT FREQUEY f /f f f f /f Figure 39. Comparative Responses of -Pole and -Pole Low-Pass Filters HIGH-LINE CURRENT SENSING WITH LPF AND GAIN ADJUSTMENT Figure is another refinement of Figure, including gain adjustment and low-pass filtering. BATTERY CLAMP DIODE V -TERM SHUNT POWER DEVICE INDUCTIVE LOAD COMMON A C V OS/IB NULL Figure. High-Line Current Sensor Interface; Gain =, Single-Pole, Low-Pass Filter V/AMP 9kΩ kω % CALIBRATION RANGE f C (Hz) =.79Hz/C(µF) (.µf FOR f C = 3.Hz) A power device that is either on or off controls the current in the load. The average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. The average differential voltage across the shunt is typically mv, although its peak value is higher by an amount that depends on the inductance of the load and the control frequency. The common-mode voltage, conversely, extends from roughly V above ground for the on condition to about. V above the battery voltage in the off condition. The conduction of the clamping diode regulates the common-mode potential applied to the device. For example, a battery spike of V may result in an applied common-mode potential of. V to the input of the devices. 9-9- BATTERY CLAMP DIODE V -TERM SHUNT POWER DEVICE INDUCTIVE LOAD COMMON A Figure. -Pole Low-Pass Filter C 7kΩ f C (Hz) = /C(µF) (.µf FOR f C = Hz) DRIVING CHARGE REDISTRIBUTION ADCS C 3kΩ kω PUT When driving CMOS ADCs such as those embedded in popular microcontrollers, the charge injection ( Q) can cause a significant deflection in the output voltage of the. Though generally of short duration, this deflection may persist until after the sample period of the ADC expires due to the relatively high open-loop output impedance (typ kω) of the. Including an R-C network in the output can significantly reduce the effect. The capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the. For these applications, the output signal should be taken from the midpoint of the RLAG CLAG combination, as shown in Figure. Because the perturbations from the analog-to-digital converter are small, the output impedance of the appears to be low. The transient response, therefore, has a time constant governed by the product of the two LAG components, CLAG RLAG. For the values shown in Figure, this time constant is programmed at approximately µs. Therefore, if samples are taken at several tenths of microseconds or more, there is negligible charge stack-up. kω R LAG kω C LAG.µF MICROPROCESSOR A/D 9-3 To produce a full-scale output of V, a gain is used, adjustable by ±% to absorb the tolerance in the shunt. Sufficient headroom allows % overrange (to. V). The roughly triangular voltage across the sense resistor is averaged by a -pole, kω Figure. Recommended Circuit for Driving CMOS A/D 9- Rev. C Page of
LINE DIMENSIONS. (.9). (.9). (.7) 3. (.97). (.). (.). (.9). (.) COPLANARITY..7 (.) BSC SEATING PLANE.7 (.).3 (.3). (.).3 (.). (.9).7 (.7). (.9). (.99).7 (.). (.7) COMPLIANT TO JEDEC STANDARDS MS-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; IH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFEREE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 3. -Lead Standard Small Outline Package [SOIC_N], Narrow Body (R-), Dimensions shown in millimeters and (inches) 3. BSC 3. BSC.9 BSC PIN. BSC...3. COPLANARITY.. MAX SEATING PLANE.3. COMPLIANT TO JEDEC STANDARDS MO-7AA... Figure. -Lead Mini Small Outline Package [MSOP], (RM-), Dimensions shown in millimeters ORDERING GUIDE Model Temperature Package Package Description Package Outline Branding YR C to + C Lead Standard Small Outline Package (SOIC_N) R- YR-REEL C to + C -Lead Standard Small Outline Package (SOIC_N) R- YR-REEL7 C to + C -Lead Standard Small Outline Package (SOIC_N) R- YRZ C to + C Lead Standard Small Outline Package (SOIC_N) R- YRZ-RL C to + C -Lead Standard Small Outline Package (SOIC_N) R- YRZ-R7 C to + C -Lead Standard Small Outline Package (SOIC_N) R- YRMZ C to + C -Lead Mini Small Outline Package (MSOP) RM- JWY YRMZ-RL C to + C -Lead Mini Small Outline Package (MSOP) RM- JWY YRMZ-R7 C to + C -Lead Mini Small Outline Package (MSOP) RM- JWY YCSURF Die Z = Pb-free part. Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D9 /(C) Rev. C Page of