Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd Chapter 3 28 Pearson Education 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The Inverter The inverter performs the oolean NOT operation. When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW. Input Output LOW () HIGH () HIGH () LOW() The NOT operation (complement) is shown with an overbar. Thus, the oolean expression for an inverter is =. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The Inverter Example waveforms: group of inverters can be used to form the s complement of a binary number: inary number s complement 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The ND Gate & The ND gate produces a HIGH output when all inputs are HIGH; otherwise, the output is LOW. For a 2-input gate, the truth table is Inputs Output The ND operation is usually shown with a dot between the variables but it may be implied (no dot). Thus, the ND operation is written as =. or =. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The ND Gate & Example waveforms: The ND operation is used in computer programming as a selective mask. If you want to retain certain bits of a binary number but reset the other bits to, you could set a mask with s in the position of the retained bits. If the binary number is NDed with the mask, what is the result? 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The ND Gate Multisim circuit is shown. WG is a word generator set in the count down mode. L is a logic analyzer with the output of the ND gate connected to first (upper) line of the analyzer. What signal do you expect to on this line? The output (line ) will be HIGH only when all of the inputs are HIGH. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The OR Gate The OR gate produces a HIGH output if any input is HIGH; if all inputs are LOW, the output is LOW. For a 2-input gate, the truth table is Inputs Output The OR operation is shown with a plus sign (+) between the variables. Thus, the OR operation is written as = +. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The OR Gate Example waveforms: The OR operation can be used in computer programming to set certain bits of a binary number to. SCII letters have a in the bit 5 position for lower case letters and a in this position for capitals. (it positions are numbered from right to left starting with.) What will be the result if you OR an SCII letter with the 8-bit mask? The resulting letter will be lower case. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The OR Gate Multisim circuit is shown. WG is a word generator set to count down. L is a logic analyzer with the output connected to first (top) line of the analyzer. The three 2-input OR gates act as a single 4-input gate. What signal do you expect on the output line? The output (line ) will be HIGH if any input is HIGH; otherwise it will be LOW. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NND Gate & The NND gate produces a LOW output when all inputs are HIGH; otherwise, the output is HIGH. For a 2-input gate, the truth table is Inputs Output The NND operation is shown with a dot between the variables and an overbar covering them. Thus, the NND operation is written as =. (lternatively, =.) 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NND Gate & Example waveforms: The NND gate is particularly useful because it is a universal gate all other basic gates can be constructed from NND gates. How would you connect a 2-input NND gate to form a basic inverter? 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NND Gate Multisim circuit is shown. WG is a word generator set in the count up mode. four-channel oscilloscope monitors the inputs and output. What output signal do you expect to see? The output (channel D) will be LOW only when all of the inputs are HIGH. Inputs 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NOR Gate The NOR gate produces a LOW output if any input is HIGH; if all inputs are HIGH, the output is LOW. For a 2-input gate, the truth table is Inputs Output The NOR operation is shown with a plus sign (+) between the variables and an overbar covering them. Thus, the NOR operation is written as = +. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NOR Gate Example waveforms: The NOR operation will produce a LOW if any input is HIGH. +5. V When is the LED is ON for the circuit shown? The LED will be on when any of the four inputs are HIGH. C D 33 W 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The OR Gate = The OR gate produces a HIGH output only when both inputs are at opposite logic levels. The truth table is Inputs Output The OR operation is written as = +. lternatively, it can be written with a circled plus sign between the variables as = +. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The OR Gate = Example waveforms: Notice that the OR gate will produce a HIGH only when exactly one input is HIGH. If the and waveforms are both inverted for the above waveforms, how is the output affected? There is no change in the output. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NOR Gate = The NOR gate produces a HIGH output only when both inputs are at the same logic level. The truth table is Inputs Output The NOR operation shown as = +. lternatively, the NOR operation can be shown with a circled dot between the variables. Thus, it can be shown as =.. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

The NOR Gate = Example waveforms: Notice that the NOR gate will produce a HIGH when both inputs are the same. This makes it useful for comparison functions. If the waveform is inverted but remains the same, how is the output affected? The output will be inverted. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Fixed Function Logic Two major fixed function logic families are TTL and CMOS. third technology is icmos, which combines the first two. Packaging for fixed function logic is shown..335.334 in. 4 3 2.74.77 in. 4 3 2 9 2 3 4 5 6 6 7.228.244 in. 7 Pin no. identifiers 8 8.25 ±. in. 9 2 3 4 5 Lead no. identifier 4 4 DIP package SOIC package 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Fixed Function Logic Some common gate configurations are shown. VCC VCC 4 3 2 9 2 3 4 5 6 ' 8 7 GND VCC 2 3 4 5 6 ' 8 7 GND VCC 2 3 4 5 6 ' 2 7 GND 2 3 4 '27 5 6 8 7 GND 2 3 4 5 6 ' 2 3 4 5 6 '4 8 7 GND 8 7 GND 2 3 4 '3 5 6 8 7 GND 2 3 4 5 6 '2 2 3 4 5 6 '8 8 7 GND 8 7 GND 4 3 2 9 2 3 4 5 6 '2 8 7 GND VCC 4 3 2 9 4 3 2 9 VCC 4 3 2 9 VCC 4 3 2 9 VCC 4 3 2 9 VCC 4 3 2 9 VCC 4 3 2 9 8 VCC 4 3 2 9 VCC 4 3 2 9 2 3 4 '32 5 6 8 7 GND 4 3 2 9 2 3 4 '86 5 6 8 7 GND 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Fixed Function Logic Logic symbols show the gates and associated pin numbers. VCC (4) () (3) (2) (4) (6) (5) (9) (8) () (2) () (3) () (2) (4) (5) (9) () (2) (3) & (3) (6) (8) () (7) GND 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Fixed Function Logic Data sheets include limits and conditions set by the manufacturer as well as DC and C characteristics. For example, some maximum ratings for a 74HC are: MIMUM RTINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND).5 to + 7. V V V in DC InputVoltage (Referenced to GND).5 to VCC +.5 V V V out DC Output Voltage (Referenced to GND).5 to VCC +.5 V V I in DC Input Current, per pin ± 2 m Iout DC Output Current, per pin ± 25 m ICC DC Supply Current, VCC and GND pins ± 5 m PD Power Dissipation in Still ir, Plastic or Ceramic DIP 75 mw 5 SOIC Package TSSOP Package 45 Tstg Storage Temperature 65 to + 5 C TL Lead Temperature, mm from Case for Seconds C 26 Plastic DIP, SOIC, or TSSOP Package 3 Ceramic DIP 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Programmable Logic Programmable Logic Device (PLD) can be programmed to implement logic. There are various technologies available for PLDs. Many use an internal array of ND gates to form logic terms. Many PLDs can be programmed multiple times. SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell = 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Programmable Logic In general, the required logic for a PLD is developed with the aid of a computer. The logic can be entered using a Hardware Description Language (HDL) such as VHDL. Logic can be specified to the HDL as a text file, a schematic diagram, or a state diagram. text entry for a programming a PLD in VHDL as a 2-input NND gate is shown for reference in the following slide. In this case, the inputs and outputs are first specified. Then the signals are described. lthough you are probably not familiar with VHDL, you can see that the program is simple to read. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Programmable Logic entity NandGate is port(, : in bit; LED: out bit); end entity NandGate; architecture Gateehavior of NandGate is signal, : bit; begin <= nand ; LED <= ; end architecture Gateehavior; 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Selected Key Terms Inverter logic circuit that inverts or complements its inputs. Truth table table showing the inputs and corresponding output(s) of a logic circuit. Timing diagram of waveforms showing the proper time diagram relationship of all of the waveforms. oolean The mathematics of logic circuits. algebra ND gate logic gate that produces a HIGH output only when all of its inputs are HIGH. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

Selected Key Terms OR gate logic gate that produces a HIGH output when one or more inputs are HIGH. NND gate logic gate that produces a LOW output only when all of its inputs are HIGH. NOR gate logic gate that produces a LOW output when one or more inputs are HIGH. Exclusive OR logic gate that produces a HIGH output only gate when its two inputs are at opposite levels. Exclusive NOR logic gate that produces a LOW output only gate when its two inputs are at opposite levels. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved

. The truth table for a 2-input ND gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

2. The truth table for a 2-input NOR gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

3. The truth table for a 2-input OR gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

4. The symbol is for a(n) a. OR gate b. ND gate c. NOR gate d. OR gate 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

5. The symbol is for a(n) a. OR gate b. ND gate c. NOR gate d. OR gate 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

6. logic gate that produces a HIGH output only when all of its inputs are HIGH is a(n) a. OR gate b. ND gate c. NOR gate d. NND gate 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

7. The expression = + means a. OR b. ND c. OR d. NOR 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

8. 2-input gate produces the output shown. ( represents the output.) This is a(n) a. OR gate b. ND gate c. NOR gate d. NND gate 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

9. 2-input gate produces a HIGH output only when the inputs agree. This type of gate is a(n) a. OR gate b. ND gate c. NOR gate d. NOR gate 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

. The required logic for a PLD can be specified in an Hardware Description Language by a. text entry b. schematic entry c. state diagrams d. all of the above 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved 28 Pearson Education

nswers:. c 6. b 2. b 7. c 3. a 8. d 4. a 9. d 5. d. d 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved