Digital E A B C D 0 1 2 3 4 5 6 Design 7 8 9 10 11 12 13 14 15 Y R. Ananda Natarajan
Digital Design
Digital Design R. ANANDA NATARAJAN Professor Department of Electronics and Instrumentation Engineering Pondicherry Engineering College Puducherry Delhi-110092 2015
DIGITAL DESIGN R. Ananda Natarajan 2015 by PHI Learning Private Limited, Delhi. All rights reserved. No part of this book may be reproduced in any form, by mimeograph or any other means, without permission in writing from the publisher. ISBN-978-81-203-4977-3 The export rights of this book are vested solely with the publisher. Published by Asoke K. Ghosh, PHI Learning Private Limited, Rimjhim House, 111, Patparganj Industrial Estate, Delhi-110092 and Printed by Mohan Makhijani at Rekha Printers Private Limited, New Delhi-110020.
To My beloved mother Late R. Saraswathi Ramaiah (1939 2014)
Contents Preface xvii Acknowledgements xix 1. Number System 1 52 Learning Objectives 1 1.1 Introduction to Digital Systems 1 1.1.1 Decimal Number System 1 1.1.2 Octal Number System 2 1.1.3 Hexadecimal Number System 2 1.1.4 Binary Number System 2 1.1.5 Why Binary Number System is Used in Computers 3 1.2 Number Base Conversions 4 1.2.1 Decimal to Binary and Binary to Decimal Conversions 4 1.2.2 Decimal to Octal and Octal to Decimal Conversions 6 1.2.3 Decimal to Hexadecimal and Hexadecimal to Decimal Conversions 7 1.2.4 Need for Octal and Hexadecimal Systems 9 1.2.5 Binary to Hexadecimal and Octal Conversions 9 1.3 Complement of a Number 10 1.4 (r 1) s Complement of a Number 11 1.5 2 s Complement and 1 s Complement 13 1.6 Binary Arithmetic 14 1.6.1 Binary Addition 14 1.6.2 Binary Subtraction 15 1.6.3 Binary Multiplication 16 1.6.4 Binary Division 16 1.7 1 s Complement Subtraction 17 1.8 2 s Complement Subtraction 18 1.9 Signed Binary Numbers 20 1.9.1 Signed Binary Addition 20 1.9.2 Signed Binary Subtraction 22 1.10 Binary Codes 25 1.10.1 Binary Coded Decimal (BCD) or 8421 Code 25 1.10.2 2421 Code 25 vii
viii Contents 1.10.3 5421 Code 26 1.10.4 Excess-3 Code 27 1.10.5 Gray Code 27 1.10.6 Advantage of Gray Code 29 1.10.7 Binary Coded Pentary (BCP) Code 30 1.10.8 Alphanumeric Codes 30 1.10.9 Error Detecting and Correcting Codes 32 1.10.10 Parity Code 33 1.10.11 Other Error-Detection Codes 33 1.10.12 Hamming Code 34 Multiple Choice Questions with Answers 36 Solutions to Multiple Choice Questions 38 Short Questions with Answers 40 Review Questions 52 2. Boolean Algebra 53 163 Learning Objectives 53 2.1 Introduction 53 2.2 Fundamental Definitions 54 2.2.1 Inverse Operation or Logical Negation (NOT) 54 2.2.2 Logical AND Operation 54 2.2.3 Logical OR Operation 55 2.3 Boolean Postulates and Theorems 56 2.3.1 Truth Table 60 2.3.2 Proof of DeMorgan s First Theorem Using Truth Table (Perfect Induction Method) 60 2.3.3 Proof of DeMorgan s Second Theorem 61 2.3.4 Principle of Duality 61 2.3.5 Consensus Theorem 61 2.3.6 Algebraic Simplifications and Manipulations 62 2.3.7 Transposition Theorem 62 2.3.8 Complement of a Function 68 2.4 Minterms and Maxterms 68 2.4.1 Minterms 68 2.4.2 Maxterms 69 2.5 Binary Logic 70 2.5.1 Definitions of Binary Logic 70 2.6 Electronic Logic Gates 70 2.6.1 NAND Gate 72 2.6.2 NOR Gate 72 2.6.3 Exclusive OR (XOR) Gate 73 2.6.4 Exclusive NOR (XNOR) Gate 73 2.7 Preparing Logic Diagrams 74 2.7.1 Extension of Multi-inputs 74 2.7.2 Fanout and Fanin 74 2.7.3 High Impedance State in Gates 74 2.7.4 Buffer 74 2.7.5 Equivalent Circuit Representations 83
Contents ix 2.8 Sum of Products (SOP) and Product of Sums (POS) Expressions 85 2.8.1 Sum of Products (SOP) 85 2.8.2 Product of Sums (POS) 85 2.8.3 Standard Form or Canonical Form 86 2.9 Logic Design 86 2.10 Universal Building Blocks 88 2.10.1 NAND is Universal Building Block 88 2.10.2 NOR is a Universal Building Block 89 2.10.3 Procedure to Convert a Given Logic Circuit in Terms of NAND Gate Implementation 89 2.10.4 Procedure to Realise the Given Logic Expression Using NOR Gate 91 2.11 Karnaugh Map 94 2.11.1 Two Variable Karnaugh Map for Sum of Products Form (SOP) 94 2.11.2 Three Variable Karnaugh Map for Sum of Products Form (SOP) 98 2.11.3 Four Variable Karnaugh Map for Sum of Products Form (SOP) 101 2.11.4 Five Variable Karnaugh Map for Sum of Products Form (SOP) 105 2.11.5 Don t Care Combinations 106 2.11.6 Product of Sums Form (POS) 108 2.11.7 Implicant 110 2.12 Quine-McCluskey or Tabulation Method of Minimisation of Logic Functions 116 Multiple Choice Questions with Answers 125 Solutions to Multiple Choice Questions 134 Short Questions with Answers 142 Review Questions 160 3. Arithmetic Circuits 164 189 Learning Objectives 164 3.1 Introduction 164 3.2 Steps to Design Arithmetic Circuits 164 3.3 Adder 165 3.3.1 Half Adder 165 3.3.2 Full Adder 167 3.3.3 Parallel Adder (Ripple Carry Adder) 169 3.4 Subtractor 170 3.4.1 Half Subtractor 170 3.4.2 Full Subtractor 171 3.4.3 Parallel Subtractor 173 3.4.4 One s Complement Generator 174 3.5 Adder/Subtractor 174 3.6 Propagation Delay in Adders 175 3.6.1 Carry Look Ahead Adder 176 3.7 Serial Arithmetic Circuits 177 3.7.1 BCD Adder 177 3.7.2 Binary Multiplier 180 3.7.3 Parallel Multiplier 180 Multiple Choice Questions with Answers 182 Solutions to Multiple Choice Questions 184 Short Questions with Answers 184 Review Questions 188
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