N-channel 650 V, 0.15 Ω typ., 20 A MDmesh M2 Power MOSFET in a TO-220FP ultra narrow leads package. Features. Description.

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Transcription:

N-channel 650 V, 0.15 Ω typ., 20 A MDmesh M2 Power MOSFET in a TO-220FP ultra narrow leads package Datasheet - production data Features Order code VDS RDS(on) max ID 650 V 0.18 Ω 20 A 1 2 3 Extremely low gate charge Excellent output capacitance (Coss) profile 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram G(1) TO-220FP ultra narrow leads D(2) Applications Switching applications Description This device is an N-channel Power MOSFET developed using MDmesh M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packaging 28N65M2 TO-220FP ultra narrow leads Tube November 2015 DocID027607 Rev 3 1/12 This is information on a product in full production. www.st.com

Contents Contents 1 Electrical ratings... 3 2 Electrical characteristics... 4 2.1 Electrical characteristics (curves)... 6 3 Test circuit... 8 4 Package mechanical data... 9 4.1 TO-220FP ultra narrow leads package information... 9 5 Revision history... 11 2/12 DocID027607 Rev 3

Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 C 20 (1) A ID Drain current (continuous) at TC = 100 C 13 (1) A IDM (2) Drain current (pulsed) 80 A PTOT Total dissipation at TC = 25 C 30 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 C) dv/dt (3) Peak diode recovery voltage slope 15 dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Tj Notes: Storage temperature Operating junction temperature (1) Current limited by package. (2) Pulse width limited by safe operating area. (3) ISD 20 A, di/dt 400 A/µs; VDSpeak < V(BR)DSS, VDD = 520 V (4) VDS 520 V 2500 V V/ns - 55 to 150 C Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 4.17 C/W Rthj-amb Thermal resistance junction-ambient max 62.5 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR EAS Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) Single pulse avalanche energy (starting Tj = 25 C, ID = IAR; VDD = 50 V) 2.4 A 760 mj DocID027607 Rev 3 3/12

Electrical characteristics 2 Electrical characteristics (TC = 25 C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 1 ma, VGS = 0 V 650 V IDSS IGSS Zero gate voltage drain current (VGS = 0) Gate-body leakage current (VDS = 0) VDS = 650 V 1 µa VDS = 650 V, TC = 125 C 100 µa VGS = ± 25 V ±10 µa VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µa 2 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 10 A 0.15 0.18 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance - 1440 - pf Coss Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 60 - pf Crss Reverse transfer capacitance - 2 - pf C oss eq. (1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 307 - pf RG Intrinsic gate resistance f = 1 MHz, ID = 0-4.9 - Ω Qg Total gate charge VDD = 520 V, ID = 20 A, - 35 - nc Qgs Gate-source charge VGS = 10 V ( see Figure 15: "Test circuit for gate - 6 - nc Qgd Gate-drain charge charge behavior" ) - 15 - nc Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 325 V, ID = 10 A, - 13.4 - ns tr Rise time RG = 4.7 Ω, VGS = 10 V ( see Figure 14: "Test circuit - 10 - ns td(off) Turn-off delay time for resistive load switching - 59 - ns tf Fall time times" and Figure 19: "Switching time waveform" ) - 8.8 - ns 4/12 DocID027607 Rev 3

Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 20 A ISDM (1) Source-drain current (pulsed) - 80 A VSD (2) Forward on voltage ISD = 20 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 384 ns Qrr Reverse recovery charge VDD = 60 V ( see Figure 16: "Test circuit for inductive - 5.7 µc IRRM Reverse recovery current load switching and diode recovery times" ) - 30 A trr Reverse recovery time ISD = 20 A, di/dt = 100 A/µs, - 544 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 C, (see Figure 16: "Test circuit - 8.2 µc IRRM Reverse recovery current for inductive load switching and diode recovery times" ) - 30.5 A Notes: (1) Pulse width limited by safe operating area. (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5%. DocID027607 Rev 3 5/12

Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics GIPG031220141331MT ID(A) VGS=7, 8, 9, 10V 50 6V 40 Figure 5: Transfer characteristics ID GIPG031220141336MT (A) VDS=20V 50 40 30 20 5V 30 20 10 10 4V 0 0 4 8 12 16 20 VDS(V) 0 0 2 4 6 8 VGS(V) Figure 6: Normalized gate threshold voltage vs. temperature VGS(th) GIPD180920141442FSR (norm) 1.1 ID = 250 µ A 1.0 0.9 0.8 0.7 0.6-75 -25 25 75 125 Tj( C) Figure 7: Normalized V(BR)DSS vs. temperature V(BR)DSS GIPD180920141448FSR (norm) 1.08 ID= 1m A 1.04 1.00 0.96 0.92 0.88-75 -25 25 75 125 Tj( C) 6/12 DocID027607 Rev 3

Figure 8: Static drain-source on-resistance GIPG031220141344MT RDS(on) (Ω) 0.158 VGS=10V 0.156 0.154 0.152 0.150 0.148 0.146 0.144 0 4 8 12 16 ID(A) Electrical characteristics Figure 9: Normalized on-resistance vs. temperature RDS(on) GIPD180920141459FSR (norm) 2.2 VGS= 10V 1.8 1.4 1 0.6 0.2-75 -25 25 75 125 Tj( C) Figure 10: Gate charge vs gate-source voltage VGS (V) 12 10 8 6 4 2 VDS VDD=520V ID=20 A GIPG031220141340MT VDS (V) 500 400 300 200 100 0 0 0 10 20 30 40 Qg(nC) Figure 11: Capacitance variations GIPG031220141347MT C (pf) 10000 Ciss 1000 100 Coss 10 1 Crss 0.1 1 10 100 VDS(V) Figure 12: Output capacitance stored energy GIPG051220141243MT Eoss (µj) Figure 13: Source-drain diode forward characteristics GIPG031220141421MT VSD(V) 10 8 6 4 2 1 0.9 0.8 0.7 0.6 TJ=-50 C TJ=150 C TJ=25 C 0 0 100 200 300 400 500 600 VDS(V) 0.5 0 4 8 12 16 20 ISD(A) DocID027607 Rev 3 7/12

Test circuit 3 Test circuit Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/12 DocID027607 Rev 3

Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 4.1 TO-220FP ultra narrow leads package information Figure 20: TO-220FP ultra narrow leads package outline 8576148_1 DocID027607 Rev 3 9/12

Package mechanical data Dim. Table 9: TO-220FP ultra narrow leads mechanical data mm Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1-0.90 G 4.95 5.20 G1 2.40 2.54 2.70 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 3.20 3.60 L9-1.30 Dia. 3.00 3.20 10/12 DocID027607 Rev 3

Revision history 5 Revision history Table 10: Document revision history Date Revision Changes 09-Mar-2015 1 Initial release 07-Oct-2015 2 Document status promoted from preliminary to production data. 12-Nov-2015 3 Updated Figure 1: "Internal schematic diagram" in cover page. Updated Table 3: "Thermal data". Minor text changes. DocID027607 Rev 3 11/12

IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. 2015 STMicroelectronics All rights reserved 12/12 DocID027607 Rev 3