Yeld Optmsaton of Power-On Reset Cells and Functonal Verfcaton Dpl.-Ing. Olver Esenberger, Dpl.-Ing. Dr. Gerhard Rapptsch, Dpl.-Ing. Stefan Schneder Dpl.-Ing. Dr. Bernd Obermeer*, Dpl.-Ing. Dpl.-Wrtsch.-Ing. Andreas Rpp*, Dpl.-Ing. Dpl.-Kfm. Mchael Pronath* austramcrosystems AG, Schloss Premstaetten, 8141 Unterpremstaetten, Austra * MunEDA GmbH, Stefan-George-Rng 29, 81929 Munch, Germany E-mal: olver.esenberger@austramcrosystems.com Abstract Smulaton based yeld optmsaton s becomng an mportant soluton for ncreasng robustness of analog IP blocks. Ths paper descrbes the yeld optmsaton of a power-on reset cell as part of an analog IP lbrary. Yeld analyss of the ntal desgn s performed and senstvtes wth respect to process parameters are determned by Monte Carlo smulaton. The nput parameters used for the Monte Carlo smulaton descrbe global and local varatons of the semconductor devces. The results of the yeld analyss are used to determne a shft of the PMOS threshold mplant dose enablng a yeld enhancement of the ntal desgn. A re-desgn usng smulaton-based desgn centerng s performed resultng n a sgnfcant yeld ncrease n consderaton of the operatng condtons. The optmsaton s based on an algorthm maxmzng the worst-case-dstance. The smulaton results on mproved producton yeld are verfed by electrcal test at wafer level for varyng process condtons. 1 Introducton The performance and the yeld of analog crcuts are determned by varatons of the producton process. Durng the development of analog buldng blocks (e.g. band gap cells, operatonal amplfers, comparators etc.) the desgner chooses a crcut topology and tres to acheve a gven nomnal target for a pre-defned performance vector. Afterwards t must be verfed that the desgn s functonal under varyng process and operatng condtons (e.g. supply voltage and temperature varaton). To calculate the yeld of a crcut dependent on both global and local varatons, Monte Carlo smulaton s supported for most CAD platforms [1]. A crtcal pont wth respect to the accuracy of Monte Carlo smulaton s the accurate statstcal modellng of the SPICE parameters reflectng the dstrbuton of basc process parameters (e.g. threshold voltage, gan factor or channel length). Methods for accurate determnaton of Monte Carlo parameters from electrcal test data are presented n [2,3]. The dstrbuton of global process parameters s determned from the statstcs of the relevant process control parameters and correlatons of the parameters should be taken nto account. The dstrbuton of local fluctuatons (msmatch) s determned from statstcal parameter extracton of measurements on specal test chps [4,5]. Besdes the nformaton on the yeld of the crcut wth respect to a gven specfcaton t s also mportant to get nformaton about the man contrbutors of yeld loss by means of senstvty analyss wth respect to desgn and process parameters. Ths nformaton can be used n two ways. Frst, for a nomnal desgn havng a low yeld at some operatng corner, the desgner can shft desgn parameters of the relevant devces (man contrbutors) enablng effcent desgn centerng [6,7,8] durng a re-desgn phase. Secondly, durng product ramp up the senstvty analyss gves nformaton about possble process shfts to ncrease the yeld of the orgnal desgn. Desgn for Yeld (DFY) tools provde both senstvty analyss and yeld optmsaton based on Monte Carlo smulaton. Smulaton based yeld optmsaton s performed by desgn centerng and automatc shft of desgn parameters wthn specfed desgn parameter lmts. In the present nvestgaton the yeld of an analog buldng block (power-on reset cell) s ncreased by two ways: frst a shft of producton parameters s calculated from senstvty analyss to ncrease the yeld of the ntal desgn and afterwards a new set of desgn parameters s determned by maxmzng the worst-casedstance (sgma to target) for the reset voltage. The smulated yeld ncrease s verfed by producton results usng process wndow verfcaton. 2 Problem Formulaton and Crcut Descrpton A power-on reset cell has been used as an IP block wthn a mxed-sgnal crcut and has been desgned usng a standard.8µm CMOS technology. Durng yeld ramp-up of the product t turned out that there s sgnfcant yeld loss at low temperature (-4 C). The yeld loss could be attrbuted to the threshold voltage V TRIG of the power-on reset cell whch was measured durng electrcal wafer test. Therefore t was decded to perform a yeld analyss of the crcut pursung two goals: Frst, fnd a possblty to shft the producton process n order to ncrease the producton yeld of the current desgn and afterwards fnd a new set of desgn parameters usng the gven crcut topology (see Fg. 1) that wll result n a mproved yeld over the whole temperature range (-4 C to 85 C) wthout changng the process.
Path 1 Path 2 Path 3 Capactance Inverter Stages 1 2 V RESET V RESET Fg. 1. Schematc of the Power-On Reset Cell The Power-On Reset cell s used to reset the outputs of dgtal gates. When the supply voltage reaches the threshold voltage level V TRIG the output of the cell V RESET swtches to low. The level of the threshold voltage s manly defned by the voltage drop at the transstors n Path 2 and wth ths path the currents of the current sources M4 and M13 are compared. To explan the man functon of the cell two dfferent supply sources consderng the rse tme have to be dstngushed: 1) Slow Rse Tme (s) Fgure 2 shows the smulated transent reset voltage V RESET at room temperature (27 C) when a supply ramp wth a constant slope of 5 V/s s appled. At the begnnng of the transent examnaton the transstor M4 causes a current flow n Path 1 (see Fgure 1). The transstor M13 causes the voltage level at Node 1 to rse wth the supply voltage. The voltage level at ths node s amplfed by two nverters resultng n the reset voltage V RESET. Therefore V RESET rses n the same way as the supply voltage. Supply Voltage Thus a current flows n Path 3 and causes the voltage level at Node 1 to decrease. After the voltage level at Node 1 reaches a certan value (supply voltage reaches threshold voltage level V TRIG ) the frst nverter (M14, M15) delvers a HIGH (correspondng to the value of the connected supply voltage) at ts output (Node 2). Ths sgnal s nverted agan by a second nverter (M16, M17) and delvers therefore a LOW (V) at the reset output V RESET of the Power-On Reset Cell. 2) Fast Rse Tme (µs) Fgure 3 shows the smulated transent reset voltage V RESET at room temperature (27 C) when a supply ramp wth a constant slope of 1 V/µs s appled. Because the supply voltage s rsng very quckly the Power-On Reset s not able to pull down the voltage level a Node 1 fast enough. Therefore the output V RESET does not swtch to zero at the defned threshold voltage V TRIG, but when the supply voltage s already at the maxmum value. To prevent short pulses (spkes) at the output of the cell the RC-element consstng of the transstors M21 (Capactance) and M12, M13, M2 (Conductance) lengthens the pulse duraton at the output V RESET. Supply Voltage Reset Voltage Reset Voltage Fg. 2. Transent characterstc of the reset voltage V RESET for a supply voltage wth a slow rse tme The voltage level at Node 1 rses untl a current can flow n Path 2. Ths current s mrrored by the transstors M9, M1 and fnally by the transstors M11, M12 wth a factor of 3. Fg. 3. Transent characterstc of the reset voltage V RESET for a supply voltage wth a fast rse tme
3 Yeld Analyss and Yeld Enhancement 3.1 Monte Carlo Smulaton The varaton of process parameters s derved from the statstcal dstrbuton of electrcal test parameters for MOS transstors and mapped to the varaton of SPICE parameters used for Monte Carlo smulaton. The global and local varaton of SPICE parameters n the Monte Carlo models are defned n the followng way (e.g. for the MOS transstor threshold voltage vth): AVT, sm vth = vtnom + delvt + delmat (1) w l where vtnom s the normally dstrbuted nomnal threshold voltage, deltvt N(, σ ) s a global random varable ~ VT descrbng the process varaton (wafer to wafer varaton), delmat ~ N(,1) s a local Gaussan random varable descrbng devce msmatch and s allowed to vary ndependently for any transstor, w and l are the drawn wdth and length of the transstor. The thrd term of the parameter defnton descrbes the geometrc dependence of msmatch correspondng to the Pelgrom law [9], where the slope factor A VT,sm s determned from matchng parameter extracton [4,5]. The dstrbuton functons for the PMOS transstor threshold voltage varaton correspondng to (1) are defned n Table I. TABLE I Monte Carlo modelng of PMOS threshold voltage varaton. vtnom [V] delvt [V] delmat [V] A VT,sm [mvµm] -.76 N(,.3) N(,1) 15 In order to model the process varatons accurately the followng SPICE parameters for the MOS transstors (BSIM3v3) have been defned by random varables derved from the dstrbuton of producton control parameters: vth (threshold voltage), u (moblty), xl (varaton of effectve channel length), xw (varaton of effectve channel wdth), nsub (substrate dopng), tox (oxde- thckness), cgd/s/bo (gate-dran/source/bulk overlap capactances), rsh (dffuson resstance) and cj (juncton capactance). The calculaton of the SPICE parameter dstrbuton uses a backward error propagaton method smlar to [3] to model the varaton of process parameters based on SPICE smulaton of control parameters and numercal computaton of senstvtes. Furthermore, correlatons of SPICE parameters are defned reflectng the statstcal nteracton of process control parameters. The Monte Carlo models are mplemented as specal devce model sectons for usage wthn the SPICE smulator Spectre [1] and the DFY tool WCkeD [6,7,8,1]. The yeld analyss of the power-on reset cell s performed usng the Monte Carlo smulaton feature of the DFY tool WCkeD [8]. The orgnal desgn had an overall yeld of 72 % wthn the allowed temperature range (T= 4 C to T= +85 C) where the yeld at the crtcal operatng pont (T= 4 C) was 73 % whereas V TRIG,mn =2.6V and V TRIG,max =4.1V (see Fg. 4). 45 4 35 3 25 2 15 1 5 VRISE, Mean: 3.9885 Std. Dev.:.21256 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 Fg. 4. Monte Carlo smulaton: Hstogram of the threshold voltage V TRIG for the orgnal desgn at T= 4 C, Yeld=73%. Specfcaton (sold lne) and smulated 3σ lmts (dashed lne). The Monte Carlo smulaton at the crtcal operatng pont (T=-4 C) results n the followng mean and standard devaton for the output threshold voltage V TRIG : µ = 3.98 V, σ =.212 V. 3.2 Senstvty Computaton The subsequent senstvty computaton provdes nformaton concernng the senstvtes wth respect to process parameters. The man contrbutors concernng the varance of V TRIG are determned by: the process varaton of the PMOS threshold voltage delvt_p (59% relatve nfluence) the process varaton of the NMOS threshold voltage delvt_n (21 % relatve nfluence) the process varaton of the effectve channel wdth del_xw (18 % relatve nfluence). The bggest nfluence s gven by the varaton of the PMOS threshold voltage where the senstvty wth respect to V TRIG has been determned from the Monte Carlo analyss assumng a standard devaton of σ = mv (see Table I) by: S V 3 dvtrig = =.188 V / σ delvt _ p TRIG Count = S VRISE (V) =.188V /.3V = 6.3 Ths nformaton s used to calculate an approprate shft of the PMOS threshold voltage n order to ncrease the yeld of the orgnal desgn durng producton. (2) (3)
The senstvty analyss and optmsaton features of the DFY tool WCkeD are based on an analytcal model of the crcut behavour as descrbed n the remander of ths paragraph. Three parameter spaces are dstngushed: The desgn parameters denoted by the vector d (e.g. drawn lengths and wdths of transstors), the operatng parameters (e.g. temperature or supply voltage) combned n the vector θ and the statstcal parameters s descrbng the global and local process varaton (1). The statstcal parameters can always be normalzed to be Gaussan dstrbuted wth mean value s = and standard devaton σ = 1 for each component. As far as the desgn propertes are concerned, the components of the vector f ( d,s s, θ) are the specfed performances of the desgn (the threshold voltage V TRIG n ths example) and the specfcaton vector f descrbes the upper and/or lower bounds for all performances. A crcut meets all specfcatons f the expresson f ( d,s s,θ) < holds true. b f b Fnally, the yeld Y d,s ) s the percentage of manufactured ( devces whch meet all specfcatons over the whole range of operatng condtons and can be expressed as Y ( d, s ) = ( ) d pdf s s s { s f(d,s s, θ ) < fb θ } Detals on the computaton of ths ntegral can be found n [6]. Senstvty analyss s supported both for the performances (devaton of a performance wth respect to a parameter) and the yeld (devaton of the expresson for yeld wth respect to a desgn parameter or the mean value of a statstcal parameter). In the present nvestgaton senstvty analyss of the performance wth respect to the statstcal process parameters has been appled. 4 Yeld Enhancement by Shft of Process Parameters As seen from Fg. 4 the 3σ lmt of V TRIG at T=-4 C (4.6 V) s 5 mv too hgh wth respect to the specfcaton (upper lmt V TRIG =4.1V). Snce the PMOS threshold voltage s the man contrbutor to the varaton of V TRIG an approprate shft of the typcal PMOS transstor threshold to decrease V TRIG by 5 mv can be calculated from the senstvty S (2) by (4) 5 = 6.3 = 79mV (5) Therefore, an ncrease of the nomnal threshold voltage by +79mV (=-.76 shfted to =-.68V) s able to lower the maxmum output by 5 mv and enables a 3σ desgn for the gven operatng pont. The ncrease of the yeld s verfed by Monte Carlo smulaton assumng shfted process parameters vtnom=-.68v n (1) and results n the followng mean and standard devaton for the output threshold V TRIG : µ = 3.7V, σ =. 21V and a smulated overall yeld of 98 %. The shft of the nomnal threshold voltage has been mplemented for the gven producton process by a correspondng decrease of the PMOS threshold adjust mplant dose (mplant dose was changed from 3.4e12/cm 2 to 3.5e12/cm 2 wth an mplant energy of 7keV). The mplemented soluton led to a yeld ncrease of 15% for the orgnal desgn durng producton. 5 Yeld Optmsaton by Desgn Centerng For the ntended re-desgn of the power-on reset cell the yeld optmzaton feature of the DFY tool WCkeD s used. Ths specal program optmzes desgn parameters for hghest yeld. The yeld optmzaton s based on the worst case dstance n the statstcal parameter space. The worst case dstance n the statstcal parameter space s best explaned on the bass of the ntegraton regon of expresson (4). The worst-case pont s wc s the set of values of the process parameter vector that s most lkely to occur durng the manufacturng among all process parameter vectors that make the crcut volate one specfcaton. For a gven assgnment of the parameter vector d, the worst case pont s wc for specfcaton s defned as: T swc T ( d) = argmn{( s s )( s s) f ( d, s s) = f The worst-case dstance s wc -s between the worst-case pont to the nomnal value determnes the yeld of performance no..: a large value of s wc -s ndcates a hgh yeld and vce versa. The automatc yeld optmzaton algorthm of WCkeD estmates yeld by worst case ponts. Ths enables a calculaton of the senstvty of yeld regardng desgn parameters, whch s not possble from a Monte Carlo smulaton. By ths yeld optmzaton, a new soluton vector d was found that resulted n a yeld ncrease of more than 2 % by changng only 3 transstor parameters: the channel lengths of two PMOS load transstors (L4 and L13) and of an NMOS transstor (L7). The values of the transstor parameters cann be seen n Table II. The moderate area ncrease of the optmzed desgn enables an easy replacement of the orgnal cell wthout ncreasng the orgnal layout area reserved for ths block. The yeld ncrease was verfed performng a Spectre-Monte Carlo smulaton wthn the Cadence [1] desgn envronment (see Fg. 6). b } ( 6)
M4 M4 Fg. 5. Layout of the orgnal desgn (upper) and the optmsed desgn (lower ). The total computaton tme for the yeld optmzaton was one hour usng a parallel LSF-based smulaton envronment and 5 servers. Monte Carlo Smulaton at 4 C TABLE II Yeld optmsaton results for power-on reset cell. Orgnal Desgn Y=73% µ=3.98v σ=212mv Optmsed Desgn Y= 98% µ=3.7v σ=191mv Total Yeld Y=72% Y=93% Desgn Parameters Orgnal Desgn Optmsed Desgn L7=6µm L4=L13=75µm Area=255µm² L7=7µm L4=L13=15µm Area=2446µm² The yeld ncrease was verfed performng a Spectre-Monte Carlo smulaton wthn the Cadence [1] desgn envronment (see Fg. 6 and Table III). process wndow verfcaton s used. The wafers of a specfc producton lot are processed n dfferent ways and a producton splt reflectng dfferent corner condtons s appled (group 1: typcal mean, group 2: worst-case-power, group 3: worst-case-speed, group 4: worst-case-one and group 5: worst-case-zero). The worst-case-condtons for the NMOS and PMOS threshold voltage are spannng a rectangular area over the allowed specfcaton (NMOS:.68V to.84v and PMOS: -.68V to -.88V). The groups are realzed by varyng the threshold adjust mplant dose for NMOS and PMOS transstors. A good yeld over all splt groups s equvalent to a long-term producton stablty. For the power-on reset cell the defned process wndow s especally sutable to verfy the robustness snce the varaton of V TRIG manly reles on the PMOS threshold varaton as determned by the senstvty analyss. Durng electrcal wafer sort, the threshold voltage V TRIG s montored at T=35 C and a test lmt V guard =3.9 V s mplemented n order to screen out bad parts at low temperature (parts wth V TRIG > 4.3 V at 4 C). Ths guard band lmt s mplemented to avod a low temperature sort and s calculated from the lnear temperature slope of the reset voltage (TK = -5.8 mv/k). The orgnal desgn had a measured mean value µ = 3.73V and a standard devaton σ =.3V for all splt groups. The total yeld of the orgnal desgn s 69 % (n= 493 out of 66 parts) and close to the Monte Carlo smulaton results (72 %). As expected from the senstvty analyss the most crtcal corner for ths desgn s the worst-case-speed corner (large magntude of PMOS threshold and NMOS threshold voltage). For the orgnal desgn, all parts are out of specfcaton for the worst-casespeed corner (see Fg. 7). worst case speed VRISE, Mean: 3.7262 Std. Dev.:.19158 45 4 35 V guard 3 Count 25 2 15 VTRIG (V) worst case power 1 5 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 Wafer Number VRISE (V) Fg. 6. Monte Carlo smulaton: Hstogram of the threshold V TRIG for the optmsed desgn at worst-case-operatng pont T=-4 C, Yeld=98%. Specfcaton (sold lne) and 3σ lmts (dashed lne). 6 EXPERIMENTAL RESULTS For expermental verfcaton the yeld of the optmsed desgn s compared to the yeld of the orgnal desgn by producton measurements on wafer level (wafer sort). Therefore, a Fg. 7. Orgnal desgn: Hstogram and Box Plots for measured reset voltage and dfferent splt groups. Total measured yeld s 69 %. Wafer test lmt V guard= 3.9V. As predcted by smulaton a clear mprovement of producton yeld can be seen for the optmsed desgn (see Fg. 8) wth a measured mean value µ=3.38v and a standard devaton σ=.23v. For the optmsed desgn all measured parts le below the crtcal producton lmts (V guard = 3.9V) and the yeld s 1%
for all splt groups (n=997 parts). The measured worst-casedstance (sgma to target) ncreased from.6σ for the ntal desgn to 2.3σ for the optmsed desgn at the low temperature corner. V guard determned by smulaton based yeld optmsaton where the goal was to keep the devce area as small as possble and to maxmze the worst-case-dstance. The smulated yeld mprovement (25%) for the optmsed desgn was expermentally proven by process wndow verfcaton. The qualty of the smulaton results heavly reles on the accuracy of SPICE smulaton models (Monte Carlo models) reflectng the global and local varatons of the producton process. VTRIG (V) Wafer Number worst case speed worst case power Fg. 8. Optmsed desgn: Hstogram and Box Plots for measured reset voltage and dfferent splt groups. Total measured yeld s 1 %. Wafer test lmt V guard= 3.9V. Fgure 9 compares the hstogram of the crtcal worst case speed corner for the orgnal (a) and the optmsed desgn (b). For the orgnal desgn all parts are above the test lmt of 3.9V. For the optmsed desgn all parts are below the test lmt wth an addtonal safety margn of 1mV to the guard band. 8 REFERENCES [1] Cadence Affrma TM Analog Crcut Desgn Envronment User Gude, Product Verson 4.4.6, 22. Cadence Desgn Systems. [2] K. Snghal and V. Vsvanathan, Statstcal devce models from worst case fles and electrcal test data, IEEE Transactons on Semconductor Manufacturng, Vol. 12, pp. 47-484, Nov. 1999. [3] C. McAndrew and P. G. Drennan, Unfed Statstcal Modelng for Crcut Smulaton, Techncal Proceedngs of the 22 Internatonal Conference on Modelng and Smulaton of Mcrosystems, Nanotech 22, Vol. 1, pp. 715-718. [4] W. Posch, H. Enchlmar, E. Schrg and G. Rapptsch, Statstcal Modellng of MOS Transstor Msmatch for Hgh-voltage CMOS Processes. Qualty and Relablty Engneerng Internatonal 25, Vol. 21, pp. 477-489. [5] H. Höller, Measurement and Msmatch Modellng n Semconductor Devces, Proceedngs ISCAS 2, Geneva, May 2, IEEE, New York, 2. N o t N o r m a l (a) 4 4 [6] R. Schwenker, F. Schenkel et al., The Generalzed Boundary Curve A Common Method for Automatc Nomnal Desgn and Desgn Centerng of Analog Crcuts, Proceedngs DATE 2 3 3. 2 2 3. 4 4 3. 6 6 3. 8 8 4. 1 N o t N o r m a l I I (b) Fg. 9. Worst case speed corner of the orgnal (a) and the optmsed desgn (b). Test Lmt = 3.9V (sold lne) 7 CONCLUSION 3.9 8 2 3.9 8 2 3 3. 2 3.4 3. 6 3.8 4 1 mv safety margn [7] F. Schenkel, M. Pronath et al., A Fast Method for Identfyng Msmatch-Relevant Transstor Pars, Proceedngs CICC, 21 [8] K. Antrech, J. Eckmueller, H. Graeb, M. Pronath, F. Schenkel, R. Schwenker and S. Zzala. WCkeD: Analog Crcut Synthess Incorporatng Msmatch Proceedngs CICC, 2. [9] M. Pelgrom, A. Dunmajer and A. Welbers: Matchng Propertes of MOS Transstors, IEEE Journal of Sold-State Crcuts, 1989 Vol.24, No. 5: 1433-1439. [1] K. Antrech, J. Eckmueller, H. Graeb, M. Pronath, F. Schenkel, R. Schwenker and S. Zzala. WCkeD: Analog Crcut Synthess Incorporatng Msmatch, Proceedngs CICC, 2. A yeld optmsaton of an IP block (power-on reset cell) was carred out usng automated smulaton based desgn centerng and verfcaton by expermental results. Frst, crtcal process parameters have been determned by senstvty analyss allowng the mprovement of producton yeld (15%) for the ntal desgn by adjustng the PMOS threshold mplant dose. In a second step a new set of desgn parameters was