TECHNICAL DATA Analog Multiplexer Demultiplexer High-erformance Silicon-Gate CMOS The utilize silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. These analog multiplexers/demultiplexers control analog voltages that may vary across the complete power supply range (from V CC to V EE ). The Channel-Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by mea of an analog switch, to the Common Output/Input.When the Enable pin is high, all analog switches are turned off. The Channel-Select and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. Fast Switching and ropagation Speeds Low Crosstalk Between Switches Diode rotection on All Inputs/Outputs Analog ower Supply Range (V CC -V EE )=2.0 to 12.0 V Digital (Control) ower Supply Range (V CC -GND)=2.0 to V Low Noise ORDERING INFORMATION N lastic DW SOIC T A = -55 to 125 C for all packages IN ASSIGNMENT LOGIC DIAGRAM Single-ole, 8-osition lus Common Off FUNCTION TABLE IN 16 =V CC IN 7 = V EE IN 8 = GND Control Inputs ON Enable Select Channels C B A L L L L X0 L L L H X1 L L H L X2 L L H H X3 L H L L X4 L H L H X5 L H H L X6 L H H H X7 H X X X None X = don t care
MAXIMUM RATINGS * Symbol arameter Value Unit V CC ositive DC Supply Voltage (Referenced to GND) (Referenced to V EE ) -0.5 to +7.0-0.5 to +14.0 V EE Negative DC Supply Voltage (Referenced to GND) -7.0 to +0.5 V V IS Analog Input Voltage V EE - 0.5 to V CC +0.5 V V IN Digital Input Voltage (Referenced to GND) -1.5 to V CC +1.5 V I DC Input Current Into or Out of Any in ±25 ma D ower Dissipation in Still Air, lastic DI+ SOIC ackage+ Tstg Storage Temperature -65 to +150 C T L Lead Temperature, 1 mm from Case for 10 Seconds 260 C (lastic DI or SOIC ackage) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - lastic DI: - 10 mw/ C from 65 to 125 C SOIC ackage: : - 7 mw/ C from 65 to 125 C 750 500 V mw RECOMMENDED OERATING CONDITIONS Symbol arameter Min Max Unit V CC ositive Supply Voltage (Referenced to GND) 2.0 V (Referenced to V EE ) 2.0 12.0 V EE Negative DC Supply Voltage (Referenced to GND) - GND V V IS Analog Input Voltage V EE V CC V V IN Digital Input Voltage (Referenced to GND) GND V CC V * V IO Static or Dynamic Voltage Across Switch - 1.2 V T A Operating Temperature, All ackage Types -55 +125 C t r, t f Input Rise and Fall Time (Channel Select or Enable Inputs) V CC =2.0 V V CC = V V CC = V * For voltage drops across the switch greater than 1.2 V (switch on), excessive V CC current may be drawn; i. e., the current out of the switch may contain both V CC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. 0 0 0 1000 500 400 This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V IN and V OUT should be cotrained to the range indicated in the Recommended Operating Conditio.. Unused digital input pi must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused Analog I/O pi may be left open or terminated.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V EE =GND, Except Where Noted V CC Guaranteed Limit Symbol arameter Test Conditio V 25 C to -55 C V IH V IL I IN I CC Minimum High-Level Input Voltage, Channel-Select or Enable Inputs Maximum Low -Level Input Voltage, Channel-Select or Enable Inputs Maximum Input Leakage Current, Channel-Select or Enable Inputs Maximum Quiescent Supply Current (per ackage) R ON = er Spec 2.0 R ON = er Spec 2.0 V IN =V CC or GND, V EE =- V Channel Select = V CC or GND Enable = V CC or GND V IS = V CC or GND V IO = 0 V V EE = GND V EE = - DC ELECTRICAL CHARACTERISTICS Analog Section 1.5 3.15 4.2 0.3 0.9 1.2 85 C 1.5 3.15 4.2 0.3 0.9 1.2 125 C 1.5 3.15 4.2 0.3 0.9 1.2 Unit ±0.1 ±1.0 ±1.0 μa 2 8 20 40 160 V CC V EE Guaranteed Limit Symbol arameter Test Conditio V V 25 C to -55 C R ON Maximum ON Resistance V IS = V CC or V EE I S 2.0 ma(figure 1) V IS = V CC or V EE (Endpoints) I S 2.0 ma(figure 1) ΔR ON I OFF I ON Maximum Difference in ON Resistance Between Any Two Channels in the Same ackage Maximum Off- Channel Leakage Current, Any One Channel Maximum Off- Channel Leakage Current, Common Channel Maximum On- Channel Leakage Current, Channel to Channel V IS = 1/2 (V CC - V EE ) I S 2.0 ma V IO = V CC - V EE Switch Off (Figure 2) V IO = V CC - V EE Switch Off (Figure 3) Switch to Switch = V CC - V EE (Figure 4) 0.0 - - 0.0 - - 0.0 - - 190 120 100 150 100 30 12 10 85 C 240 150 125 190 125 100 35 15 12 125 C 2 170 140 230 140 115 40 18 14 V V μa Unit - 0.1 0.5 1.0 μa - 0.2 2.0 4.0-0.2 2.0 4.0 μa Ω Ω
AC ELECTRICAL CHARACTERISTICS (C L =50pF,Input t r =t f = ) V CC Symbol arameter V 25 C to -55 C t LH, t HL t LH, t HL t LZ, t HZ t ZL, t ZH C IN C I/O Maximum ropagation Delay, Channel-Select to Analog Output (Figures 8 and 9) Maximum ropagation Delay, Analog Input to Analog Output (Figures 10 and 11) Maximum ropagation Delay, Enable to Analog Output (Figures 12 and 13) Maximum ropagation Delay, Enable to Analog Output (Figures 12 and 13) 2.0 2.0 2.0 2.0 370 74 63 60 12 10 290 58 49 345 69 59 Guaranteed Limit 85 C 125 C Unit 465 93 79 75 15 13 364 73 62 435 87 74 550 110 94 90 18 15 430 86 73 515 103 87 Maximum Input Capacitance, Channel-Select or Enable Inputs - 10 10 10 pf Maximum Capacitance - 35 35 35 pf Analog I/O All Switches Off Common O/I - 130 130 130 Feedthrough - 1.0 1.0 1.0 C D ower Dissipation Capacitance (er ackage) (Figure 14) Used to determine the no-load dynamic power coumption: D =C D V CC 2 f+i CC V CC Typical @25 C,V CC =5.0 V, V EE =0 V 45 pf
ADDITIONAL ALICATION CHARACTERISTICS (GND = 0.0 V) V CC V EE Limit * Symbol arameter Test Conditio V V 25 C Unit BW Maximum On- Channel Bandwidth or Minimum Frequency Respoe (Figure 5) - Off-Channel Feedthrough Isolation (Figure 6) - Feedthrough Noise, Channel Select Input to Common O/I (Figure 7) THD f in =1 MHz Sine Wave Adjust f in Voltage to Obtain 0 dbm at V OS Increase f in Frequence Until db Meter Reads -3 db R L =50 Ω, C L =10 pf f in = Sine Wave Adjust f in Voltage to Obtain 0 dbm at V IS f in = 10 khz, R L =600 Ω, C L =50 pf f in = 1.0 MHz, R L =50 Ω, C L =10 pf V IN 1 Mhz Square Wave (t r = t f = 6 ) Adjust R L at Setup so that I S = 0 A Enable = GND R L =600 Ω, C L =50 pf R L =10 Ω, C L =10 pf 0 0 0 0 0 0 0 0 0 0 Total Harmonic f in = 1 khz, R L =10 kω, C L =50 pf Distortion THD = THD Measured - THD Source (Figure 15) V IS =4.0 V sine wave V IS =8.0 V sine wave V IS =11.0 V sine wave * Limits not tested. Determined by design and verified by qualification. 0 0 - -0-0 - -0-0 - -0-0 - -0-0 - -0-0 - -0-0 -50-50 -50-40 -40-40 25 105 135 35 145 190 0.10 0.08 0.05 MHz db mv % Figure 1. On Resistance Test Set-Up
Figure 2. Maximum Off Channel Leakage Current, Any One Channel, Test Set-U Figure 3. Maximum Off Channel Leakage Current, Common Channel, Test Set-U Figure 4. Maximum On Channel Leakage Current, Channel to Channel, Test Set-U * Includes all probe and jig capacitance. Figure 5. Maximum On Channel Bandwidth, Test Set-U * Includes all probe and jig capacitance. * Includes all probe and jig capacitance. Figure 6. Off Channel Feedthrough Isolation, Test Set-U Figure 7.Feedthrough Noise, Channel Select to Common Out, Test Set-U
Figure 8. Switching Weveforms * Includes all probe and jig capacitance. Figure 9. Test Set-U, Channel Select to Analog Out Figure 10. Switching Weveforms * Includes all probe and jig capacitance. Figure 11. Test Set-U, Analog In to Analog Out Figure 12. Switching Weveforms Figure 13. Test Set-U, Enable to Analog Out
Figure 14. ower Dissipation Capacitance, Test Set-Up * Includes all probe and jig capacitance Figure 15. Total Harmonic Distortion, Test Set-U EXANDED LOGIC DIAGRAM
N SUFFIX LASTIC DI (MS - 001BB) 16 1 A G F 0.25 (0.010) M T NOTES: 1. Dimeio A, B do not include mold flash or protrusio. Maximum mold flash or protrusio 0.25 mm (0.010) per side. 9 8 D N B -T- C -T- K SEATING LANE M L H J Dimeion, mm Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 G H 2.54 7.62 J 0 10 K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AC) H 16 1 D G A 0.25 (0.010) M T C M 9 8 B K C SEATING LANE Symbol MIN MAX A 9.8 10 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 J 0 8 NOTES: K 0.1 0.25 1. Dimeio A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side 5.8 6.2 for A; for B 0.25 mm (0.010) per side. R 0.25 0.5 J R x 45 F M G H Dimeion, mm 1.27 5.72