128K x 8 Static RAM Features High speed t AA = 12 ns Low active power 495 mw (max. 12 ns) Low CMOS standby power 55 mw (max.) 4 mw 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with,, and options Functional Description [1] The / is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable ( ), an active HIGH Chip Enable ( ), an active LOW Output Enable (), and three-state drivers. Writing to the device is accomplished by taking Chip Enable One ( ) and Write Enable () inputs LOW and Chip Enable Two ( ) input HIGH. Data on the eight I/O pins (I/O 0 through I/O 7 ) is then written into the location specified on the address pins (A 0 through A 16 ). Reading from the device is accomplished by taking Chip Enable One ( ) and Output Enable () LOW while forcing Write Enable () and Chip Enable Two ( ) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O 0 through I/O 7 ) are placed in a high-impedance state when the device is deselected ( HIGH or LOW), the outputs are disabled ( HIGH), or during a write operation ( LOW, HIGH, and LOW). The is available in standard 400-mil-wide SOJ and 32-pin TSOP type I packages. The is available in a 300-mil-wide SOJ package. The and are functionally equivalent in all other respects. Logic Block Diagram A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 ROW DECODER INPUT BUFFER 512x256x8 ARRAY COLUMN DECODER A9 A10 A11 A12 A13 A 14 A 15 A16 SENSE AMPS POR DOWN Pin Configurations Note: 1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document #: 001-06430 Rev. ** Revised February 1, 2006 I/O 0 I/O 1 I/O 2 NC A 16 A 14 A 12 A7 A6 A5 A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 GND SOJ Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 32 31 30 29 28 27 26 25 24 23 22 21 20 14 19 15 18 16 17 V CC A 15 A 13 A 8 A 9 A 11 A 10 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O A 3 11 1 32 A 9 2 31 A 8 3 30 I/O 4 A 13 4 29 5 28 6 27 I/O 5 A 15 7 TSOP I 26 V CC 8 Top View 25 NC 9 (not to scale) 24 I/O 6 A 16 10 23 A 14 11 22 A 12 12 21 I/O 7 A 7 13 20 A 6 14 19 A 5 15 18 A 4 16 17 A 10 CE I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 GND I/O 2 I/O 1 I/O 0 A 0 A 1 A 2 A 3
Selection Guide 7C109B-12 7C1009B-12 7C109B-15 7C1009B-15 7C109B-20 7C1009B-20 Unit Maximum Access Time 12 15 20 ns Maximum Operating Current 90 80 75 ma Maximum CMOS Standby Current 10 10 10 ma L 2 2 2 ma Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature... 65 C to +150 C Ambient Temperature with Power Applied... 55 C to +125 C Supply Voltage on V CC to Relative GND [2]... 0.5V to +7.0V DC Voltage Applied to Outputs in High Z State [2]... 0.5V to V CC + 0.5V DC Input Voltage [2]... 0.5V to V CC + 0.5V Current into Outputs (LOW)... 20 ma Static Discharge Voltage... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current... >200 ma Operating Range Ambient Range Temperature V CC Commercial 0 C to +70 C 5V ± 10% Industrial 40 C to +85 C 5V ± 10% Electrical Characteristics Over the Operating Range 7C109BN-12 7C1009BN-12 7C109BN-15 7C1009BN-15 7C109BN-20 7C1009BN-20 Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Unit V OH Output HIGH Voltage V CC = Min., I OH = 4.0 ma 2.4 2.4 2.4 V V OL Output LOW Voltage V CC = Min., I OL = 8.0 ma 0.4 0.4 0.4 V V IH Input HIGH Voltage 2.2 V CC + 0.3 2.2 V CC + 0.3 2.2 V CC + 0.3 V V IL Input LOW Voltage [2] 0.3 0.8 0.3 0.8 0.3 0.8 V I IX Input Leakage GND < V I < V CC 1 +1 1 +1 1 +1 µa Current I OZ Output Leakage GND < V I < V CC, 5 +5 5 +5 5 +5 µa Current Output Disabled I OS Output Short V CC = Max., V OUT = GND 300 300 300 ma Circuit Current [3] I CC I SB1 I SB2 Capacitance [4] V CC Operating Supply Current V CC = Max., I OUT = 0 ma, 90 80 75 ma f = f MAX = 1/t RC Automatic CE Max. V CC, > V IH Power-Down Current or < V IL, V IN > V IH or TTL Inputs V IN < V IL, f = f MAX Automatic CE Max. V CC, Power-Down Current > V CC 0.3V, CMOS Inputs or < 0.3V, V IN > V CC 0.3V, or V IN < 0.3V, f = 0 45 40 30 ma 10 10 10 ma L 2 2 2 ma Parameter Description Test Conditions Max. Unit C IN Input Capacitance T A = 25 C, f = 1 MHz, 9 pf C OUT Output Capacitance V CC = 5.0V 8 pf Notes: 2. Minimum voltage is 2.0V for pulse durations of less than 20 ns. 3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06430 Rev. ** Page 2 of 9
AC Test Loads and Waveforms R1 480Ω 5V OUTPUT 30 pf INCLUDING JIG AND SCOPE (a) R1 480Ω 5V OUTPUT R2 5 pf 255Ω INCLUDING JIG AND SCOPE (b) R2 255Ω 3.0V GND 3 ns 10% ALL INPUT PULSES 90% 90% 10% 3 ns Equivalent to: OUTPUT THÉ VENIN EQUIVALENT 167Ω 1.73V Switching Characteristics [5] Over the Operating Range 7C109BN-12 7C1009BN-12 7C109BN-15 7C1009BN-15 7C109BN-20 7C1009BN-20 Parameter Description Min. Max. Min. Max. Min. Max. Unit Read Cycle t RC Read Cycle Time 12 15 20 ns t AA Address to Data Valid 12 15 20 ns t OHA Data Hold from Address Change 3 3 3 ns t ACE LOW to Data Valid, HIGH to Data Valid 12 15 20 ns t D LOW to Data Valid 6 7 8 ns t LZ LOW to Low Z 0 0 0 ns t HZ HIGH to High Z [6, 7] 6 7 8 ns t LZCE LOW to Low Z, HIGH to Low Z [7] 3 3 3 ns t HZCE HIGH to High Z, LOW to High Z [6, 7] 6 7 8 ns t PU LOW to Power-Up, HIGH to Power-Up 0 0 0 ns t PD HIGH to Power-Down, LOW to 12 15 20 ns Power-Down Write Cycle [8] t WC Write Cycle Time [9] 12 15 20 ns LOW to Write End, HIGH to Write End 10 12 15 ns t AW Address Set-Up to Write End 10 12 15 ns t HA Address Hold from Write End 0 0 0 ns t SA Address Set-Up to Write Start 0 0 0 ns t P Pulse Width 10 12 12 ns t SD Data Set-Up to Write End 7 8 10 ns t HD Data Hold from Write End 0 0 0 ns t LZ HIGH to Low Z [7] 3 3 3 ns t HZ LOW to High Z [6, 7] 6 7 8 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I OL /I OH and 30-pF load capacitance. 6. t HZ, t HZCE, and t HZ are specified with a load capacitance of 5 pf as in part (b) of AC Test Loads. Transition is measured ±500 mv from steady-state voltage. 7. At any given temperature and voltage condition, t HZCE is less than t LZCE, t HZ is less than t LZ, and t HZ is less than t LZ for any given device. 8. The internal write time of the memory is defined by the overlap of LOW, HIGH, and LOW. and must be LOW and HIGH to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 ( controlled, LOW) is the sum of t HZ and t SD. Document #: 001-06430 Rev. ** Page 3 of 9
Data Retention Characteristics Over the Operating Range (Low Power version only) Parameter Description Conditions Min. Max Unit V DR V CC for Data Retention No input may exceed V CC + 0.5V 2.0 V I CCDR Data Retention Current V CC = V DR = 2.0V, > V CC 0.3V or < 0.3V, 150 µa t CDR Chip Deselect to Data Retention Time V IN > V CC 0.3V or V IN < 0.3V 0 ns t R Operation Recovery Time 200 µs Data Retention Waveform DATA RETENTION MODE V CC 4.5V V DR > 2V 4.5V t CDR t R CE Switching Waveforms [10, 11] Read Cycle No. 1 t RC t OHA t AA DATA OUT PREVIOUS DATA VALID DATA VALID [11, 12] Read Cycle No. 2 ( Controlled) t RC t ACE t HZ thzce t D DATA OUT t LZ HIGH IMPEDANCE DATA VALID HIGH IMPEDANCE V CC SUPPLY CURRENT t LZCE t PU 50% t PD 50% I CC I SB Notes: 10. Device is continuously selected., = V IL, = V IH. 11. is HIGH for read cycle. 12. Address valid prior to or coincident with transition LOW and transition HIGH. Document #: 001-06430 Rev. ** Page 4 of 9
Switching Waveforms (continued) Write Cycle No. 1 ( or Controlled) [13, 14] t WC t SA t AW t P t HA t SD t HD DATA I/O DATA VALID [13, 14] Write Cycle No. 2 ( Controlled, HIGH During Write) t WC t AW t HA t SA t P t SD t HD DATA I/O NOTE 15 DATA IN VALID t HZ Notes: 13. Data I/O is high impedance if = V IH. 14. If goes HIGH or goes LOW simultaneously with going HIGH, the output remains in a high-impedance state. 15. During this period the I/Os are in the output state and input signals should not be applied. Document #: 001-06430 Rev. ** Page 5 of 9
Switching Waveforms (continued) Write Cycle No. 3 ( Controlled, LOW) [14] t WC t AW t HA t SA t P t SD t HD DATA I/O NOTE 15 DATA VALID t HZ t LZ Truth Table I/O 0 I/O 7 Mode Power H X X X High Z Power-Down Standby (I SB ) X L X X High Z Power-Down Standby (I SB ) L H L H Data Out Read Active (I CC ) L H X L Data In Write Active (I CC ) L H H H High Z Selected, Outputs Disabled Active (I CC ) Document #: 001-06430 Rev. ** Page 6 of 9
Ordering Information Speed (ns) Ordering Code Package Diagram Package Type Operating Range 12-12VC 51-85032 32-Lead (400-Mil) Molded SOJ Commercial -12VC 51-85031 32-Lead (300-Mil) Molded SOJ -12ZC 51-85056 32-Lead TSOP Type I -12ZXC 51-85056 32-Lead TSOP Type I (Pb-free) 15 L-15VC 51-85032 32-Lead (400-Mil) Molded SOJ Commercial -15VC 51-85032 32-Lead (400-Mil) Molded SOJ -15VC 51-85031 32-Lead (300-Mil) Molded SOJ -15ZC 51-85056 32-Lead TSOP Type I -15ZXC 51-85056 32-Lead TSOP Type I (Pb-free) -15VI 51-85032 32-Lead (400-Mil) Molded SOJ Industrial -15VI 51-85031 32-Lead (300-Mil) Molded SOJ 20-20VC 51-85032 32-Lead (400-Mil) Molded SOJ Commercial -20VC 51-85031 32-Lead (300-Mil) Molded SOJ -20VI 51-85032 32-Lead (400-Mil) Molded SOJ Industrial -20ZC 51-85056 32-Lead TSOP Type I Commercial -20ZXC 51-85056 32-Lead TSOP Type I (Pb-free) Please contact local sales representative regarding availability of these parts Package Diagrams 28-Lead (400-Mil) Molded SOJ (51-85032) PIN 1 I.D 14 1.435.395.445.405 DIMENSIONS IN INCHES MIN. MAX. 15 28.720.730 SEATING PLANE.050 TYP..015.020.026.032.025 MIN..128.148 0.004.360.380.007.013 51-85032-*B Document #: 001-06430 Rev. ** Page 7 of 9
Package Diagrams (continued) NOTE : 28-Lead (300-Mil) Molded SOJ (51-85031) 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DS NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX. PIN 1 ID A DETAIL EXTERNAL LEAD DESIGN 14 1 15 28 0.697 0.713 0.291 0.300 0.330 0.350 SEATING PLANE 0.026 0.013 0.032 0.019 0.014 0.020 OPTION 1 OPTION 2 0.050 TYP. A 0.025 MIN. 0.120 0.140 0.004 0.262 0.272 0.007 0.013 51-85031-*C 32-Lead TSOP I (8x20 mm) (51-85056) 51-85056-*D All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06430 Rev. ** Page 8 of 9 Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Document History Page Document Title: / 128K x 8 Static RAM Document Number: 001-06430 Issue Orig. of REV. ECN NO. Date Change Description of Change ** 423847 See ECN NXR New Data Sheet Document #: 001-06430 Rev. ** Page 9 of 9