A Cobined Multipulse-Multilevel Inverter Suitle For High Power Applications B. Geethalakshi d P. Djay Abstract Power electronic devices are finding increased applications in the trsforation of electrical energy into useful fors, especially at higher power levels. The recent trend in power electronic converters is to switch the power seiconductor devices in power odulators at increased frequencies with a view to iniize haronics, enhce power quality d regulate the output voltage. This paper is aied to present the design of high power inverter topology caple of producing a near sinusoidal ac voltage with inial haronic distortion which enles its use in high power applications. The alytical expressions for the proposed inverter output voltages using Fourier alysis have been obtained. ector diagras are drawn to clearly illustrate the echis of haronic ccellation in the proposed ultipulse-ultilevel inverter topology. The coplete digital siulation of the proposed SI is perfored using MATLAB/Siulink d the siulation results closely agreed with the alytical results. Index Ters Multi-pulse inverter, Multi-level inverter, Phase shifting trsforer, Total Haronic Distortion, oltage source inverter. Inverters are generally used in a host of applications that include varile speed drive, uninterruptible power supplies, flexible AC trsission systes (FACTS), high voltage dc trsission (HDC) systes, active filters, etc., The output voltage wavefors of ideal inverters should be sinusoidal. But, the wavefors of practical inverters are non-sinusoidal d contain certain haronics. Square wave or quasi-square wave voltages ay be acceptle for low- d ediu-power applications. However, low distorted sinusoidal wavefors are required for high power applications especially when they are used in power syste applications. Appropriate voltage source inverter circuits have to be developed in order to integrate power converter circuits into power systes. The haronics generated on the ac side of the power inverter circuits greatly influence the power quality of the trsission syste. Hence, in the present work, attept is ade to propose a suitle inverter configuration useful for high power applications. II. EOLUTION OF HIGH POWER INERTERS I. INTRODUCTION The progress of a nation is assessed by its econoic growth, industrial developent besides technological advceents. The per capita consuption of electrical energy is treated as a easure to evaluate the overall progress. It is iperative that the existing resources are fully utilized before venturing to look for alternatives, in the present energy crisis scenario. However, it is equally iportt to realize the rapid depletion of energy sources d conteplate easures to augent its sustainility. The field of power electronics has witnessed treendous developent in recent ties. The advent of new power controlled devices has contributed significtly to enhced perforce of the existing power converters. The birth of innovative converter topologies has paved the way for further iproving the overall power quality. It has contributed to build sophisticated utilities d enle precise control of flow of power over the trsission lines. Muscript received May 14, 2009. B.Geethalakshi is with the Departent of Electrical d Electronics Engineering, Pondicherry Engineering College, Pondicherry, India (e-ail: bgeethalakshi_pec@yahoo.co.in). P.Djay is with the Departent of Electronics d Counication Engineering, Pondicherry Engineering College, Pondicherry, India. (Corresponding Author Phone:9443768716; fax:04132655101; eail-pdjay@rediffail.co). The traditional two-level SI produces a square wave output as it switches the direct voltage source on d off. However for high voltage applications, a near sinusoidal ac voltage with inial haronic distortion is required. In order to realise higher voltages, each ain switch of the 2-level inverter is fored by connecting y seiconductor devices in a series/parallel fashion. It is essential that with this arrgeent, the electrical d theral characteristics of the series d/or parallel connected seiconductor devices should be atched [1]. In response to the growing ded for high power inverter units, ultipulse inverters (MPI) have drawn increased interest in the field of research d industry [2-4]. A ultipulse inverter generates a staircase wave closely resebling a sine wave by connecting nuber of identical three-phase inverter bridges through phase shifting trsforers (PST). The high power STATCOM coissioned at Sulliv substation, United States used 48-pulse voltage source inverter in order to obtain higher operating voltages with less haronic content [6]. The key proble with the ultipulse inverter is the requireent of agnetic interfaces constituted by coplex zig-zag phase shifting trsforers which treendously increases the cost of the coplete syste [1]. An attractive alternative to the ultipulse inverter is the ultilevel inverter (MLI) [6-11] which has evolved in three different topologies naely diode claped ultilevel inverter 257
International Journal of Coputer d Electrical Engineering, ol. 2, No. 1, April, 2010 (DCMLI), [6, 7] flying capacitor ultilevel inverter (FCMLI) [8] d cascaded ultilevel inverter (CMLI) [9, 10]. Aong the three configurations, the CMLI with a separate dc capacitor is widely accepted for applications in high power drives d utility systes due to its odularized circuit layout d sufficiently high operating voltages [11]. Though the basic concept of the CMLI has existed over ore th two decades, it was not fully realized until F.Z.Peng d J.S.Lai [9] patented it. The CMLI consists of a nuber of H-bridge power conversion cells with each cell supplied by isolated source on the dc side d series connected on the ac side so as to produce a staircase wavefor. A preiu quality output wavefor c be achieved with a sufficiently high nuber of voltage levels. However, the nuber of voltage levels is liited due to control coplexity d cost. Besides, a large nuber of dc capacitors are required whose voltages ust be balced in order to avoid over-voltages on y particular link. The critical review of literature shows neither ultipulse inverter nor ultilevel inverter is useful on their own. A hybrid inverter topology incorporating the advtages of both MPI d MLI will be attractive. In the present work it is proposed to build up a forty eight pulse inverter topology through the twenty four pulse configuration in which each individual two level inverters are converted to 3-level diode claped structures. This new topology enjoys the benefits of both the MPI d MLI configurations d is referred as cobined ultipulse-ultilevel inverter topology. The haronic perforce of this inverter topology is evaluated through MATLAB based siulation. It estlishes that this structure alost offers the sae response as that of a forty eight pulse inverter in respect of THD. Fig.1 Cobined ultipulse-ultilevel inverter In this configuration the nuber of PST requireent is reduced to half of that needed in 48-pusle operation. Though the configuration is siilar to a 24-pulse inverter, it provides very less THD as that of the 48-pulse inverter. This is possible by selectively eliinating the 23 rd d 25 th haronic coponents through the appropriate selection of the conduction gle () of the individual three-level inverter units. TABLE I PHASE DISPLACEMENT FOR THE COMBINED Coupling trsforer MULTIPULSE-MULTILEEL INERTER Gate pulse pattern Phase shifting trsforer Y-Y +7.5-7.5 Δ-Y -22.5-7.5 Y-Y -7.5 +7.5 Δ-Y -37.5 +7.5 III. PROPOSED INERTER TOPOLOGY The proposed configuration shown in Fig.1 is obtained by cobining four three-level diode claped ultilevel inverters with adequate phase shifts between the. The voltages generated by each of the three level inverters are applied to the secondary windings of four different PSTs. Two of the are Y-Y trsforers with a turns ratio of 11 d the reaining two are -Y trsforers with a turns ratio of 13. The priary windings of the PSTs are connected in series d the proper pulse pattern as tulated in Tle I is aintained so that the fundaental coponents of the individual 3-level inverters are added in phase on the priary side. Each unit in the proposed structure is a diode claped three-level inverter configuration as shown in Fig.2. The dc-bus voltage is split into three levels by two series connected bulk capacitors, C 1 d C 2. The output voltage v has three states naely dc /2, 0 d dc /2 when the switch pairs S 1 & S 2, S 2 & S 1 d S1 & S 2 are switched ON respectively. In general the conduction gle of the three- level inverter is chosen as 1 σ = 180 1 - (1) where is the haronic coponent which is to be eliinated. 258
where 4 2 DC 3 = sin t+ d( t) + DC sin t+ d( t) π 2 6 6 2 2 4 DC σ π = sin cos π 2 6 (6) (7) Fig.2 Diode claped 3-level inverter I. HARMONIC ANALYSIS The phase-to-phase voltage d the phase-to-neutral voltage of a single three level diode claped ultilevel inverter with conduction gle are described in Fig.3. Fig.3 Phase d line voltages of 3-level inverter Carrying out the Fourier alysis of the inverter output voltage, the instteous phase-to-neutral voltage is expressed as: v t = sin ωt (2) =1 where 4 DC = sinωt d(ωt) π 2 2 2 (3) 2DC π - σ = cos (4) π 2 Siilarly the instteous phase-to-phase voltage is expressed as π v t = sin ωt + =1 6 (5) The voltages v bc (t) d v ca (t) exhibit a siilar pattern except that they are phase shifted by 120 d 240 respectively. Siilarly the phase voltages v bn (t) d v cn (t) are also phase shifted by 120 d 240 respectively. It contains only odd haronics in the order of 6r1, where r is a nueral c assue values 1, 2, 3,.. In general star d delta connected windings have a relative phase shift of 30 d the three-level inverters connected to each of these Y d trsforers will give overall 12-pulse operation d offers a better haronic perforce. The output voltage will have a twelve pulse wavefor, with haronics of the order of 12r1. Thus the twelve pulse inverter will have 11 th, 13 th, 23 rd, 25 th,.. haronics with aplitudes of 1/11 th, 1/13 th, 1/23 rd, 1/25 th, respectively of the fundaental ac voltage. The relationship between the phase-to-phase voltage d the phase-to-neutral voltage is expressed as: r v = -1 3 v (8) For obtaining 12-pulse inverter the SI 1 output is connected to a Y-Y trsforer with a 11 turn ratio, d the line to neutral voltage using equation (8) c be expressed as: 1 v t = sin ωt 1 r (9) 3 =1-1 = 6r?, r = 0,1,2,... If the SI 2 produces phase-to-phase voltages lagging by 30 with respect to SI 1 d with the sae agnitude, it is given by 2 v t = sin ωt (10) =1 If this inverter output is connected to a -Y trsforer with a 11/3 turn ratio, the line-to-neutral voltage in the Y-connected secondary will be vy t = 2 sin ωt (11) =1 Therefore line-to-line voltage in the secondary side is π vy t = 3 2 sin ωt + (12) =1 6 The 12-pulse inverter output is obtained by adding the equations (5) d (12). v t = v t + v t (13) 12 Y 2 π v t = 12 sin ωt + 12 =1 6 =12r?, r = 0,1,2,... (14) 259
International Journal of Coputer d Electrical Engineering, ol. 2, No. 1, April, 2010 since = 12 + 3 = 2 π v t = 2 12 sin ωt + (15) =1 6 Siilarly two twelve pulse inverters phase shifted by 15 fro each other c provide a 24-pulse inverter, with uch lower haronics in the ac side. The ac output voltage will have 24r1 order haronics, i.e., 23 rd, 25 th, 47 th, 49 th,.. haronics, with agnitudes of 1/23 rd, 1/25 th, 1/47 th, 1/49 th,. respectively, of the fundaental ac voltage. Thus the output voltage of twenty four pulse inverter is obtained as: 鞍 v t = 4 24 sin ωt + 22.5 + 7.5 x (16) =1 4 鞍 v t = 24 sin ωt + 22.5-22.5 x (17) 3 =1 where x = 1 for positive sequence haronics x = -1 for negative sequence haronics = 24r?, r = 0,1,2,... In order to eliinate the 23 rd d 25 th haronic coponents, the conduction gle of the inverter is set to = 172.5 by choosing = 24 in equation (1). This configuration produces alost a near sinusoidal output voltage since the lowest significt haronic coponent is the 47 th haronic. Fig 5 Three level SI 2 haronics Fig 6 Three level SI 3 haronics. HARMONIC NEUTRALIZATION The agnitude d phase gle of the haronic coponents present at the outputs of the diode claped ultilevel inverters SI 1 to SI 4 are given in Figs.4-7 respectively. Since the haronic coponents 5, 7, 17, 19, 29, 31, 41, 43 present in adjacent inverters (SI 1 d SI 2, SI 3 d SI 4 ) are out of phase d have the sae agnitude, they ccel each other. Siilarly the haronic coponents 11, 13, 35, 37 present in the adjacent pairs of inverters are also ccelled. The haronic coponents 23, 25, 47, 49 which are in phase in all the four inverters add up with each other. This results to a 24-pulse inverter with the haronic coponents in the order of 24r±1. Fig.8 displays the haronic coponents of the 24-pulse inverters. Fig 7 Three level SI 4 haronics Fig 8 24-pulse inverter haronics Fig 4 Three level SI 1 haronics I. SIMULATION RESULTS AND DISCUSSION The 24-pulse inverter obtained by cobining MPI d MLI is siulated using MATLAB/Siulink to alyze the haronics in its output voltage. A dc source of 2000 volts is used at the input side. The load is a star connected RL load of 10 oh resistce d 0.1 H inductce connected in series. In order to reduce the agnitude of 23 rd d 25 th haronics the conduction gle of the inverter is set to = 172.5. The output voltage expressions derived for the 24-pulse inverter are validated with siulated results d are highlighted in Tle II. The cobined ultipulse-ultilevel 260
inverter configuration produces alost a near sinusoidal output voltage with a total haronic distortion of out 3.81% as depicted in Figs.9 d 10 respectively. TABLE II COMPARISON OF ANALYTICAL AND SIMULATED RESULTS Significt Haronics Peak output voltage (volts) Analytical Siulation 23 rd 25.095 25.21 25 th 23.087 24.27 47 th 187.36 189.56 49 th 179.715 183.02 [3] Ricardo Davalos M., Ju M. Rairez d O. Ruben Tapia, Three-phase ulti-pulse converter STATCOM alysis, Electric Power d Energy Systes, vol.27, 2005, pp.39-51. [4] Bhi Singh d R. Saha, A New 24-Pulse STATCOM for voltage regulation, Proceedings of International Conference on Power Electronics, Drives d Energy systes, PEDES 2006, 2006, 8B-03. [5] L. Gyugyi d N. G. Hingori, Understding FACTS: Concepts d Technology of Flexible AC Trsission Systes, IEEE press, New York, 1999. [6] A. Nae, Akira Takahashi, Isao Akagi d Hirofui, A new neutral point claped PWM inverter, IEEE Trsactions on Industry Applications, vol.ia-7, no.5, 1981, 518-523. [7] X.Yu d I.Barbi, Fundaentals of a new diode claping ultilevel inverter, IEEE Trsactions on Power Electronics, vol.15, no.4, 2002, pp.711-718. [8] J.S.Lai d F.Z.Peng, Multilevel converters A new breed of power converters, IEEE Trsactions on Industrial Applications, vol.32, 1996, pp.509-517. [9] F.G.Peng d J.S.Lai, Multilevel cascade voltage source inverter with separate dc sources, U.S. Patent 5 642 275, 1997. [10] J. Rodriguez, J.S.Lai d F.Z.Peng, Multilevel inverters: A survey of topologies, controls d applications, IEEE Trsactions on Industrial Electronics, vol.49, no.4, 2002, 724-738. [11] F.Z.Peng, J.S.Lai, J.W.McKeever d J.A.coevering, Multilevel voltage source inverter with separate dc sources for static var generation, IEEE Trsactions on Industrial Applications, vol.32, no.5, 1996, pp.1130-1138. Fig 9 Multipulse-ultilevel inverter output voltage B.Geethalakshi received Bachelor of Engineering in 1996 d Master of Engineering in 1999 fro Bharathidas University. She is copleted her Ph.D work in power electronics applications in power systes. She published paper in international journals d presented research papers in various international conferences. Her areas of interest include power converters such as ac-dc-ac converters, atrix converter d power factor correction techniques. P.Djay received Bachelor of Science fro University of Madras in 1978, Bachelor of Technology in 1982 d Master of Engineering in 1984 fro the Madras Institute of Technology, Chennai d Ph.D degree fro Anna University, Chennai in 1998. He is working as a Professor d Head of the Departent of Electronics d Counication Engineering, Pondicherry Engineering College, Pondicherry, India. He has ore th 60 publications in National d International Journals. He has presented ore th 130 papers in National d International conferences. He has produced 6 Ph.D cdidates d is currently guiding eight Ph.D students. His areas of interest include power electronics application in power syste, ATM Networks, Wireless Counication d Spread spectru Techniques. Fig 10 Multipulse-ultilevel inverter output voltage THD II. CONCLUSION A cobined ultipulse-ultilevel inverter topology suitle for high power applications has been proposed. The pulse pattern d the phase shifting trsforer arrgeent for haronic neutralization have been discussed in detail. The alytic expressions for the proposed inverter topology are derived using Fourier series d found to closely agree with the siulated results. This new inverter configuration produces alost three phase sinusoidal voltage d aintains THD well below 4%. Thus the proposed inverter is highly suitle for power syste applications. REFERENCES [1] Diego Soto d Ti.C. Green, A coparison of High-Power Converter Topologies for the ipleentation of FACTS Controllers, IEEE Trsactions on Industrial Electronics, vol.49, 2002, pp.1072-1080. [2] Bhi Singh, G. Bhuveswari d ipin Garg, Haronic itigation using 12-pulse ac-dc converter in ector Controlled Induction Motor Drives, IEEE Trsactions on Power Delivery, vol.21, no.3,2006, 1483-1492. 261