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Operating Range 2-V to.-v V CC Latch-Up Performance Exceeds 20 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A11-A) 1000-V Charged-Device Model (C101) SN4AHC00...J OR W PACKAGE SN74AHC00... D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y 1 2 4 6 7 14 1 12 11 10 9 8 V CC 4B 4A 4Y B A Y description/ordering information SN74AHC00... RGY PACKAGE (TOP VIEW) 1B 1Y 2A 2B 2Y 2 4 6 1A Y V 1 14 7 8 CC 1 12 11 10 9 4B 4A 4Y B A SN4AHC00... FK PACKAGE (TOP VIEW) 1Y 2A 2B 1B 1A V CC 4B 4 2 1 20 19 18 6 7 8 17 16 1 14 91011121 2Y Y A No internal connection 4A 4Y B The AHC00 devices perform the Boolean function Y A B or Y A B in positive logic. TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER QFN RGY Tape and reel SN74AHC00RGYR HA00 TOP-SIDE MARKING PDIP N Tube SN74AHC00N SN74AHC00N Tube SN74AHC00D SOIC D Tape and reel SN74AHC00DR 40 C to8 C AHC00 SOP NS Tape and reel SN74AHC00NSR AHC00 SSOP DB Tape and reel SN74AHC00DBR HA00 TSSOP PW Tape and reel SN74AHC00PWR HA00 TVSOP DGV Tape and reel SN74AHC00DGVR HA00 CDIP J Tube SNJ4AHC00J SNJ4AHC00J C to 12 C CFP W Tube SNJ4AHC00W SNJ4AHC00W LCCC FK Tube SNJ4AHC00FK SNJ4AHC00FK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2002, Texas Itruments Incorporated On products compliant to MIL-PRF-8, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 60 DALLAS, TEXAS 726 1

FUTION TABLE (each gate) INPUTS OUTPUT A B Y H H L L X H X L H logic diagram, each gate (positive logic) A B Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC.......................................................... 0. V to 7 V Input voltage range, V I (see Note 1).................................................. 0. V to 7 V voltage range, V O (see Note 1)........................................ 0. V to V CC + 0. V Input clamp current, I IK (V I < 0)........................................................... 20 ma clamp current, I OK (V O < 0 or V O > V CC )............................................ ±20 ma Continuous output current, I O (V O = 0 to V CC ).............................................. ±2 ma Continuous current through V CC or................................................... ±0 ma Package thermal impedance, θ JA (see Note 2): D package................................... 86 C/W (see Note 2): DB package................................. 96 C/W (see Note 2): DGV package............................... 127 C/W (see Note 2): N package................................... 80 C/W (see Note 2): NS package................................. 76 C/W (see Note 2): PW package................................ 11 C/W (see Note ): RGY package................................ 47 C/W Storage temperature range, T stg................................................... 6 C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 1-7.. The package thermal impedance is calculated in accordance with JESD 1-. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726

recommended operating conditio (see Note 4) SN4AHC00 SN74AHC00 MIN MAX MIN MAX Supply voltage 2. 2. V = 2 V 1. 1. VIH High-level input voltage = V 2.1 2.1 V =. V.8.8 = 2 V 0. 0. VIL Low-level input voltage = V 0.9 0.9 V =. V 1.6 1.6 VI Input voltage 0. 0. V VO voltage 0 0 V = 2 V 0 0 A IOH High-level output current =. V ± 0. V 4 4 = V ± 0. V 8 8 ma = 2 V 0 0 A IOL Low-level output current =. V ± 0. V 4 4 t/ v Input traition rise or fall rate = V ± 0. V 8 8 =. V ± 0. V 100 100 = V ± 0. V 20 20 TA Operating free-air temperature 12 40 8 C NOTE 4: All unused inputs of the device must be held at or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 2 C SN4AHC00 SN74AHC00 MIN TYP MAX MIN MAX MIN MAX 2 V 1.9 2 1.9 1.9 IOH = 0 A V 2.9 2.9 2.9 VOH 4. V 4.4 4. 4.4 4.4 V IOH = 4 ma V 2.8 2.48 2.48 IOH = 8 ma 4. V.94.8.8 2 V 0.1 0.1 0.1 IOL = 0 A V 0.1 0.1 0.1 VOL 4. V 0.1 0.1 0.1 V IOL = 4 ma V 0.6 0. 0.44 IOL = 8 ma 4. V 0.6 0. 0.44 II VI =. V or to. V ±0.1 ±1* ±1 A ICC VI = or, IO = 0. V 2 20 20 A Ci VI = or V 2 10 10 pf * On products compliant to MIL-PRF-8, this parameter is not production tested at =. ma /V POST OFFICE BOX 60 DALLAS, TEXAS 726

switching characteristics over recommended operating free-air temperature range, V CC =. V ± 0. V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 2 C SN4AHC00 SN74AHC00 PARAMETER (INPUT) (OUTPUT) CAPACITAE MIN TYP MAX MIN MAX MIN MAX.* 7.9* 1* 9.* 1 9. AorB Y CL =1pF.* 7.9* 1* 9.* 1 9. 8 11.4 1 1 1 1 AorB Y CL =0pF 8 11.4 1 1 1 1 * On products compliant to MIL-PRF-8, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, V CC = V ± 0. V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 2 C SN4AHC00 SN74AHC00 PARAMETER (INPUT) (OUTPUT) CAPACITAE MIN TYP MAX MIN MAX MIN MAX.7*.* 1* 6.* 1 6. AorB Y CL =1pF.7*.* 1* 6.* 1 6..2 7. 1 8. 1 8. AorB Y CL =0pF.2 7. 1 8. 1 8. * On products compliant to MIL-PRF-8, this parameter is not production tested. noise characteristics, V CC = V, C L = 0 pf, T A = 2 C (see Note ) PARAMETER SN74AHC00 MIN TYP MAX VOL(P) Quiet output, maximum dynamic VOL 0. 0.8 V VOL(V) Quiet output, minimum dynamic VOL 0. 0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.6 V VIH(D) High-level dynamic input voltage. V VIL(D) Low-level dynamic input voltage 1. V NOTE : Characteristics are for surface-mount packages only. operating characteristics, V CC = V, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance No load, f = 1 MHz 9. pf 4 POST OFFICE BOX 60 DALLAS, TEXAS 726

PARAMETER MEASUREMENT INFORMATION From Under Test CL (see Note A) Test Point From Under Test CL (see Note A) RL = 1 kω S1 Open TEST / tplz/tpzl tphz/tpzh Open Drain S1 Open LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR -STATE AND OPEN-DRAIN OUTPUTS Input 0% tw 0% Timing Input Data Input tsu 0% th 0% 0% PULSE DURATION SETUP AND HOLD TIMES Input In-Phase Out-of-Phase 0% 0% 0% 0% VOH 0% VOL VOH 0% VOL PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Control Waveform 1 S1 at (see Note B) Waveform 2 S1 at (see Note B) tpzl tpzh 0% 0% 0% 0% tplz VOL + 0. V VOL tphz ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING VOH VOH 0. V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, tr, tf. D. The outputs are measured one at a time with one input traition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726

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