Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00 Latch-Up Performance Exceeds 20 ma Per JESD 17 ESD Protection Exceeds 2000 Per MIL-STD-88, Method 01; Exceeds 200 Using Machine Model (C = 200 pf, R = 0) Package Optio Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin ery Small-Outline (DG), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) DIPs SN4AHCT12...J OR W PACKAGE SN74AHCT12... D, DB, DG, N, OR PW PACKAGE (TOP IEW) SN4AHCT12... FK PACKAGE (TOP IEW) 1Y 2A 2B 1A 1B 1Y 2A 2B 2Y 1 2 4 6 7 1B 1A 14 1 12 11 10 9 8 CC 4B CC 4B 4A 4Y B A Y 4 2 1 20 19 18 6 7 8 17 16 1 14 91011121 4A 4Y B description The AHCT12 devices are quadruple No internal connection positive-nand gates. These devices perform the Boolean function Y = A B or Y = A + B in positive logic. Each circuit functio as a NAND gate, but because of the Schmitt action, it has different input threshold levels for positive- and negative-going signals. These circuits are temperature compeated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. The SN4AHCT12 is characterized for operation over the full military temperature range of C to 12 C. The SN74AHCT12 is characterized for operation from 40 C to 8 C. FUTION TABLE (each gate) INPUTS OUTPUT A B Y H H L L X H X L H 2Y Y A Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Itruments Incorporated. UNLESS OTHERWISE NOTED this document contai PRODUCTION DATA information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 60 DALLAS, TEXAS 726 Copyright 1998, Texas Itruments Incorporated 1
logic symbol 1 1A 2 1B 2A 2B A B 4A 4B 4 9 10 12 1 & 6 8 11 1Y 2Y Y 4Y This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DG, J, N, PW, and W packages. logic diagram (positive logic) A Y B absolute maximum ratings over operating free-air temperature range Supply voltage range, CC.......................................................... 0. to 7 Input voltage range, I (see Note 1)................................................... 0. to 7 voltage range, O (see Note 1)......................................... 0. to CC + 0. Input clamp current, I IK ( I < 0)............................................................ 20 ma clamp current, I OK ( O < 0 or O > CC )............................................ ±20 ma Continuous output current, I O ( O = 0 to CC ).............................................. ±2 ma Continuous current through CC or................................................... ±0 ma Package thermal impedance, θ JA (see Note 2): D package.................................. 127 C/W DB package................................. 18 C/W DG package............................... 182 C/W N package................................... 78 C/W PW package................................ 170 C/W Storage temperature range, T stg.................................................... 6 C to 10 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 1, except for through-hole packages, which use a trace length of zero. 2 POST OFFICE BOX 60 DALLAS, TEXAS 726
recommended operating conditio (see Note ) SN4AHCT12 SN74AHCT12 MIN MAX MIN MAX CC Supply voltage 4.. 4.. IH High-level input voltage 2 2 IL Low-level input voltage 0.8 0.8 I Input voltage 0. 0. O voltage 0 CC 0 CC IOH High-level output current 8 8 ma IOL Low-level output current 8 8 ma TA Operating free-air temperature 12 40 8 C NOTE : All unused inputs of the device must be held at CC or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS CC TA = 2 C SN4AHCT12 SN74AHCT12 MIN TYP MAX MIN MAX MIN MAX T+ 4. 1.9 1.9 1.9 Positive-going input threshold voltage. 2.1 2.1 2.1 T Negative-goinggoing 4. 0. 0. 0. input threshold voltage. 0.6 0.6 0.6 TT 4. 0. 1.4 0. 1.4 0. 1.4 Hysteresis (T+ T ). 0. 1. 0. 1. 0. 1. IOH = 0 A IOH = 8 ma IOL = 0 A IOL = 8 ma 4 4. 4 4. 4.4 4. 4.4 4.4.94.8.8 0.1 0.1 0.1 0.6 0. 0.44 II I = CC or. ±0.1 ±1 ±1 A ICC I = CC or, IO = 0. 2 20 20 A ICC One input at.4, Other inputs at CC or. 1. 1. 1. ma Ci I = CC or 2 10 10 pf This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 or CC. switching characteristics over recommended operating free-air temperature range, CC = ± 0. (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD (INPUT) (OUTPUT) CAPACITAE * * AorB Y CL =1pF AorB Y CL =0pF * On products compliant to MIL-PRF-8, this parameter is not production tested. SN4AHCT12 TA = 2 C MIN TYP MAX MIN MAX. 8 1 9 4. 6 1 7 6. 9 1 10. 7 1 8 PRODUCT PREIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 60 DALLAS, TEXAS 726
switching characteristics over recommended operating free-air temperature range, CC = ± 0. (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD (INPUT) (OUTPUT) CAPACITAE SN74AHCT12 TA = 2 C MIN MIN TYP MAX MAX AorB Y CL =1pF. 8 1 9 4. 6 1 7 AorB Y CL =0pF 6. 9 1 10. 7 1 8 noise characteristics, CC =, C L = 0 pf, T A = 2 C (see Note 4) PARAMETER SN74AHCT12 MIN TYP MAX (P) Quiet output, maximum dynamic 0. 0.8 () Quiet output, minimum dynamic 0.28 0.8 () Quiet output, minimum dynamic IH(D) High-level dynamic input voltage 2 IL(D) Low-level dynamic input voltage 0.8 NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, CC =, T A = 2 C PARAMETER TEST CONDITIONS TYP Cpd Power dissipation capacitance No load, f = 1 MHz 1 pf 4 POST OFFICE BOX 60 DALLAS, TEXAS 726
PARAMETER MEASUREMENT INFORMATION From Under Test CL (see Note A) Test Point From Under Test CL (see Note A) RL = 1 kω S1 CC Open TEST / tplz/tpzl tphz/tpzh Open Drain S1 Open CC CC LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR -STATE AND OPEN-DRAIN OUTPUTS Input 1. tw TAGE WAEFORMS PULSE DURATION 1. 0 Timing Input Data Input tsu 1. th 1. 1. TAGE WAEFORMS SETUP AND HOLD TIMES 0 0 Input In-Phase Out-of-Phase 1. 1. 0% CC 0% CC 0% CC 0 0% CC TAGE WAEFORMS PROPAGATION DELAY TIMES INERTING AND NONINERTING OUTPUTS Control Waveform 1 S1 at CC (see Note B) Waveform 2 S1 at (see Note B) tpzl tpzh 1. tplz 0% CC tphz 0% CC 1. TAGE WAEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEEL ENABLING 0 CC + 0. 0. 0 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, tr, tf. D. The outputs are measured one at a time with one input traition per measurement. Figure 1. Load Circuit and oltage Waveforms POST OFFICE BOX 60 DALLAS, TEXAS 726
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