MAGNT Research Report (ISSN. -8939) A Study of a Three Phase Diode Clamped Multilevel Inverter Performance For Harmonics Reduction Rosli Omar, Mohammed Rasheed, Marizan Sulaiman, Ahmed Al-Janad Universiti Teknikal Malaysia Melaka, Industrial Power, Faculty of Electrical Engineering, Hang Tuah Jaya 76 Durian Tunggal, Melaka, Malaysia. Abstract: This paper presents a comparative study five to nine levels of diode clamped multilevel inverter, for reduction of harmonics in the multilevel inverter output. The proposed system is designed using MATLAB/SIMULINK and it consists of diode clamped multilevel inverter. The controller is based on the sinusoidal pulse width modulation (SPWM) technique which is applied to the purposed three phase multilevel inverters. The various performances of simulation results of the diode clamped multilevel inverters have been investigated. The Total harmonic distortion (THDv) of the output voltage is measured of the five to nine levels of multilevel inverters. Based on varying simulation results, it is found that the THD voltage of the nine levels is considerably lower than the seven and five levels diode clamped multilevel inverter. Keywords- Multilevel inverter, Diode Clamped Inverter (NPC), SPWM. I. INTRODUCTION Nowadays, multilevel inverters have become more attractive for their initial usage in highvoltage and high-power applications. Multilevel converters (or inverters) have been used for AC to DC, AC to DC to AC, DC to AC, and DC to DC power conversion in high power applications such as utility and large motor drive applications []. Multilevel inverters provide more than two voltage levels. The generalized multilevel inverter topology can balance each voltage level by itself regardless of inverter control and load characteristics. The concept of multilevel converters has been introduced since 975 []. The usage of these applications has become more diverse and affects a wide field of electrical engineering from a few watts to several hundred megawatts. Converting static structures that comprise mainly applications of power electronics are becoming increasingly powerful, the technology has had to adapt to the growth of the power to convert Multilevel inverters have three topologies. Cascaded H-bridge (CHB) Diode Clamped (NPC) Flying Capacitors (FC) Cells with separated DC sources shown in Fig.. This growth has been possible to the development of technologies of semiconductor components. Changing templates voltage and current as well as improved performance of these components has to use more power electronics performance for applications of greater power [3]. The emergence and development of new components controllable powers opening and closing as the GTO (gate turn-off Thyristor) and IGBT (insulated gate bipolar transistors) allowed the design of new converters reliable, fast and powerful. Thus, all drives (static machine converter current AC) saw costs are reduced considerably.progress in the field of the microcomputer (fast and powerful microcontrollers) Allowed the syndissertation control algorithms of these sets more efficient converter machine and robust []. The Pulse Width Modulation (PWM) is a technique to control static converters for interfacing between a load (electrical machine) and supply means (three-phase inverter). It is a technique used for energy conversion, having its base in the field of telecommunications (signal processing). It bears the English name of Pulse Width Modulation (PWM) or Pulse-Duration Modulation (PDM), using a name older. Far from being an accessory element in the chain of variable speed (inverter power associated with an electric machine), the PWM stage plays an important role with impact on the performance of all system performance driving, loss in the inverter or in the machine, the acoustic noise, electromagnetic noise, even the destruction of the system, eg due to over voltages which occur during the use of long cables [5].
(a) Cascaded H-Bridge (CHB) (b) Diode Clamped (NPC) (c) Flying capacitor (FC) Fig : Topologies of Multilevel Inverter, (a) Cascaded H-Bridge (CHB), (b) Diode Clamped (NPC) (c) Flying Capacitor (FC). II. MULTILEVEL INVERTER The Concepts of multilevel inverters (MLI) depends not only on two voltage levels to create the AC signal. Instead, it is added to most levels of voltage to the other to create a form of reinforced smooth wave, with a low dv/dt and less harmonic distortion. With more in the inverter voltage levels it creates a smoother waveform becomes, but with many levels of design becomes more complex, with more components and must be more complex controller for inverter [6]. The multilevel inverters diagrams Fig.. Illustrates of the inverters have been -level inverter, 3-level inverter, and the N-level inverter. All the capacitors include to a voltage of V dc. Vdc Vdc/ Vdc/N- Vdc/N- Vdc/N- a a a Vdc/ Vdc/N- Vdc/N- (a) (b) (c) where the objectives were to improve performance, simplify PWM strategies and applications of microprocessors later, to produce a reduction of harmonic distortion and reduce switching losses [7]. Has been extended to several principles support levels based PWM technology as a means of controlling the active devices in a multilevel converter. PWM three techniques commonly used are- the sinusoidal PWM technology [8]. l)- High-qualify utilization of a DC power supply that is to deliver a higher output voltage with the same DC supply. )- Good linearity in voltage and/ or current control. 3)- Low harmonic contents in the output voltage and/ or currents, especially in the low-frequency region. )- Low switching losses. A. Sinusoidal Pulse-Width Modulation Control technology is the most popular method of pulse width modulation sine adapter s two traditional levels. The tem sinusoidal PWM reference is made to the production of the PWM output signal with a sine wave as a modulation signal [9]. The on and off instants of a PWM signal ill this case, can be determined by comparing the sinusoidal signal (wave modulation) with a triangular wave frequency (carrier wave), as shown in Fig 3 sinusoidal PWM technology is commonly used in industrial applications and abbreviated here as SPWM []. Frequency of the modulating wave determines the frequency of the output voltage. The enlargement of the height of the modulation index of the waveform and determines the composition turn control the RMS value of the output voltage []. V Reference single Carrier wave Triangle No 8 Fig.. The MLI diagrams of (a) -levels (b) 3- levels (c) N-llevels. - 7 6 5 3 III. PULSE WIDTH MODULATION (PWM) TECHNIQUES In the early 97s, the majority of PWM inverters using techniques based on the sampling method. Sinusoidal pulse width modulation of the primitive techniques, which are used to suppress the harmonics, present in a quasi-square wave. Over the years, he has developed technical PWM - Output Voltage Fig 3: Sinusoidal Pulse-Width Modulations. The RMS value of the output voltage can be varied by changing the modulation index. The t
output voltage of the inverter contains harmonics. However, to be paid for the harmonics of the band around the carrier frequency and its complications []. To perform sinusoidal PWM using analog circuit, use a series of bricks: ) High-frequency triangular wave generator. ) Sine wave generator. 3) Comparator. ) Inverter circuits with dead-band generator to generate complimentary driving Signals with required dead band. IV. TOPOLOGIESMULTILEVELINVERTE R B. Diode Clamped Multilevel Inverter According to the patent, developed the first Multi-Level Inverter (MLI) in 975, and was cascaded inverter blocking diode source. This inverter was later derived into the Diode Clamped Multilevel Inverter, also called Neutral- Point Clamped Inverter (NPC), as shown in Fig. NPCMLI topology and the use of voltage limiting diodes are essential. Shared DC bus is divided by an even number, depending on the number of voltage levels of the inverter and the majority of capacitors in series with the neutral point in the middle of the line as shown in Fig.[3]. The DC bus, with neutral point and capacitors, there are clamping diodes connected in an M- number of valve pairs, where M is the number of voltage levels in the inverter (voltage levels it can generate). By adding two identical circuits the three phases-legs can together generate a three-phase signal where the sharing of the DC-bus is possible. Note that the required number of clamping diodes is very high and a large number of voltage levels topology NPC would not be practical due to this fact[]. Due to the inverter for clamping diodes connected in series so that all the diodes can be the same voltage rating and be able to block the right number of voltage levels. In Fig all diodes are rated for Vdc ( Vdc ) and the D diodes need to m block 3 ( Vdc ) Thus, there are three diodes in series. However, for low-voltage application, it is not necessary to connect a plug-in series to withstand the voltage, since components with sufficient high voltage ratings are easy to find. Can be generated with this configuration five voltage levels between point a and the neutral point n; Vdc, Vdc,, Vdc and Vdc depending on which switches that are switched on. Waveform from one-phase leg to the inverter as shown in Fig in which the steps are clearly visible. NPCMLI: S with a larger number of voltage levels the steppes will be smaller and the waveform smaller to a sinusoidal signal. Of course, with a higher number of voltage levels the complexity of the inverter increase and also, as earlier mentioned, the number of components needed. To achieve the different voltage levels in the output a setup of switching state combinations are used [5]. + _ Vdc Vdc/ C Vdc/ C n C3 -Vdc/ C -Vdc/ v D D' D D' D3 D3' Vout S S S3 S S' S' S3' S' t a load Fig : One phase-leg for a five-level NPC Inverter. V. STUDY OF MUTLILEVEL INVERTER BASED ON ATLAB/SIMULINKMODELING This paper describes the study of the three phase diodes clamped in multilevel inverters using MATLAB/SIMULINK. It describes the layout of the proposed multilevel inverters to simulate the step-by-step procedure to build the simulation model. MATLAB / Simulink version 7.8 was used to model, analyse and Simulink for five to nine levels for modelling, simulation and analysis. It supports the systems, as in the time of
linear, time samples and non-linear, constantly. As for the model, Simulink provides the construction of models and diagrams. Control block generates a PWM signal is given to the new level inverters for reduce total harmonic distortion can be calculated using equations (3., 3., 3.3). n H ( n) THD () H Where: H is the amplitudes of the fundamental component, whose frequency is w and H n is the amplitudes of the nth harmonics at frequency nw s hn k cos( n k ) () n s hn n leth n hnandh h k k n cos( ) ( ) s ( n cos( n)) k THD n (3) s cos( n ) k C. Sinusoidal Pulse Width Modulation SPWM The generations of gating signals with sinusoidal Pulse Width Modulation (SPWM) are shown in Fig 5(a). There are sinusoidal reference waves ( ra, rb and rc ) and each is shifted by. A carrier wave is compared with the reference signal corresponding to a phase to generate the gating signal for that phase. Furthermore, when comparing the carrier signal with the reference phase rc ra, rb andrc it produced g and g 5, respectively as shown in Fig 5(b). The instantaneous line-to-line output voltage is: ab VS gg3 () where; ab = Sinusoidal reference. V S = Line-to-line output voltage. The output voltage as shown in Fig 5(c), is generated by eliminating the condition that two switching devices in the same arm cannot be conducted at the same time. The normalized k carrier frequency, mf, should be odd and multiplied by three. Thus, all phase-voltage ( ra, rb and rc ) were identical, but out of phase was without even harmonics; moreover harmonics at frequency multiplier of three were identical in amplitude and phase in all the phases. For instance, if the ninth harmonic voltage in phase a is an 9 t 9sin 9 wt (5) where; an 9 = Phase-voltage. wt = f. The corresponding ninth harmonics in phase b would be, an 9 t 9 sin 9wt ) 9 sin 9wt 8 ) 9 sin 9wt (6) Thus, the ac output line voltage does not contain the ninth ab an bn harmonics. Therefore, for the odd multiples of three time of the normalized carrier frequency mf, the harmonics in the ac output voltage appeared to be at a normalized frequency fh centred around mf and its multiple, specifically, at n jmf k (7) n jmf k (8) where; mf = Carrier frequency. Besides, it is considered as good quality for the output voltage if the modulation index (MI) is in the range of to.95. In the case of MI is greater than.95, there is a direct correlation between the anti-wave quality and amplitude of the output voltage if the quality decreases, and then increases the output voltage wave size. The SPWM technology has its limitations regarding the maximum voltage that can be achieved, and the transfer of power. In the case of a three-phase inverter, the proportion of the main ingredient to the line of maximum possible line voltage to a DC supply voltage is 86.6% and this indicates the use of poor DC power supply. Besides, the SPWM is an effective way to reduce the lower harmonics of the system while varying the output voltage. However, the low-frequency harmonic content is in minimum value
V Vra Vrb Vrc (a) wt V+ (b) (c) -V wt wt wt Fig 5: Sinusoidal Pulse Width Modulation for three-phase inverter. D. Models of Diodes Clamped in Multilevel Inverter(NPC) In order to convert five level of multilevel inverter, it requires control signal. Five level of multilevel inverter has (m-) levels, where m is the number of voltage levels. Thus, the controller of the five level inverter needs eight control signals. Fig 6, show the control signals generated by the Diodes Clamped in Multilevel Inverter. Moreover, the simulation diagrams for the seven and nine level similarly are shown in one block. Four sets of saturation phase arm devices are connected to the block. Thus, the lower four signals can be generated from the major brands, but this requires the signals to be reversed and the dead time to be included. Next, in the implementation of SPWM system, the samples were regularly implemented to reduce the carrier frequency of equity in 5 for the implementation of the total harmonic reduction (THDv), which is less than 5%, based on many calculations. In this system, block consists of switches GTO in Diodes Clamped (NPC) Thyristor as shown in Figure 7. the diodes in the multi-level inverter (NPCMLI) are not used for generating control signals. This is due to the low levels of harmonic that have been created by the multi-level converters that are able to work within the switching frequencies. Therefore, it is easy to calculate the modulating wave compared to the sampling frequency. Fig 6:Simulink Multilevel Inverter diagram with Five Levels of control signal generated by Clamped Diodes. Fig 7: Switching GTO Thyristor for five Levels with Diodes Clamped in Multilevel Inverter. VI. HARMONIC REDUCTION BY INCREASING THE NUMBER OF VOLTAGE LEVEL IN MULTILEVEL INVERTERS Reduction of harmonics in multilevel converters could not be achieved by increasing the number of levels of the staircase wave form output. THD was produced less by increasing the number of voltage sources. The effective values of the output voltage depended on the number of units in a multilevel inverter. The switching pattern that was used in this dissertation for all of the multilevel inverters was indeed a harmonic elimination method. In this method, the switching angles for the switches were calculated in such a way that the lower dominant harmonics were eliminated. In this study, the cases of 5-level, 7- level and 9-level multilevel inverters were investigated. For the 5-level inverter, the 5th harmonic was eliminated. On the other hand, as for the 7-level inverter, the and the harmonic were removed. Lastly, in the 9-level inverter, the, and harmonics were eliminated. The Fourier analysis was conducted to determine the frequency spectra of the output wave form. The
Line Voltage (V) Line Voltage (V) Phase Voltage (V) Phase Voltage (V) Fourier series of a 5-level unity DC source is shown in (9). V dc V f t f t f t h h dc cos cos (9) h sin hwt [cos h ] h i () h VII. SIMULATION RESULTS This paper presents the data and the results gathered from the preceding paper. In this work, two types of multilevel inverter; diodes clamped (NPC), were tested with three phases, using sinusoidal pulse width modulation (SPWM) control inverter, and a simulation module by MATLAB/SIMULINK three phase multilevel inverters. Based on the simulation results, a Fivelevel to Nine levels (odd levels) of SPWM inverters was presented to alleviate harmonic components of output voltage. The inverters were designed in different ways, the multilevel inverters applied a GTO Thyristor inverter, which generated 5 Hz. Additionally, the selected carrier frequency was 5 Hz and he modulation index was equal to.8 and.95. A. Diode Clamped Multilevel Inverter Results The simulation result is shown in Fig 8. As for the five-level diodes clamped in the multilevel inverter, the output voltage wave form for line to neutral with Modulation Index was equal to.95 and the output voltage was 67.6 V RMS in value. When the Modulation Index decreased to.8, as shown in Fig 9, the inverter output voltage was equal to 58.7 V RMS. The number of steps for both the figures were 5 (n=5) for the quarter wave and in the case of full wave, the number of steps was (n=,n=5).the simulation result is shown in Fig, for the five-level diodes clamped in the multilevel inverter. The output voltage wave form for line to line in the of number of steps in this level increased to for the quarter wave and steps for full wave, with the Modulation Index equal to.95, whereas, the output voltage produced 85.5 V RMS. When the Modulation Index decreased to.8, the output voltage value was equal to 7.6 V RMS. The number of steps used was similar, as in Fig. The THD V for voltage for the five level output diodes clamped in the multilevel inverter was measured when the Modulation Index was equal to.95. It was found that the value of THD V for voltage was around 7.%, as shown in Fig. Furthermore, FFT analysis is shown in Fig 3 for the five level Diodes clamped in the multilevel inverter output. The THD V for voltage obtained from the output of diodes clamped in the multilevel inverter when the Modulation Index was equal to.8, was actually lower when the Modulation Index was equal to.95 and its value was 7.6%. 3 5 - -...6.8. Fig 8. Phase Voltage of MI=.95 - - -3...6.8. 5 Fig 9.Phase Voltage of MI=.8-5...6.8. Fig. Line Voltage of MI=.95-5...6.8. Fig. Line Voltage of MI=.8.
Line Voltage (V) Line Voltage (V) Phase Voltage (V) Phase Voltage (V) Fundamental (5Hz) = 38., THD= 7.% 3.5 3 Fundamental (5Hz) = 38, THD= 7.6% 3.5.5.5 3 5 6 7 8 9 3 5 6 7 8 9 Fig. Harmonic Voltage of MI=.95. Fig 3. Harmonic Voltage of MI=.8. The simulation result is shows in Fig. for the Seven-level diodes clamped in the multilevel inverter. The output voltage wave form for line to neutral with the Modulation Index was equal to.95, as shown in Fig 5, and the output voltage was 6. V RMS. The Modulation Index decreased to.8 as the inverter output voltage was equal to 7. V RMS. The number of steps for both the figures were 7 (n=7) for the quarter wave and in the case of full wave, the number of steps was (n=,n=7). Next, the simulation results for the Seven-level diodes clamped in multilevel inverter showed that the output voltage wave form for line to line in the number of steps increased to for the quarter wave and 8 steps for the full wave, with Modulation Index equal to.95, as shown in Fig 6. The output voltage produced was about 373.6 V RMS. When the Modulation Index decreased to.8, the output voltage value was equal to 3. V RMS. The number of steps used was similar as in Fig 7. The THD V for voltage of the seven level output for the diodes clamped in multilevel inverter was around 5.7% when the Modulation Index was equal to.95, as shown in Fig 8. The FFT analysis is shown in Fig 9 with the seven level Diodes clamped in multilevel inverter. The THD V for the voltage obtained when the Modulation Index was equal to.8, was lower when the Modulation Index was equal to.95 and its value was 5.3%. 3 - - - -3 -...6.8. -...6.8. Fig. Phase Voltage of MI=.95. Fig5.Phase Voltage of MI=.8. 8 6 6 - - -6 - - -8...6.8. Time(sec) Fig6. Line Voltage of MI=.95. -6...6.8. Fig 7. Line Voltage of MI=.8.
Line Voltage (v) Line Voltage (v) Phase Voltage (v) Phase Voltage (v) Fundamental (5Hz) = 3.7, THD= 5.7% 3.5 Fundamental (5Hz) = 9., THD= 5.3%.5 3.5.5.5.5 3 5 6 7 8 9 3 5 6 7 8 9 Fig 8.Harmonic Voltage of MI=.95. Fig 9.Harmonic Voltage of MI=.8. Next, the simulation result is shown in Fig. for the Nine-level diodes clamped in multilevel inverter. The output voltage wave form for line to neutral when the Modulation Index was.95, was 35.5 V RMS. When the Modulation Index decreased to.8, as shown in Fig the inverter output voltage was equal to 85. V. The number of steps for both figures were 9 (n=9) for the quarter wave and in full wave, the number of steps was 8 (n=8,n=9). As for the Nine-level diodes clamped in multilevel inverter, the simulation result is shown in Fig The output voltage wave form for line to line in the number of steps for this level increased to 8 for the quarter wave and 36 steps for the full wave with Modulation Index equal to.95. The output voltage produced was about 5.7 V RMS. When the Modulation Index decreased to.8, the output voltage value was equal to 9.9 V RMS. The number of steps used was similar as in Fig 3. The THD V for the voltage of the output diodes clamped in multilevel inverter was measured when the Modulation Index was equal to.95. It was found that the value of the THD V of the voltage was around 3.9%, as shown in Fig. The FFT analysis is shown in Fig 5 for Diodes clamped in multilevel inverter. The THD V for the voltage was obtained when the Modulation Index was equal to.8, which was lower, when the Modulation Index was equal to.95 with value of 3.7%. 5 5-5...6.8. -5...6.8. Fig.Phase Voltage of MI=.95. Fig.Phase Voltage of MI=.8. 5 5-5 -5 -...6.8. Fig.Line Voltage of MI=.95. -...6.8. Fig 3. Line Voltage of MI=.8.
Fundamental (5Hz) = 766.6, T HD= 3.9% Fundamental (5Hz) = 69.8, T HD= 3.7% 3.5 6 8 6 8 Fig.Harmonic Voltage of MI=.95. Fig 5.Harmonic Voltage of MI=.8. TABLE I: Comparison of five to nine levels diodes clamped inverters with different modulation index (m=.95,m=.8). Index(M) Phase Voltage RMS Line Voltage RMS THDv Diode Diode Diode Five MI=.95 67.6 85.5 7.% MI=.8 58.7 7.6 7.6% Seven MI=.95 6. 373.6 5.7% MI=.8 7. 3. 5.3% Nine MI=.95 35.5 5.7 3.9%. MI=.8 85. 9.9 3.7%. VIII. CONCLUSION The choice was based on the topology of each inverter and depended on the use of the inverter. Each topology had its advantages and disadvantages. By increasing the number of ACKNOWLEDGMENT The authors wish to thank University of Technical Malaysia Melaka. This work was supported primarily by the MTUN-CoE, Project code: MTUN//UTeM-FKE/ M REFERENCES [] D. V. Wanjekeche, T.; Jimoh, A. A.; Nicolae, A Novel 9-Level Multilevel Inverter Based on 3-Level NPC/H-Bridge Topology for Photovoltaic Applications, vol., no. 5, pp. 769 777, 9. [] J. Rodríguez, S. Member, and J. Lai, Multilevel Inverters : A Survey of Topologies, levels, the THDv dropped, but the cost on the other hand, was high as well. Moreover, since the angles of the switching were not identical, the control circuit for each switch was separate from other switches. The two-level inverter had the lowest cost and weight compared to other topologies. However, this inverter had a very high THD; THD for about 3% when using the switching event for fundamental period. The cost and weight of the transformers at the 5-level multilevel inverters were better than the 7- and 9- levels at the multilevel inverters. By increasing the number of levels, the cost and the weight of the multilevel inverter were increased too. The advantage that the 9-level multilevel inverter had over the 7- and 5-levels was the THDv. The 9- level multilevel inverter had lower THDv than the 7- and the 5-levels. For example, the THDv at 5, 7 and 9 levels multilevel inverters were 7%, 5% and 3%, respectively, with the modulation index used was M =.95 and M =.8. Controls, and Applications, vol. 9, no., pp. 7 738,. [3] S. H. Hosseini, M. Ahmadi, and S. G. Zadeh, Reducing the output Harmonics of Cascaded H-Bridge Multilevel Inverter for Electric Vehicle Applications, vol., no., pp. 75 755. [] F. Farokhnia, Naeem; Vadizadeh, Hadi; Anvariasl, Line Voltage THD Calculation of Cascaded Multilevel Inverter s Stepped Waveform with Equal DC Sources, vol. 6, no. 3, pp. 9 8,. [5] D. P. Duggapu and S. Nulakajodu, Comparison between Diode Clamped and H- Bridge Multilevel Inverter ( 5 to 5 odd levels ), vol., no. 5, pp. 8 56,. [6] Y. Q. Bo Gong, Shanmei Cheng, Kai Cai, Simple Three-Level Neutral Point Potential
Balance Control Scheme Based on SPWM, vol. 7, no., pp. 663 67,. [7] N. R. Rosli Omar, New Configuration of a Three Phase Dynamic Voltage Restorer (DVR) for Voltage Disturbances Mitigation in Electrical Distribution System, Arabian Journal for Science and Engineering,vol. 37,no. 8, pp.5. [8] L. M. Tolbert, S. Member, and F. Z. Peng, Multilevel PWM Methods at Low Modulation Indices, vol. 5, no., pp. 79 75,. [9] N. R. R Omar, Voltage unbalanced compensation using dynamic voltage restorer based on supercapacitor, International Journal of Electrical Power & Energy Systems, vol. 3, no., pp. 573 58. [] L. Tolbert and T. Habetler, Novel multilevel inverter carrier-based PWM method, Industry Applications, IEEE, 999. [] I. Engineering and A. Issn, A comparative study of Total Harmonic Distortion in Multi level inverter topologies, vol., no. 3, pp. 6 37,. [] S. Kiruthika, S. Sudarsan, M. Murugesan, and B. Jayamanikandan, High Efficiency Three Phase Nine Level Diode Clamped Multilevel Inverter, vol., no. 3, pp. 3,. [3] H. W. Rahim, N. A.; Elias, M. F. M.; Ping, Three-Phase Cascaded Multilevel Inverter Based on Transistor-Clamped H-Bridge Power Cell, vol. 6, no. 5, pp. 6 67,. [] F. Z. Peng, S. Member, J. Lai, J. W. Mckeever, and J. Vancoevering, Fang Zheng Peng, vol. 3, no. 5, pp. 3 38, 996. [5] M. S. Rosli Omar, Mohammed Rasheed, Fundamental Studies of a Three Phase Cascaded H-Bridge and Diode Clamped Multilevel Inverters Using Matlab/Simulink, International Review of Automatic