Dual N-Channel V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A) a Q g (Typ.).35 at V GS = 4.5 V..36 at V GS =.5 V SOT-363 SC-7 (6-LEADS).9 FEATURES Halogen-free According to IEC 649-- Definition TrenchFET Power MOSFET % R g Tested Compliant to RoHS Directive /95/EC APPLICATIONS Load Switch and DC/DC Converter for Portable Devices High Speed Switching S 6 D Marking Code D D G D 3 5 4 G S PE XX Lot Traceability and Date Code Part # Code Y Y G G Top View Ordering Information: -T-GE3 (Lead (Pb)-free and Halogen-free) S N-Channel MOSFET S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (T A = 5 C, unless otherwise noted) Parameter Symbol Limit Unit Drain-Source Voltage V DS V Gate-Source Voltage V GS ± T C = 5 C. T Continuous Drain Current (T J = 5 C) C = 7 C.9 I D T A = 5 C b, c T A = 7 C.8 b, c A Pulsed Drain Current (t = 3 µs) I DM T C = 5 C.35 Continuous Source-Drain Diode Current I S T A = 5 C.5 b, c T C = 5 C.4 T C = 7 C.7 Maximum Power Dissipation P D W T A = 5 C.3 b, c T A = 7 C.3 b, c Operating Junction and Storage Temperature Range T J, T stg - 55 to 5 C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambient b, d t 5 s R thja 9 35 C/W Maximum Junction-to-Foot (Drain) Steady State R thjf 5 3 Notes: a. Based on T C = 5 C. b. Surface mounted on " x " FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 4 C/W. S-36-Rev. B, -Nov- This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
SPECIFICATIONS (T J = 5 C, unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage V DS V GS = V, I D = 5 µa V V DS Temperature Coefficient ΔV DS /T J 5 I D = 5 µa V GS(th) Temperature Coefficient ΔV GS(th) /T J -.6 mv/ C Gate-Source Threshold Voltage V GS(th) V DS = V GS, I D = 5 µa.6.5 V Gate-Source Leakage I GSS V DS = V, V GS = ± V ± na V Zero Gate Voltage Drain Current I DS = V, V GS = V DSS V DS = V, V GS = V, T J = 85 C µa On-State Drain Current a I D(on) V DS 5 V, V GS = 4.5 V A Drain-Source On-State Resistance a V R GS = 4.5 V, I D = A.95.35 DS(on) V GS =.5 V, I D =.3 A.55.36 Ω Forward Transconductance g fs V DS = V, I D = A 3 ms Dynamic b Input Capacitance C iss 6 Output Capacitance C oss V DS = V, V GS = V, f = MHz pf Reverse Transfer Capacitance C rss 7 V Total Gate Charge Q DS = V, V GS = V, I D = A 3 g.9.4 nc Gate-Source Charge Q gs V DS = V, V GS = 4.5 V, I D = A. Gate-Drain Charge Q gd. Gate Resistance R g f = MHz.4 4 Ω Turn-On Delay Time t d(on) 4 8 Rise Time t r V DD = V, R L =.5 Ω 3 Turn-Off DelayTime t d(off) I D.8 A, V GEN = V, R g = Ω Fall Time t f 9 8 Turn-On Delay Time t d(on) 6 ns Rise Time t r V DD = V, R L =.5 Ω 6 4 Turn-Off Delay Time t d(off) I D.8 A, V GEN = 4.5 V, Rg = Ω 3 Fall Time t f Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current I S T C = 5 C.35 Pulse Diode Forward Current a I SM A Body Diode Voltage V SD I S =.8 A.8. V Body Diode Reverse Recovery Time t rr 4 nc Body Diode Reverse Recovery Charge Q rr 8 6 I F =.8 A, di/dt = A/µs Reverse Recovery Fall Time t a 5 ns Reverse Recovery Rise Time t b 3 Notes: a. Pulse test; pulse width 3 µs, duty cycle %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. S-36-Rev. B, -Nov- This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
TYPICAL CHARACTERISTICS (5 C, unless otherwise noted). V GS = 5 V thru.5 V.8 I D - Drain Current (A) V GS = V V GS =.5 V I D - Drain Current (A).6.4. T C = 5 C T C = 5 C.5.5 V DS - Drain-to-Source Voltage (V) T C = - 55 C.5.5 V GS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics.4 8 R DS(on) - On-Resistance (Ω).34.8..6 V GS =.5 V V GS = 4.5 V C - Capacitance (pf) 6 4 C oss C iss C rss..5.5 I D - Drain Current (A) On-Resistance vs. Drain Current and Gate Voltage 5 5 V DS - Drain-to-Source Voltage (V) Capacitance V GS - Gate-to-Source Voltage (V) 8 6 4 I D = A V DS = 5 V V DS = V V DS = 6 V R DS(on) -On-Resistance (Normalized).8.5..9 I D = A V GS = 4.5 V V GS =.5 V.5.5 Q g - Total Gate Charge (nc) Gate Charge.6-5 - 5 5 5 75 5 5 T J - Junction Temperature ( C) On-Resistance vs. Junction Temperature S-36-Rev. B, -Nov- 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
TYPICAL CHARACTERISTICS (5 C, unless otherwise noted).5 I D = A I S - Source Current (A) T J = 5 C R DS(on) - On-Resistance (Ω).4.3. T J = 5 C T J = 5 C T J = 5 C....4.6.8.. V SD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage..8.6 3.4 4. 5 V GS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage..5 8 V GS(th) (V).9 I D = 5 μa Power (W) 6 4.75.6-5 - 5 5 5 75 5 5 T J -Temperature( C) Threshold Voltage... Time (s) Single Pulse Power (Junction-to-Ambient) Limited by R DS(on) * I D - Drain Current (A). μs ms ms ms T C = 5 C Single Pulse. BVDSS Limited DC, s, s. V DS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, Junction-to-Ambient 4 S-36-Rev. B, -Nov- This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
TYPICAL CHARACTERISTICS (5 C, unless otherwise noted)..9 I D - Drain Current (A).6.3 5 5 75 5 5 T C - Case Temperature ( C) Current Derating*.5.4.4.3 Power (W).3. Power (W)... 5 5 75 5 5 T C - Case Temperature ( C) Power Derating, Junction-to-Foot. 5 5 75 5 5 T A - Ambient Temperature ( C) Power Derating, Junction-to-Ambient * The power dissipation P D is based on T J(max.) = 5 C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. S-36-Rev. B, -Nov- 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
TYPICAL CHARACTERISTICS (5 C, unless otherwise noted) Normalized Effective Transient Thermal Impedance. Duty Cycle =.5...5. Single Pulse..... Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient Normalized Effective Transient Thermal Impedance. Duty Cycle =.5...5.. Single Pulse.... Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see /ppg?67876. 6 S-36-Rev. B, -Nov-
Package Information 6 5 4 3 e b e D E E -B- -A- A A c L Dim Min Nom Max Min Nom Max A.9..35.43 A..4 A.8..3.39 b.5.3.6. c..5.4. D.8...7.79.87 E.8..4.7.83.94 E.5.5.35.45.49.53 e.65bsc.6bsc e..3.4.47.5.55 L...3.4.8. 7 Nom 7 Nom A ECN: S-3946 Rev. B, 9-Jul- DWG: 555 Document Number: 754 6-Jul-
AN84 Dual-Channel LITTLE FOOT SC-7 6-Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel LITTLE FOOT power MOSFETs in the SC-7 package. These new devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 5 ma) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of on-resistance specifications in 6-pin versions. The new 6-pin SC-7 package enables improved on-resistance values and enhanced thermal performance. PIN-OUT Figure shows the pin-out description and Pin identification for the dual-channel SC-7 device in the 6-pin configuration. SOT-363 SC-7 (6-LEADS) applications for which this package is intended. For the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of % when using a -inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC7-6 The 6-pin SC-7 evaluation board (EVB) measures.6 inches by.5 inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6-pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC-7 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard -inch square FR4 PCB with copper on both sides of the board. S G D 3 Top View FIGURE. For package dimensions see outline drawing SC-7 (6-Leads) (http:///doc?754) BASIC PAD PATTERNS See Application Note 86, Recommended Minimum Pad Patterns With Outline Drawing Access for MOSFETs, (http:///doc?786) for the 6-pin SC-7. This basic pad pattern is sufficient for the low-power 6 5 4 D G S THERMAL PERFORMANCE Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-7 6-pin package measured as junction-to-foot thermal resistance is 3 C/W typical, 35 C/W maximum. The foot is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 4 lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) The typical Rθ JA for the dual 6-pin SC-7 is 4 C/W steady state. Maximum ratings are 46 C/W for the dual. All figures based on the -inch square FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-7 package at two different ambient temperatures. Document Number: 737 -Dec-3
AN84 SC-7 (6-PIN) 5 Room Ambient 5 C Elevated Ambient 6 C Dual EVB 4 P D T J(max) T A R JA P D 5o C 5 o C 4 o C W P D 3 mw P D T J(max) T A R JA P D 5o C 6 o C 4 o C W P D 5 mw NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-7 will handle power dissipation in excess of. W. Thermal Resistance (C/W) 3 Square FR4 PCB Testing -5-4 -3 - - Time (Secs) To aid comparison further, Figure illustrates the dual-channel SC-7 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of Rθ JA for the dual 6-pin SC-7 are as follows: LITTLE FOOT SC-7 (6-PIN) ) Minimum recommended pad pattern (see Figure ) on the EVB of.5 inches x.6 inches. ) Industry standard square PCB with maximum copper both sides. 58 C/W 43 C/W FIGURE. Comparison of Dual SC7-6 on EVB and Square FR4 PCB. The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to %. This fact confirms that the power dissipation is restricted with the package size and the Alloy 4 leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-7 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN85, (http:///doc?7334). Document Number: 737 -Dec-3
Application Note 86 RECOMMENDED MINIMUM PADS FOR SC-7: 6-Lead.67 (.7) APPLICATION NOTE.96 (.438).45 (.43).6 (.648).6 (.46).6 (.648). (.4) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index Document Number: 76 8 Revision: -Jan-8
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