Data Sheet Dual Picoampere Input Current Bipolar Op Amp Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 7.329.7 22 27 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com Data Sheet Dual Picoampere Input Current Bipolar Op Amp FEATURES High DC Precision V Max Offset Voltage.5 V/ C Max Offset Drift 2 pa Max Input Bias Current.5 V p-p Voltage Noise,. Hz to Hz 75 A Supply Current Available in -Lead PDlP and Surface-Mount (SOIC) Packages Available in Tape and Reel in Accordance with EIA-A Standard Quad Version: AD7 APPLICATIONS Low Frequency Active Filters Precision Instrumentation Precision Integrators CONNECTION DIAGRAM PDIP (N) and Plastic SOIC (R) Packages AMPLIFIER AMPLIFIER 2 OUTPUT IN IN 2 3 7 6 V 5 TOP VIEW V OUTPUT IN IN GENERAL DESCRIPTION The is a dual, low power, bipolar op amp that has the low input bias current of a JFET amplifier, but which offers a significantly lower I B drift over temperature. It utilizes superbeta bipolar input transistors to achieve picoampere input bias current levels (similar to FET input amplifiers at room temperature), while its I B typically only increases by 5 at 25 C (unlike a JFET amp, for which I B doubles every C for a increase at 25 C). The also achieves the microvolt offset voltage and low noise characteristics of a precision bipolar input amplifier. Since it has < 2 pa of bias current, the does not require the commonly used balancing resistor. Furthermore, the current noise is only 5 fa/ Hz, which makes this amplifier usable with very high source impedances. At 6 A max supply current (per amplifier), the is well suited for today s high density boards. The is an excellent choice for use in low frequency active filters in 2-bit and -bit data acquisition systems, in precision instrumentation, and as a high quality integrator. The is internally compensated for unity gain and is available in five performance grades. The J is rated over the commercial temperature range of C to +7 C. The A is rated for the extended industrial temperature range of C to +5 C. The is offered in two varieties of an -lead package: PDIP and surface-mount (SOIC). PRODUCT HIGHLIGHTS. The is a dual low drift op amp that offers JFET level input bias currents, yet has the low I B drift of a bipolar amplifier. It may be used in circuits using dual op amps such as the LT2. 2. The provides both low drift and high dc precision. 3. The can be used in applications where a chopper amplifier would normally be required but without the chopper s inherent noise. TYPICAL I B na. TYPICAL JFET AMP. 55 +25 + +25 TEMPERATURE C Figure. Input Bias Current vs. Temperature Rev. G Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 96, Norwood, MA 262-96, U.S.A. Tel: 7.329.7 22 2 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
SPECIFICATIONS (@ T A = +25 C, V CM = V and 5 V dc, unless otherwise noted.) J/A Parameter Conditions Min Typ Max Unit INPUT OFFSET VOLTAGE Initial Offset 3 µv Offset T MIN to T MAX 5 µv vs. Temperature, Average TC.2.5 µv/ C vs. Supply (PSRR) V S = ±2 V to ± V 32 db T MIN to T MAX V S = ±2.5 V to ± V 6 26 db Long Term Stability.3 µv/month INPUT BIAS CURRENT V CM = V 5 2 pa V CM = ±3.5 V 25 pa vs. Temperature, Average TC.3 pa/ C T MIN to T MAX V CM = V 3 pa T MIN to T MAX V CM = ±3.5 V pa INPUT OFFSET CURRENT V CM = V 3 5 pa V CM = ±3.5 V 25 pa vs. Temperature, Average TC.6 pa/ C T MIN to T MAX V CM = V 25 pa T MIN to T MAX V CM = ±3.5 V 35 pa MATCHING CHARACTERISTICS Offset Voltage 5 µv T MIN to T MAX 25 µv Input Bias Current 2 3 pa T MIN to T MAX 5 pa Common-Mode Rejection 6 db T MIN to T MAX 6 db Power Supply Rejection 6 db T MIN to T MAX db Crosstalk (Figure 2a) @ f = Hz R L = 2 kω 5 db FREQUENCY RESPONSE Unity Gain Crossover Frequency. MHz Slew Rate G =.5 V/µs T MIN to T MAX.5 V/µs INPUT IMPEDANCE Differential 2 MΩ pf Common Mode 3 2 GΩ pf INPUT VOLTAGE RANGE Common-Mode Voltage ±3.5 ± V Common-Mode Rejection Ratio V CM = ±3.5 V 32 db T MIN to T MAX 2 db INPUT CURRENT NOISE. Hz to Hz 3 pa p-p f = Hz 5 fa/ Hz INPUT VOLTAGE NOISE. Hz to Hz.5 µv p-p f = Hz 7 nv/ Hz f = khz 5 22 nv/ Hz OPEN-LOOP GAIN V O = ±2 V R LOAD = kω 2 2 V/mV T MIN to T MAX 5 5 V/mV V O = ± V R LOAD = 2 kω 2 V/mV T MIN to T MAX 5 V/mV OUTPUT CHARACTERISTICS Voltage Swing R LOAD = kω ±3 ± V T MIN to T MAX ±3 ± V Current Short Circuit ± 5 ma Capacitive Load Drive Capability Gain = +, pf 2
SPECIFICATIONS (continued) J/A Parameter Conditions Min Typ Max Unit POWER SUPPLY Rated Performance ± 5 V Operating Range ±2. ± V Quiescent Current, Total.75.2 ma T MIN to T MAX.. ma TRANSISTOR COUNT Number of Transistors 9 NOTES Bias current specifications are guaranteed maximum at either input. 2 Input bias current match is the difference between corresponding inputs (I B of IN of Amplifier minus I B of IN of Amplifier 2). CMRR match is the difference between OS CM for Amplifier and OS2 CM for Amplifier 2, expressed in db. PSRR match is the difference between OS SUPPLY All min and max specifications are guaranteed. Specifications subject to change without notice. for Amplifier and OS2 SUPPLY ABSOLUTE MAXIMUM RATINGS Supply Voltage................................ ± V Internal Power Dissipation (Total: Both Amplifiers) 2.................... 65 mw Input Voltage................................... ±V S Differential Input Voltage 3...................... +.7 V Output Short Circuit Duration................ Indefinite Storage Temperature Range (N, R)....... 65 C to +25 C Operating Temperature Range J............................. C to +7 C A............................ C to +5 C Lead Temperature (Soldering secs)............. 3 C NOTES Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for device in free air: -Lead PDIP Package: θ JA = C/W -Lead Small Outline Package: θ JA = 55 C/W 3 The input pins of this amplifier are protected by back-to-back diodes. If the differential voltage exceeds ±.7 V, external series protection resistors should be added to limit the input current to less than 25 ma. for Amplifier 2, expressed in db. ESD CAUTION OUTPUT A INPUT A METALIZATION PHOTOGRAPH Dimensions shown in inches and (mm). Contact factory for latest dimensions. 2. (3.) 7 OUTPUT B +INPUT A 3 6 INPUT B 5 +INPUT B.7 (.) 3
Typical Performance Characteristics (Default Conditions: 5 V, C L = 5 pf, G = 2, R g = R f = kω, R L = 2 kω, V O = 2 V p-p, Frequency = MHz, T A = 25 C) SAMPLE SIZE: 3 SAMPLE SIZE: 5 SAMPLE SIZE: 2 NUMBER OF UNITS 6 NUMBER OF UNITS 6 NUMBER OF UNITS 6 2 2 2 INPUT OFFSET VOLTAGE V 6 6 INPUT BIAS CURRENT pa 2 6 6 2 INPUT OFFSET CURRENT pa TPC. Typical Distribution of Input Offset Voltage TPC 2. Typical Distribution of Input Bias Current TPC 3. Typical Distribution of Input Offset Current INPUT COMMON-MODE VOLTAGE LIMIT Volts (REFERRED TO SUPPLY VOLTAGES) V S.5..5.5..5 5 5 2 SUPPLY VOLTAGE Volts TPC. Input Common-Mode Voltage Range vs. Supply Voltage OUTPUT VOLTAGE Volts p-p 35 3 25 2 5 5 k k k M TPC 5. Large Signal Frequency Response OFFSET VOLTAGE DRIFT V/ C. SOURCE RESISTANCE MAY BE EITHER BALANCED OR UNBALANCED FOR INDUSTRIAL TEMPERATURE RANGE. k k k M M M SOURCE RESISTANCE TPC 6. Offset Voltage Drift vs. Source Resistance NUMBER OF UNITS 2 6 2 SAMPLE SIZE: 375 55 C TO 25 C.... OFFSET VOLTAGE DRIFT V/ C TPC 7. Typical Distribution of Offset Voltage Drift CHANGE IN OFFSET VOLTAGE V 3 2 2 3 WARM-UP TIME Minutes TPC. Change in Input Offset Voltage vs. Warm-Up Time 5 INPUT BIAS CURRENT pa 6 2 2 POSITIVE I B NEGATIVE I B 6 5 5 5 5 COMMON-MODE VOLTAGE Volts TPC 9. Input Bias Current vs. Common-Mode Voltage
VOLTAGE NOISE nv/ Hz CURRENT NOISE fa/ Hz 2M k V OUT.5 V TPC. Input Noise Voltage Spectral Density TPC. Input Noise Current Spectral Density 5 TIME Seconds TPC 2.. Hz to Hz Noise Voltage 6 6 QUIESCENT CURRENT A 9 7 +25 C +25 C 55 C CMRR db 2 6 2 PSRR db 2 6 + PSRR PSRR 6 5 5 2 SUPPLY VOLTAGE Volts TPC 3. Quiescent Supply Current vs. Supply Voltage. k k k M TPC. Common-Mode Rejection Ratio vs. Frequency 2. k k k M TPC 5. Power Supply Rejection Ratio vs. Frequency M OPEN-LOOP VOLTAGE GAIN M +25 C 55 C +25 C OPEN-LOOP VOLTAGE GAIN db 2 6 2 GAIN PHASE 3 6 9 2 5 2 PHASE SHIFT Degrees OUTPUT VOLTAGE SWING Volts (REFERRED TO SUPPLY VOLTAGES).5..5 +.5 +. +.5 k 2 6 LOAD RESISTANCE k TPC 6. Open-Loop Gain vs. Load Resistance vs. Load Resistance 2 2.. k k k M M TPC 7. Open-Loop Gain and Phase Shift vs. Frequency 5 5 2 SUPPLY VOLTAGE Volts TPC. Output Voltage Swing vs. Supply Voltage 5
CROSSTALK db 2 CLOSED-LOOP OUTPUT IMPEDANCE.. AV = I OUT = +ma AV = + 6 k k k Figure 2a. Crosstalk vs. Frequency. F. k k Figure 3. Magnitude of Closed-Loop Output Impedance vs. Frequency k 2 3 SINE WAVE GENERATOR /2 2k. F R L 2k V OUT 2V p-p V IN /2 R F. F R L 2k V OUT C L 2.2k 6 5 /2 7 F. F V OUT2 SQUARE WAVE INPUT. F Figure a. Unity Gain Follower (For large signal applications, resistor R F limits the current through the input protection diodes.) CROSSTALK = 2 LOG V OUT2 V OUT 2dB Figure 2b. Crosstalk Test Circuit Figure b. Unity Gain Follower Large Signal Pulse Response, R F = kω, C L =, pf Figure c. Unity Gain Follower Small Signal Pulse Response, R F = Ω, C L = pf Figure d. Unity Gain Follower Small Signal Pulse Response, R F = Ω, C L = pf 6
k V IN SQUARE WAVE INPUT k /2 + +. F.µF R L 2.5k Figure 5a. Unity Gain Inverter Connection V OUT C L Figure 5b. Unity Gain Inverter Large Signal Pulse Response, C L =, pf Figure 5c. Unity Gain Inverter Small Signal Pulse Response, C L = pf Figure 5d. Unity Gain Inverter Small Signal Pulse Response, C L = pf Figure 6 shows an in-amp circuit that has the obvious advantage of requiring only one, rather than three op amps, with subsequent savings in cost and power consumption. The transfer function of this circuit (without R G ) is R VOUT = ( VIN VIN2 ) + R3 for R = R and R2 = R3. Input resistance is high, thus permitting the signal source to have an unbalanced output impedance. V IN V IN2 R 9.9k R P * k R P * k 3 + A R G (OPTIONAL) R2 R3 R. FF 2 5 /2 9.9k + + /2 A2 V OUT = (V IN V IN2 ) (+ R ) + ( 2R ) R3 R FOR R = R, R2 = R3 G. FF * OPTIONAL *OPTIONAL INPUT INPUT PROTECTION PROTECTION RESISTOR RESISTOR FOR FOR GAINS GAINS GREATER GREATER THAN THAN OR INPUT OR INPUT VOLTAGES VOLTAGES EXCEEDING EXCEEDING THE THE SUPPLY SUPPLY VOLTAGE. VOLTAGE. 6 7 OUTPUT Figure 6. Two Op Amp Instrumentation Amplifier Furthermore, the circuit gain may be fine trimmed using an optional trim resistor, R G. Like the three op amp circuit, CMR increases with gain, once initial trimming is accomplished but 7 CMR is still dependent upon the ratio matching of Resistors R through R. Resistor values for this circuit, using the optional gain resistor, R G, can be calculated using R= R = 9.9 kω 9.9 kω R2 = R3 =.9 G 99. kω R G =.6 G where G = The desired circuit gain. Table I provides practical % resistance values. Note that without resistor R G, R2 and R3 = 9.9 kω/g. Table I. Operating Gains of Amplifiers A and A2 and Practical % Resistor Values for the Circuit of Figure 6 Circuit Gain Gain of A Gain of A2 R2, R3 R, R... 99 kω 9.9 kω.33..33 5 kω 9.9 kω.5 3..5 kω 9.9 kω 2. 2. 2. 9.9 kω 9.9 kω... 5.9 kω 9.9 kω... 99 Ω 9.9 kω. 9.9 Ω 9.9 kω For a much more comprehensive discussion of in-amp applications, refer to the Instrumentation Amplifier Applications Guide available free from Analog Devices, Inc.
INPUT R M R2 M *WITHOUT THE NETWORK, PINS AND 2, AND 6 AND 7 OF THE ARE TIED TOGETHER. CAPACITORS C AND C2 ARE SOUTHERN ELECTRONICS MPCC, POLYCARB 5%, 5V C 3 + C2 /2 2 R5 2M C3 R3 R M M 5 /2 C. F 6 C5. F OPTIONAL BALANCE RESISTOR NETWORKS* + R6 2M 7. F C6. F OUTPUT Figure 7. Hz, -Pole Active Filter Hz, -Pole, Active Filter Figure 7 shows the in an active filter application. An important characteristic of the is that both the input bias current, input offset current, and their drift remain low over most of the op amp s rated temperature range. Therefore, for most applications, there is no need to use the normal balancing resistor. Adding the balancing resistor enhances performance at high temperatures, as shown by Figure. OFFSET VOLTAGE OF FILTER CIRCUIT (RTI) V 2 6 6 2 WITHOUT OPTIONAL BALANCE RESISTOR, R3 WITH OPTIONAL BALANCE RESISTOR, R3 2 TEMPERATURE C Figure. V OS vs. Temperature Performance of the Hz Filter Table II. Hz, -Pole, Low Pass Filter Recommended Component Values Section Section 2 Desired Low Frequency Frequency C C2 C3 C Pass Response (Hz) Q (Hz) Q ( F) ( F) ( F) ( F) Bessel.3.522.6.6.6.7.6.66 Butterworth..5..3.72.7.6.69. db Chebychev.6.69.9 2..3.9.733.35.2 db Chebychev.63.66.9 2..3.2.23.37.5 db Chebychev.5.75.932 2.9.6.29..29. db Chebychev.92.75.925 3.56.5.26.23.22 NOTE Specified Values are for a 3 db point of. Hz. For other frequencies simply scale capacitors C through C directly, i.e. for 3 Hz Bessel response, C =.37 µf, C2 =.357 µf, C3 =.533 µf, C =.25 µf.
Data Sheet OUTLINE DIMENSIONS. (.6).365 (9.27).355 (9.2).2 (5.33) MAX.5 (3.).3 (3.3).5 (2.92).22 (.56). (.6). (.36). (2.5) BSC 5.2 (7.).25 (6.35).2 (6.).5 (.3) MIN SEATING PLANE.5 (.3) MIN.6 (.52) MAX.5 (.3) GAUGE PLANE.325 (.26).3 (7.7).3 (7.62).3 (.92) MAX.95 (.95).3 (3.3).5 (2.92). (.36). (.25). (.2).7 (.7).6 (.52).5 (.) COMPLIANT TO JEDEC STANDARDS MS- CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 9. -Lead Plastic Dual-in-line Package [PDIP] Narrow Body (N-) Dimensions shown in inches and (millimeters) 766-A 5. (.96). (.9). (.57) 3. (.97) 5 6.2 (.2) 5. (.22).25 (.9). (.) COPLANARITY. SEATING PLANE.27 (.5) BSC.75 (.6).35 (.532).5 (.2).3 (.22).25 (.9).7 (.67).5 (.96).25 (.99).27 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS-2-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model Temperature Range Package Description Package Option AR C to +5 C -Lead SOIC_N R- ARZ C to +5 C -Lead SOIC_N R- ARZ-REEL C to +5 C -Lead SOIC_N, 3 Tape and Reel R- ARZ-REEL7 C to +5 C -Lead SOIC_N, 7 Tape and Reel R- JNZ C to + 7 C -Lead PDIP N- JRZ C to + 7 C -Lead SOIC_N R- JRZ-REEL C to + 7 C -Lead SOIC_N, 3 Tape and Reel R- JRZ-REEL7 C to + 7 C -Lead SOIC_N, 7 Tape and Reel R- 27-A 9
Data Sheet REVISION HISTORY 7/2 Rev. F to Rev. G Changed Plastic Mini-DIP to PDIP... Universal Updated Outline Dimensions... /27 Rev. E to Rev. F Changes to Figure 6... 6 Updated Outline Dimensions... Changes to Ordering Guide... /23 Rev. D to Rev. E Removed K Version... Universal Changes to Features and Product Description... Renumbered TPC s... Renumbered Figured... 6 Updated Outline Dimensions... 9 /22 Rev. C to Rev. D Deleted -Lead CERDIP (Q-) Package... Universal Changes to Features and Product Description... Changes to Specifications Section... 2 Changes to Absolute Maximum Ratings Section... 3 Changes to Ordering Guide... 3 Updated Outline Dimensions... 5 2 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D2--7/(G) Rev. G Page of