Volume-5, Issue-6, December-2015 International Journal of Engineering and Management Research Page Number: 484-493 Implementation of Multicarrier Based Control Schemes for Cascaded 9-Levels Multilevel Inverter Pratigya Sharma 1, Prof. Pawan Pandey 2 1 M.Tech Student, Department of Electrical and Electronics Engineering, Malwa Institute of Technology, Indore, INDIA 2 Sr. Assistant Professor, Malwa Institute of Technology, Indore, INDIA ABSTRACT In this proposed work upon the various Multi Carrier Based Pulse width (MCBPW) modulation techniques implemented by single phase multilevel inverter and their comparisons. The main focus in this paper is reducing of total harmonic distortion (THD). The multilevel inverter is used to improve the voltage quality by reducing the harmonics, as the number of voltage levels of multilevel inverter (MLI) is increased the harmonics are reduced and hence losses are minimized significantly, increasing the efficiency of the system. In proposed paper generation of carrier based PWM scheme using IPD, POD and APOD. This control signal used in multilevel inverter (MLI), and 9-level inverter system modeled and simulated using MATLAB simulator. The test results verify the effectiveness of the proposed strategy in terms of low distorted voltage with low-switching losses and total harmonic reduces in output voltage with increasing the number of voltage level. Keywords MLI, THD, IPD, POD and APOD I. INTRODUCTION The Inverter is a device that converts electrical power from DC to AC form using electronic circuits. Generally simple inverter gives 2 or 3 level output voltage. Multilevel inverter gives 3 or more output voltage levels. It produces a stepped output voltage with reduced harmonic distortion when compared to a 2 level inverter. Numerous industrial applications have begun to require higher power apparatus in recent years. Some medium voltage motor drives and utility applications require medium voltage and megawatt power level. For a medium voltage grid, it is troublesome to connect only one power semiconductor switch directly. As a result, a multilevel power converter structure has been introduced as an alternative in high power and medium voltage situations subsequently; several multilevel converter topologies have been developed. Multilevel Inverter (MLI) offers a number of advantages when compared to the conventional two level inverter in terms of improved DC link utilization and harmonic spectrum. The stepped approximation of the sinusoidal output waveform with higher levels reduces the harmonic distortion of the output waveform and the stresses across the semiconductor devices and also allows higher voltage/current and power ratings. The reduced switching frequency of each individual switch of the inverter also reduces the switching losses and improves the efficiency of the inverter. In recent years, multilevel inverters have gained popularity with medium and high power ratings. Renewable energy sources such as photovoltaic, wind, and fuel cells can be interfaced to a multilevel converter system. Many multilevel converter topologies have been proposed during the last two decades. Research has engaged novel converter topologies and unique modulation schemes. In recent era there is huge power requirement in industries and other areas. Multilevel inverter has become popular to fulfill power requirement due to advantage of high power quality waveforms, low electromagnetic compatibility. II. DIFFERENT MODULATION METHODS CONTROLLING OF MLI Mainly the power electronic converters are operated in the switched mode, means the switches among the converter are invariably in either one of the 2 states, turned off (no current flows), or turned on (saturated with solely a tiny voltage drop across the switch). The operation within the linear region other than for the unavoidable transition from conducting to non 484 Copyright 2011-15. Vandana Publications. All Rights Reserved.
conducting incurs an undesirable loss of efficiency and an intolerable rise in power switch power dissipation. A. Pulse Width Modulation (PWM) This happens rapidly enough that the inductors and capacitors at the input and output nodes of the converter average or filter the switched signal. Switched element is attenuated and the desired DC or low frequency AC component is retained. This method is known as Pulse Width Modulation (PWM), since the required average worth is controlled by modulating the width of the pulses. PWM Techniques The fundamental methodology of pulse width modulation (PWM) are divided into the Traditional voltage source and current regulated strategies. Voltage-source strategies more easily lend themselves to digital signal processor (DSP) or programmable logic device (PLD) implementation[39]. Fig 1.1. Pulse-width modulation This type of modulation is pattern that encodes information as variations in the instantaneous phase of a carrier wave. 2. Level shifted multi carrier modulation In level shifted multi carrier modulation (m-1) carrier waves are used for m- level.these triangular carrier also having same frequency and amplitude. The (m-1) triangular carriers are vertically disposed such that the bands they occupy are contiguous. There are three alternative PWM strategies with different phase relationships for the level-shifted multicarrier modulation. C. In Phase Disposition (IPD) This technique involves a number of carriers (ml) which are all in phase accordingly. The phase disposition PWM technique is illustrated in - The rules for the in phase disposition methodology, once the number of level N = 3, are The N 1 = 3-1=2 carrier waveforms are organized so that each carrier is in phase. The converter is switched to +Vdc/ 2 once the reference is greater than both carrier waveforms. The convertor is switched to zero when the reference is greater than the lower carrier waveform however less than the upper carrier waveform. The converter is switched to - Vdc/ 2 once the reference is less than both carrier waveforms. In the carrier -based implementation, at every instant of time the modulation signals are compared with the carrier and depending on which is greater, the switching pulses are generated. However, current controls usually rely on event scheduling and are thus analog implementations that will solely be reliably operated up to a certain power level. In distinct current -regulated strategies the harmonic performance is not as good as that of voltage-source strategies. A sample PWM methodology is delineated below. There are many modulation techniques are used for multilevel inverter to synthesize the output voltage as close as possible to the sinusoidal wave form. Its main use is to allow the control of the ability provided to electrical devices. The control techniques developed for harmonic reduction and switching loss minimization [39]. B. Multi Carrier Pulse Width Modulation Techniques The carrier-based modulation schemes for multilevel inverters can be generally classified into two categories: 1. Phase -shifted 2. Level shifted 1. Phase shifted multi carrier modulation using the formula is: 360 /(m-1) Fig. 1.2 : Switching pattern produced using the IPD carrier-based PWM scheme D. Phase Opposition Disposition (POD) For phase opposition disposition (POD) modulation all carrier waveforms above zero reference are in phase and are 180 out of phase with those below zero axis. The rules for the phase opposition disposition method, when the number of level N = 3 are 485 Copyright 2011-15. Vandana Publications. All Rights Reserved.
1.The N 1 = 2 carrier waveforms are organized so all carrier waveforms above zero are in phase and are 180 out of phase with those below zero. 2.The converter is switched to + Vdc/ 2 once the reference is greater than both carrier waveforms. 3.The converter is switched to zero once the reference is greater than the lower carrier waveform but less than the upper carrier waveform. 4.The converter is switched to - Vdc / 2 once the reference is less than each carrier waveforms. As seen from Figure 3.10 the figure illustrates the switching functions produced by POD carrier based PWM scheme. In PWM scheme there are two triangles, upper triangle magnitude from 1 to 0 and the lower triangle from 0 to 1 and these 2 triangle waveforms are in out of phase. Once the modulation signal is greater than both the carrier waveforms, S1ap and S2ap are turned on and the converter switches to positive node voltage and once the reference is less than the upper carrier waveform however greater than the lower carrier, S2ap and S1an are turned on and the converter power switches to neutral purpose. when the reference is lower than each carrier waveforms, S1an and S2an are turned on and the converter switches to negative node voltage. E. Alternate Phase Opposition Disposition (APOD) In case of alternate phase disposition (APOD) modulation, every carrier waveform is in out of phase with its neighbor carrier by 180. Since APOD and POD schemes in case of 3 level inverter are an equivalent, 5 level inverter is considered to discuss about the APOD methodology. The foundations for APOD methodology, once the number of level N = 5, are 1. The N 1 = four carrier waveforms are organized so that each carrier waveform is in out of phase with its neighbor carrier by 180. The converter switches to + Vdc/ 2 when the reference is greater than all the carrier waveforms. 2. The converter switches to Vdc/ four once the reference is less than the uppermost carrier waveform and greater than all other carriers. 3. The converter switches to 0 when the reference is less than 2 the 2} uppermost carrier waveform and greater than two lowermost carriers. 4. The converter switches to - Vdc/ four when the reference is greater than the lowermost carrier waveform and lesser than all other carriers. 5. The converter switches to -Vdc/ 2 when the reference is lesser than all the carrier waveforms. Fig. 1.4: Switching pattern produced using the APOD carrier -based PWM scheme. III. PROPOSED 9-LEVEL DESIGN In case of 9 level Asymmetric Cascaded MLI three DC sources are used having 2 same and third different and 12 power switches are used. The Asymmetric Multilevel Inverter increases the number of levels in the output and reduces the number of input DC sources required [3]. IGBT is used as semiconductor switch for designing the inverter circuit. It has the high power rating, less conduction loss and less switching loss. These topology uses level-shifted multi carrier based new PWM method, used to produced a nine- level output voltage. Fig.1.3. Switching pattern produced using the POD carrier -based PWM scheme: 486 Copyright 2011-15. Vandana Publications. All Rights Reserved.
Fig. 1.5: Simulink model of 7-level inverter The simulink model of 9- level multilevel inverter implemented in Matlab-Simulink is shown in Figure 1.5 and 1.6.It is basically a Cascaded H-bridge type of Multilevel Inverter. Here the used DC source is Asymmetrical type, Asymmetrical source defines that it has different value of DC sources used in an Inverter. For 9 level inverter the DC sources are 100V, 200v, and 100 V respectively. The simulink model for 9- level multilevel inverter shown in figure 1.5 and 1.6 Fig. 1.6: Simulink model of 9 level with IM Working of this inverter is nothing but how we make power switches (IGBTs) ON and OFF as per voltage level desired. We have generated switching pulses to obtain staircase output voltage which resembles nearly equal to sine wave. For different switching angles the power circuit behaves differently producing different waveforms. In this topology, we have generated 9 voltage levels as 0, 100V, 200V, 300V and 400V.The circuit working for each level is described below: For 0 voltage level Since S1and S3 are ON or all power switches are OFF, the current will cancelled out in the bridge and hence it gives 0 V voltage level. For 100V voltage level Since S1, S10, S12, S6, S8 and S2 are ON and remaining switches are OFF, the voltage across load will gives 100V level. For 200V voltage level Since S1, S4, S5, S6, S10 & 487 Copyright 2011-15. Vandana Publications. All Rights Reserved.
S12 are ON and remaining switches are OFF, the voltage across load will gives 200V level. For 300V voltage level Since S1, S2, S5, S6, S10 & S12 are ON and remaining switches are OFF, the voltage across load will gives 300V level For 400Vvoltage level Since S1, S2, S5, S6, S9 & S10 are ON and remaining switches are OFF, the voltage across load will gives 400V level For 0V voltage level Since S1and S3 are ON or all power switches are OFF, the current will cancelled out in the bridge and hence it gives 0 V voltage level For- 100V voltage level Since S3, S4, S6, S8, S10, and S12 are ON and remaining switches are OFF, the voltages across load will gives -100V level. For -200V voltage level Since S2, S4, S7, S8 S10, and S12are ON and remaining switches are OFF, the voltage across load will gives -200V level. For- 300V voltage level Since S3, S4, S7, S8, S10, & S12 are ON and remaining switches are OFF, the voltages across load will gives -300V level. I. For- 300V voltage level For -400V voltage level Since S3, S4, S7, S8, S11, & S12 are ON and remaining switches are OFF, the voltages across load will gives -400V level For detail operation of new topology can also be understand by analyzing table no. 1.1 which is given below. Here 0 means switches are OFF and 1 means switches are ON IV. RESULT SWITCHING SCHEME In this section, a switching procedure is developed so the topology may be modulated with the extent shifted pulse width modulation (PWM). This modulation schemes can be applied to the cascaded H- bridge (CHB) inverters. An m-level CHB inverter using level-shifted multicarrier modulation scheme needs (m-1) triangular carriers, all having an equivalent frequency and amplitude. The (m-1) triangular carriers are vertically disposed specified the bands they occupy are contiguous. There are 3 different PWM methods with different phase relationships for the level-shifted multicarrier modulations are developed shown in figure 1.7, 1.8 and 1.9. (i) In-phase disposition (IPD), where all carrier waveforms are in phase. (ii) Phase opposition disposition (POD), where all carrier waveforms higher than zero reference are in phase but in opposition with those below the zero reference. (iii) Alternative phase opposite disposition (APOD), where all carriers are alternatively in opposite disposition. B. Generation of Reference and Carrier Waveform for 9- CLSPWM Inverter Table no. 5.1 Switching pattern for asymmetrical cascaded nine level inverter Table 1.2: System parameters for nine level Inverter System Parameters Value Reference frequency Carrier frequency Load resistance Load inductance 50 Hz 1.2K Hz 1Ω 1 mh Fig.1.7: Reference and carrier waveform for IPD CLSPWM DC Sources 100V, 200V,300V 488 Copyright 2011-15. Vandana Publications. All Rights Reserved.
Simulation Result of (9-Level) ACMLI with IM Using IPD- CLSPWM Figure 1.8: Reference and carrier waveform for POD CLSPWM Figure 1.10: Output phase voltage waveform for asymmetric (9-level) MLI using IPD-CLSPWM Figure 1.9: Reference and carrier waveform for APOD CLSPWM Also shows the output voltage of nine-level asymmetrical cascaded multilevel inverters cascaded is compared for the PD, POD, APOD techniques,and it also shows the THD profile and performance of the circuit with IM for three pwm techniques, and also the compare all result with seven-level MLI. Cascaded multi level inverter shows the lowest THD profile without any type of filter and also any type of dependency of inductor and capacitor used for smooth the current wave form and due to less number of switching devices gate firing circuit also reduced that s why total cost and performance has been increased. Figure1.11: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using IPD-CLSPWM 489 Copyright 2011-15. Vandana Publications. All Rights Reserved.
Figure 1.13: Output phase voltage waveform for asymmetric (9-level) MLI using POD-CLSPWM Figure 1.12: Motor output of (9-level) cascaded MLI using IPD-CLSPWM Simulation Result of (9-Level) ACMLI with IM Using POD-CLSPWM Figure 1.14: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using POD-CLSPWM 490 Copyright 2011-15. Vandana Publications. All Rights Reserved.
Figure 1.17: FFT analysis of voltage waveform of asymmetric (9-level) cascaded MLI using APOD- CLSPWM Figure 1.15: Motor output of (9-level) cascaded MLI using POD-CLSPWM Simulation Result of (9-Level) ACMLI with IM Using APOD- CLSPWM Figure 1.16: Output phase voltage waveform for asymmetric (9-level) MLI using APOD-CLSPWM Figure 1.18: Motor output of (9-level) cascaded MLI using APOD-CLSPWM V. CONCLUSION In this paper, the multicarrier pulse width modulation (PWM) techniques for 7-level & 9-level have 491 Copyright 2011-15. Vandana Publications. All Rights Reserved.
been presented. Performance factor like total harmonic distortion (THD) of the output voltage of asymmetric cascade multi level inverter (CMLI) have been evaluated, presented and analyzed. The total harmonic distortion (THD) of the output voltage of unbalanced cascade multi level inverter (CMLI) is studied under different techniques such as IPD, POD & APOD, compare for seven and nine level multi level inverter (MLI) and less total harmonic distortion (THD) is observed for APOD techniques for 7- level and IPD techniques best for 9-level multi level inverter (MLI). Therefore, it concluded that It that the 9- level cascade multi level inverter (CMLI) provide a lower percentage total harmonic distortion (THD) as compared to 7-level multi level inverter (MLI). The harmonic distortions present in the output voltage waveforms were experiential and calculate from side to side Fast Fourier Transform (FFT) analysis tool in Matlab and simulink. In this work is it shown that the reducing the total harmonic distortion (THD) in multilevel inverter (MLI) with increasing the no voltage level and using multicarrier pulse width modulation (PWM) techniques,the work can be expanded in following area. The proposed inverter has been operated by only three control schemes, namely IPD, POD and APOD PWM schemes. Applying the improved switching techniques can still improve the output quality. So potential of proposed version could be explored by adopting different switching techniques. The proposed version of CMI is only adopted for harmonic reduction applications. In fact the merits of CMI can be used to build for photovoltaic/grid connected systems. So it can extend to multiple applications like STATCOM, SSSC and UPQC etc. REFERENCES [1] J. S. Lai and F. Z. Peng, Multilevel converters A new breed of power converters, IEEE Trans. Ind. Applicat., vol. 32, pp. 1098 1107, May/June 1996. [2] J. Rodriguez, J.-S. Lai, and F. Z. Peng, "Multilevel inverters: a survey of topologies, controls, and applications," IEEE Trans. Ind. Electron., vol. 49, pp. 724-738, 2002. [3] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, "Multilevel converters for large electric drives," IEEE Trans. Ind. Applicat., vol. 35, pp. 36-44, 1999. [4] H. Stemmler. Power electronics in electric traction applications. IEEE conference of Industrial Electronics, Control and Instrumentation, IECON 93, 2:7 07 713, 1993. [5] H. Fujita, S. Tominaga, and H. Akagi. Analysis and design of an advanced static VAR compensator using quad-series voltage-source inverters. IEEE Industry Apps Meeting, 3:2565 2572, 1995. [6] Y. Yoshioka, S. Konishi, N. Eguchi, M. Yamamoto, K. Endo, K. Maruyama, and K. Hino. Self-commutated static flicker compensator for arc furnaces. In IEEE Applied Power Electronics Conference, volume 2, pages 891 897, 1996. [7] L. Gyugyi, "Power electronics in electric utilities: static var compensators.," Proc. IEEE, vol. 76, pp. 3, 1987. [8] Peter W. Hammond. A new approach to enhance power quality for medium voltage AC drives. IEEE Trans. Industry Applications, 33(1):202 208, January 1997. [9] M. F. Escalante, J. C. Vannier, and A. Arzande Flying Capacitor Multilevel Inverters and DTC Motor Drive Applications, IEEE Transactions on Industry Electronics, vol. 49, no. 4, Aug. 2002, pp. 809-815. [10] L. M. Tolbert, F. Z. Peng, Multilevel Converters as a Utility Interface for Renewable Energy Systems, in Proceedings of 2000 IEEE Power Engineering Society Summer Meeting, pp. 1271-1274. [11] L. M. Tolbert, F. Z. Peng, T. G. Habetler, A Multilevel Converter-Based Universal Power Conditioner, IEEE Transactions on Industry Applications, vol. 36, no. 2, Mar./Apr. 2000 pp.596-603. [12] L. M. Tolbert, F. Z. Peng, T. G. Habetler, Multilevel Inverters for Electric Vehicle Applications, IEEE Workshop on Power Electronics in Transportation, Oct 22-23, 1998, Dearborn, Michigan, pp. 1424-1431. [13] In-Dong Kim, Eui-Cheol Nho,, Heung-Geun Kim,, and Jong Sun Ko,. A Generalized Undeland Snubber for Flying Capacitor Multilevel Inverter and Converter.IEEE transactions on industrial electronics, vol. 51, no. 6, December 2004. [14] R. H. Baker and L. H. Bannister, Electric Power Converter, U.S. Patent 3 867 643, Feb. 1975. [15] A. Nabae, I. Takahashi, and H. Akagi, A New Neutral-point Clamped PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-17, pp. 518-523, Sept./Oct. 1981. [16] F. Z. Peng and J. S. Lai, Multilevel Cascade Voltagesource Inverter with Separate DC source, U.S. Patent 5 642 275, June 24, 1997. [17] N. S. Choi, J. G. Cho, and G. H. Cho, A general circuit topology of multilevel inverter, in Proc. IEEE PESC 91, 1991, pp. 96 103. [18] T. A. Meynard and H. Foch, Multilevel conversion: High voltage choppers and voltage source inverters, in Proc. IEEE PESC 92, 1992, pp. 397 403. [19] F. Z. Peng, J.-S. Lai, J. Mckeever, and J. VanCoevering, A multilevel voltage-source inverter with separate DC source for static var generation, in Conf. Rec. IEEE-IAS Annu. Meeting, 1995, pp. 2541 2548. [20] P. W. Hammond, "Four-quadrant AC-AC drive and method," U.S. Patent 6 166 513, Dec. 2000. [21] M. F. Aiello, P. W. Hammond, and M. Rastogi, "Modular multi-level adjustable supply with series connected active inputs," U.S. Patent 6 236 580, May 2001. [22] F. Z. Peng, "A generalized multilevel inverter topology with self voltage balancing," IEEE Trans. Ind. Applicat., vol. 37, pp. 611-618, 2001. 492 Copyright 2011-15. Vandana Publications. All Rights Reserved.
[23] W. A. Hill and C. D. Harbourt, "Performance of medium voltage multi-level inverters," Conf. Rec. IEEE- IAS Annu. Meeting, 1999, pp. 1186-92. [24] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, "Hybrid multilevel power conversion system: a competitive solution for high-power applications," IEEE Trans. Ind. Applicat., vol. 36, pp. 834-841, 2000. [25] Y.-S. Lai and F.-S. Shyu, "Topology for hybrid multilevel inverter," IEE Proc. Electr. Power Applicat., vol. 149, pp. 449-458, 2002. [26] B.-M. Song, J. Kim, J.-S. Lai, K.-C. Seong, H.-J. Kim, and S.-S. Park, "A multilevel soft switching inverter with inductor coupling," IEEE Trans. Ind. Applicat., vol. 37, pp. 628-36, 2001. [27] E. Cengelci, S. U. Sulistijo, B. O. Woom, P. Enjeti, R. Teodorescu, and F. Blaabjerg, A New Medium Voltage PWM Inverter Topology for Adjustable Speed Drives, in Conf. Rec. IEEE-IAS Annu. Meeting, St. Louis, MO, Oct. 1998, pp. 1416-1423. [28] P. Jahn, and H. Leichtfried: Traction equipment of the class 1822 dual-system locomotive, ABB Rev., 1992, (4), pp. 15-22. [29] A. Nabae, I. Takahashi, and H. Akagi, A new neutral point clamped PWM inverter, ZEEE Trans., 1981, 1A-17, (5), pp.518-523. [30] N. G. Hingorani and L. Gyugyi, "Understanding FACTS", IEEE Press, 2000 [31] Rodriguez, J.; Jih-Sheng Lai; Fang Zheng Peng;, "Multilevel inverters: a survey of topologies, controls, and applications," Industrial Electronics, IEEE Transactions on, vol.49, no.4, pp. 724-738, Aug 2002 doi: 10.1109/TIE.2002.801052 [32] Jih-Sheng Lai; Fang Zheng Peng;, "Multilevel converters-a new breed of power converters," Industry Applications, IEEE Transactions on, vol.32, no.3, pp.509-517, May/Jun 1996 doi: 10.1109/28.502161 [33] Singh P., Tiwari, S., "A New Transistor Clamped 5- level H-bridge Multilevel Inverter with Voltage Boosting Capacity," IEEE Transaction on Power Electronics, Drives and Energy System(PEDES), 2012 international Conference on 16-19 Dec 2012. [34] AyoubKavousi, Behrooz Vahidi, Reza Salehi, Mohammad Kazem Bakhshizadeh," Application of the Bee Algorithm for Selective Harmonic Elimination Strategy inmultilevel Inverters" IEEE Transactions On Power Electronics, Vol. 27, No. 4, April 2012 [35] Jose Rodriguez, Jih-sheng lai, Fan zheng peng,, "Multilevel inverter: A survey of topologies, controls, and applications" IEEE transactions on industrial electronics, vol. 49,no.4,aug 2002. 493 Copyright 2011-15. Vandana Publications. All Rights Reserved.